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2026-01-28 - 08:19
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack7slot1.osadl.org (updated Wed Jan 28, 2026 00:45:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
10026211955,58sleep00-21swapper/019:07:180
10007210351,20sleep10-21swapper/119:07:041
999828860,23sleep20-21swapper/219:06:562
1001928658,23sleep30-21swapper/319:07:143
258742590,2sleep229400-21stress23:35:022
21512500,1sleep229399-21stress22:35:592
10332994017,20cyclictest0-21swapper/023:42:060
10332994011,27cyclictest0-21swapper/022:20:440
10332994011,27cyclictest0-21swapper/022:20:440
10332994010,27cyclictest0-21swapper/021:27:390
229532395,13sleep30-21swapper/320:54:213
207012395,13sleep30-21swapper/320:47:313
10335993925,12cyclictest0-21swapper/321:45:543
10335993925,12cyclictest0-21swapper/321:45:543
10335993911,25cyclictest0-21swapper/321:51:103
10335993911,25cyclictest0-21swapper/300:11:123
1033299399,28cyclictest0-21swapper/023:23:030
1033299399,27cyclictest0-21swapper/021:30:150
10332993917,19cyclictest0-21swapper/023:31:220
10332993915,21cyclictest0-21swapper/023:10:320
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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