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2025-08-29 - 14:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack7slot1.osadl.org (updated Fri Aug 29, 2025 12:45:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
744721360,1sleep125237-21stress09:41:031
1326521330,1sleep325237-21stress09:55:283
4837212259,58sleep30-21swapper/307:06:133
120421210,1sleep025237-21stress09:28:340
120421210,1sleep025237-21stress09:28:340
4806211652,59sleep20-21swapper/207:05:482
4815211552,23sleep10-21swapper/107:05:551
3061211353,54sleep00-21swapper/007:05:010
15662810,1sleep21567-21latency_hist09:30:022
5262994114,24cyclictest0-21swapper/212:38:342
5262994114,24cyclictest0-21swapper/212:28:552
5262994114,24cyclictest0-21swapper/212:28:552
5261994125,14cyclictest0-21swapper/109:36:131
5263994014,23cyclictest0-21swapper/311:50:113
5262994016,21cyclictest0-21swapper/210:17:592
5261994011,26cyclictest0-21swapper/112:30:441
5262993916,21cyclictest0-21swapper/209:47:172
526199394,24cyclictest0-21swapper/109:20:471
526199394,24cyclictest0-21swapper/109:20:471
5261993915,21cyclictest0-21swapper/110:36:031
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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