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2025-10-29 - 01:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack7slot1.osadl.org (updated Tue Oct 28, 2025 12:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30178211855,23sleep30-21swapper/307:06:573
30146211653,23sleep20-21swapper/207:06:312
28668211151,21sleep00-21swapper/007:05:250
2090121060,1sleep318890-21stress09:13:513
2090121060,1sleep318890-21stress09:13:503
2868628756,26sleep10-21swapper/107:05:391
30525996312,48cyclictest0-21swapper/012:25:330
3052599598,22cyclictest0-21swapper/012:24:000
3052599589,46cyclictest0-21swapper/011:53:320
3052599585,49cyclictest0-21swapper/009:25:360
30525995815,22cyclictest0-21swapper/012:04:190
30525995815,21cyclictest0-21swapper/011:59:230
3052599579,45cyclictest0-21swapper/011:10:380
3052599578,46cyclictest0-21swapper/011:25:150
30525995715,39cyclictest0-21swapper/012:05:250
30525995711,43cyclictest0-21swapper/009:44:300
30525995616,37cyclictest0-21swapper/011:20:300
30525995615,38cyclictest0-21swapper/011:30:350
30525995614,39cyclictest0-21swapper/010:34:500
30525995614,39cyclictest0-21swapper/010:34:500
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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