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2025-06-28 - 23:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack7slot1.osadl.org (updated Sat Jun 28, 2025 12:45:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
24732211452,23sleep10-21swapper/107:08:031
24716211151,55sleep00-21swapper/007:07:490
24729210950,20sleep30-21swapper/307:08:013
2461429668,23sleep20-21swapper/207:06:302
24981994710,20cyclictest0-21swapper/011:08:570
76092450,1sleep111615-21stress11:32:301
24981994216,23cyclictest0-21swapper/010:47:570
24983994116,22cyclictest0-21swapper/212:01:402
24983994116,22cyclictest0-21swapper/212:01:392
2498199419,29cyclictest0-21swapper/009:54:300
196752410,1sleep111617-21stress09:25:471
2498199399,27cyclictest0-21swapper/011:48:180
2498199399,27cyclictest0-21swapper/010:09:350
2498199398,28cyclictest0-21swapper/010:13:470
227372395,13sleep20-21swapper/208:18:412
24983993816,20cyclictest0-21swapper/209:35:272
24982993815,20cyclictest0-21swapper/110:22:131
2498199388,27cyclictest0-21swapper/010:31:590
24981993814,21cyclictest0-21swapper/011:38:070
224322380,1sleep111617-21stress12:08:171
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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