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2026-02-10 - 02:21
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack7slot1.osadl.org (updated Tue Feb 10, 2026 00:45:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19447211857,20sleep30-21swapper/319:06:043
19404211754,58sleep10-21swapper/119:05:291
1512021090,1sleep36719-21stress21:29:573
1966129166,20sleep20-21swapper/219:08:482
1941828354,24sleep00-21swapper/019:05:400
1985999576,36cyclictest0-21swapper/322:10:343
1985999576,36cyclictest0-21swapper/322:10:343
1985999536,22cyclictest0-21swapper/322:40:013
1985999535,34cyclictest0-21swapper/323:15:203
1985999527,41cyclictest0-21swapper/321:15:173
1985999516,42cyclictest0-21swapper/323:50:013
1985999515,36cyclictest0-21swapper/300:35:513
1985999515,24cyclictest0-21swapper/322:50:303
1985999507,39cyclictest0-21swapper/322:20:163
1985999506,41cyclictest0-21swapper/323:30:343
1985999506,41cyclictest0-21swapper/321:10:263
1985999506,22cyclictest0-21swapper/300:35:013
1985999496,39cyclictest0-21swapper/300:25:193
1985999496,22cyclictest0-21swapper/323:40:233
1985999496,22cyclictest0-21swapper/321:44:513
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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