You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-05-03 - 01:49
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack7slot1.osadl.org (updated Fri May 02, 2025 12:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2934329646,17sleep00-21swapper/007:05:150
3091129544,19sleep20-21swapper/207:05:412
2943429564,24sleep10-21swapper/107:05:151
3106129368,20sleep30-21swapper/307:07:303
284002560,1sleep121095-21stress10:35:421
284002560,1sleep121095-21stress10:35:421
31370995414,16cyclictest0-21swapper/011:04:090
31370995414,15cyclictest0-21swapper/011:11:010
31370995414,15cyclictest0-21swapper/011:11:000
31370995215,15cyclictest0-21swapper/012:15:160
284982520,1sleep021093-21stress10:36:540
284982520,1sleep021093-21stress10:36:540
3137099519,19cyclictest0-21swapper/010:40:300
31370995115,12cyclictest0-21swapper/009:20:290
31370995115,12cyclictest0-21swapper/009:20:290
31370995015,14cyclictest0-21swapper/009:55:210
31370995015,14cyclictest0-21swapper/009:55:200
31370995014,15cyclictest0-21swapper/010:21:290
31370995014,13cyclictest0-21swapper/011:50:320
31370995014,13cyclictest0-21swapper/011:50:310
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional