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2025-11-12 - 05:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack7slot1.osadl.org (updated Wed Nov 12, 2025 00:45:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
28163211353,21sleep00-21swapper/019:09:110
28072211350,58sleep20-21swapper/219:08:002
28098211251,56sleep30-21swapper/319:08:203
27890211151,21sleep10-21swapper/119:05:531
280942510,1sleep216864-21stress00:00:352
28346994314,26cyclictest0-21swapper/321:18:413
28343994112,26cyclictest0-21swapper/021:43:130
28343994021,16cyclictest0-21swapper/021:56:420
28343994021,16cyclictest0-21swapper/021:56:420
28343994011,26cyclictest0-21swapper/023:30:110
2834499399,27cyclictest0-21swapper/100:06:551
2834399399,27cyclictest0-21swapper/022:46:110
2834399399,27cyclictest0-21swapper/000:21:200
2834399399,27cyclictest0-21swapper/000:21:200
2834399398,28cyclictest0-21swapper/023:28:160
2834399398,28cyclictest0-21swapper/023:06:390
2834399398,28cyclictest0-21swapper/021:24:430
55692385,13sleep30-21swapper/320:42:233
28346993812,23cyclictest0-21swapper/322:40:293
28346993812,23cyclictest0-21swapper/321:25:583
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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