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2025-09-16 - 07:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack7slot1.osadl.org (updated Tue Sep 16, 2025 00:45:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
186521210,1sleep121690-21stress21:37:041
31904211551,58sleep30-21swapper/319:05:083
131929365,23sleep20-21swapper/219:09:332
123328456,23sleep10-21swapper/119:08:281
107528455,24sleep00-21swapper/019:06:340
146099536,44cyclictest0-21swapper/000:30:310
146099536,43cyclictest0-21swapper/022:00:330
146099536,43cyclictest0-21swapper/022:00:320
146099535,44cyclictest0-21swapper/023:20:150
146099516,39cyclictest0-21swapper/021:30:200
146099506,41cyclictest0-21swapper/022:30:190
146099506,21cyclictest0-21swapper/000:25:160
146099505,43cyclictest0-21swapper/023:49:030
146099505,42cyclictest0-21swapper/022:50:340
146099505,42cyclictest0-21swapper/022:40:590
146099505,42cyclictest0-21swapper/022:10:290
146099505,42cyclictest0-21swapper/021:35:140
146099505,42cyclictest0-21swapper/000:03:480
146099505,20cyclictest0-21swapper/023:10:370
146099496,39cyclictest0-21swapper/022:55:290
146099496,39cyclictest0-21swapper/022:55:280
146099496,21cyclictest0-21swapper/023:00:180
146099495,41cyclictest0-21swapper/023:45:000
146099495,41cyclictest0-21swapper/022:25:320
146099495,41cyclictest0-21swapper/021:55:270
146099495,41cyclictest0-21swapper/021:27:000
146099495,41cyclictest0-21swapper/021:20:270
146099495,41cyclictest0-21swapper/000:20:300
146099495,20cyclictest0-21swapper/023:15:210
146099495,20cyclictest0-21swapper/022:40:000
146099495,20cyclictest0-21swapper/021:50:170
146099495,20cyclictest0-21swapper/021:50:170
146099486,21cyclictest0-21swapper/023:50:190
146099485,41cyclictest0-21swapper/023:25:180
146099485,41cyclictest0-21swapper/023:25:180
146099485,40cyclictest0-21swapper/023:55:140
146099485,40cyclictest0-21swapper/022:45:160
146099485,40cyclictest0-21swapper/022:20:260
146099485,40cyclictest0-21swapper/022:20:260
146099485,40cyclictest0-21swapper/021:12:420
146099485,40cyclictest0-21swapper/000:35:200
146099485,40cyclictest0-21swapper/000:10:190
146099485,20cyclictest0-21swapper/022:15:280
146099485,20cyclictest0-21swapper/022:05:290
146099485,20cyclictest0-21swapper/021:15:270
146099485,20cyclictest0-21swapper/000:05:260
146099476,38cyclictest0-21swapper/023:05:140
146099475,39cyclictest0-21swapper/023:30:320
146099475,26cyclictest0-21swapper/021:04:200
146099475,26cyclictest0-21swapper/020:39:200
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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