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2026-02-01 - 16:43
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack7slot1.osadl.org (updated Sun Feb 01, 2026 12:45:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
23167211555,20sleep20-21swapper/207:08:592
2306229665,26sleep30-21swapper/307:07:383
2318629353,35sleep10-21swapper/107:09:131
122112850,4sleep3391rcuc/309:15:013
2298228355,23sleep00-21swapper/007:06:360
70132423,23sleep110080-21stress10:17:541
23349994115,23cyclictest0-21swapper/311:50:483
23349993914,23cyclictest0-21swapper/310:31:463
23349993914,23cyclictest0-21swapper/310:31:463
23348993914,22cyclictest0-21swapper/209:10:142
81562385,13sleep20-21swapper/209:05:102
324282385,13sleep30-21swapper/307:29:173
23349993814,22cyclictest0-21swapper/310:37:403
23349993814,21cyclictest0-21swapper/309:23:333
23349993814,21cyclictest0-21swapper/309:23:323
23349993812,23cyclictest0-21swapper/311:24:253
23348993815,20cyclictest0-21swapper/212:05:012
23348993810,25cyclictest0-21swapper/210:23:272
2334799388,27cyclictest0-21swapper/110:49:031
2334799387,28cyclictest0-21swapper/109:26:551
23346993815,20cyclictest0-21swapper/012:00:010
83052375,13sleep20-21swapper/207:46:522
82572375,13sleep10-21swapper/107:46:141
75552375,13sleep30-21swapper/309:00:423
71242375,13sleep20-21swapper/209:00:222
63522375,13sleep20-21swapper/207:43:432
35702375,13sleep10-21swapper/108:54:041
300722375,13sleep30-21swapper/307:21:073
295692375,13sleep30-21swapper/308:38:183
295132375,13sleep20-21swapper/208:37:332
293532375,13sleep10-21swapper/108:35:301
285392375,13sleep20-21swapper/207:20:092
280222375,13sleep10-21swapper/107:16:551
250932375,13sleep10-21swapper/107:10:571
23349993716,19cyclictest0-21swapper/311:45:553
23349993716,19cyclictest0-21swapper/311:45:543
23349993715,19cyclictest0-21swapper/311:12:033
23349993714,21cyclictest0-21swapper/311:27:013
23349993714,20cyclictest0-21swapper/310:51:253
23349993710,25cyclictest0-21swapper/312:10:223
23349993710,25cyclictest0-21swapper/309:48:133
23348993715,19cyclictest0-21swapper/210:00:172
23348993715,19cyclictest0-21swapper/210:00:172
23348993714,20cyclictest0-21swapper/210:07:242
23348993714,20cyclictest0-21swapper/209:47:222
23348993713,22cyclictest0-21swapper/212:30:352
23348993712,22cyclictest0-21swapper/212:30:012
23348993712,22cyclictest0-21swapper/212:30:002
23348993712,22cyclictest0-21swapper/211:30:112
23348993712,22cyclictest0-21swapper/210:15:262
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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