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2025-06-17 - 02:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack7slot1.osadl.org (updated Mon Jun 16, 2025 12:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2506321480,1sleep210672-21stress09:41:302
24014211552,23sleep10-21swapper/107:08:581
24014211552,23sleep10-21swapper/107:08:581
23903210951,20sleep00-21swapper/007:07:340
23903210951,20sleep00-21swapper/007:07:330
2403529567,23sleep20-21swapper/207:09:152
2403529567,23sleep20-21swapper/207:09:152
2381429365,23sleep30-21swapper/307:06:233
2381429365,23sleep30-21swapper/307:06:233
295382660,1sleep110672-21stress12:26:301
229682530,1sleep310674-21stress09:36:383
9492470,2sleep210672-21stress11:20:192
2419999446,26cyclictest0-21swapper/112:00:321
24199994412,22cyclictest0-21swapper/111:25:361
24199994412,22cyclictest0-21swapper/111:25:351
24198994311,29cyclictest0-21swapper/011:09:100
24198994311,23cyclictest0-21swapper/010:20:200
24199994213,21cyclictest0-21swapper/107:55:181
2419899428,26cyclictest0-21swapper/012:19:120
24198994216,23cyclictest0-21swapper/009:20:590
261912410,1sleep110674-21stress11:00:471
24199994113,25cyclictest0-21swapper/110:40:121
24199994113,25cyclictest0-21swapper/110:40:121
24199994110,20cyclictest0-21swapper/111:50:211
24199994110,20cyclictest0-21swapper/111:50:201
24198994111,27cyclictest0-21swapper/010:15:130
24198994110,28cyclictest0-21swapper/009:57:350
2419999406,21cyclictest0-21swapper/109:40:231
24199994010,21cyclictest0-21swapper/112:10:011
24199994010,21cyclictest0-21swapper/110:45:271
24199994010,21cyclictest0-21swapper/110:45:271
24198994012,25cyclictest0-21swapper/011:16:220
24198994011,26cyclictest0-21swapper/011:40:570
2420299398,28cyclictest0-21swapper/310:04:303
2419999395,32cyclictest0-21swapper/110:55:311
24199993916,16cyclictest0-21swapper/109:55:261
24199993914,22cyclictest0-21swapper/111:55:281
24199993914,22cyclictest0-21swapper/111:55:281
24199993914,22cyclictest0-21swapper/111:40:331
24199993911,20cyclictest0-21swapper/109:15:311
282502385,13sleep00-21swapper/008:34:220
2419999388,21cyclictest0-21swapper/109:35:281
24199993813,22cyclictest0-21swapper/111:35:181
24199993810,21cyclictest0-21swapper/107:36:541
24199993810,20cyclictest0-21swapper/112:30:171
24199993810,20cyclictest0-21swapper/112:30:161
24198993811,24cyclictest0-21swapper/011:20:080
238832385,13sleep00-21swapper/008:22:430
217992385,13sleep00-21swapper/008:17:590
90912375,13sleep20-21swapper/207:47:142
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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