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2025-12-05 - 20:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack7slot1.osadl.org (updated Fri Dec 05, 2025 12:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2073211754,23sleep30-21swapper/307:06:403
1940211652,58sleep20-21swapper/207:05:072
2045211454,21sleep00-21swapper/007:06:210
183828252,23sleep10-21swapper/107:05:021
2449996215,45cyclictest0-21swapper/312:16:183
2449996215,45cyclictest0-21swapper/312:16:183
2449996011,18cyclictest0-21swapper/310:55:403
2449995915,41cyclictest0-21swapper/310:43:223
2449995816,21cyclictest0-21swapper/312:14:303
2449995710,44cyclictest0-21swapper/310:06:403
244999549,42cyclictest0-21swapper/312:00:113
244999548,22cyclictest0-21swapper/312:25:283
2449995415,14cyclictest0-21swapper/309:45:033
2449995413,17cyclictest0-21swapper/311:40:273
2449995413,17cyclictest0-21swapper/311:40:273
244999536,25cyclictest0-21swapper/310:50:173
2449995314,36cyclictest0-21swapper/311:53:033
2449995310,40cyclictest0-21swapper/311:31:203
2449995214,16cyclictest0-21swapper/309:31:303
2449995115,15cyclictest0-21swapper/310:10:133
2449995114,16cyclictest0-21swapper/309:40:053
2449995015,15cyclictest0-21swapper/311:26:283
2449995014,14cyclictest0-21swapper/309:20:233
2449995012,16cyclictest0-21swapper/311:45:293
244999495,24cyclictest0-21swapper/310:25:183
244999495,24cyclictest0-21swapper/310:25:183
2449994914,14cyclictest0-21swapper/309:10:203
2449994913,18cyclictest0-21swapper/312:20:203
2449994813,12cyclictest0-21swapper/310:45:143
2449994810,19cyclictest0-21swapper/309:15:173
2449994810,19cyclictest0-21swapper/309:15:173
244999478,17cyclictest0-21swapper/311:55:183
244999475,23cyclictest0-21swapper/311:39:223
244999475,23cyclictest0-21swapper/307:11:223
2449994714,12cyclictest0-21swapper/312:35:143
2449994714,12cyclictest0-21swapper/309:25:153
2449994710,13cyclictest0-21swapper/310:30:343
2449994710,13cyclictest0-21swapper/310:30:333
244999468,19cyclictest0-21swapper/311:23:093
2449994614,12cyclictest0-21swapper/310:35:203
2449994613,14cyclictest0-21swapper/309:55:213
2449994613,14cyclictest0-21swapper/309:55:203
244999457,17cyclictest0-21swapper/310:05:023
244999456,23cyclictest0-21swapper/310:20:353
244999456,19cyclictest0-21swapper/311:19:183
244999456,19cyclictest0-21swapper/311:19:183
244999455,37cyclictest0-21swapper/311:00:163
244999455,21cyclictest0-21swapper/307:39:523
2449994510,15cyclictest0-21swapper/309:35:293
244999447,14cyclictest0-21swapper/312:30:203
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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