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2025-07-19 - 10:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack7slot1.osadl.org (updated Sat Jul 19, 2025 00:45:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1616529769,23sleep30-21swapper/319:06:513
1630729466,23sleep20-21swapper/219:08:382
1605828352,26sleep00-21swapper/019:05:360
1634328255,23sleep10-21swapper/119:09:061
106182730,2sleep210619-21timerwakeupswit22:40:352
76082720,3sleep13382-21stress21:20:001
16519997210,46cyclictest0-21swapper/023:46:370
1651999718,43cyclictest0-21swapper/000:20:260
16519997014,44cyclictest0-21swapper/000:05:300
16519996914,43cyclictest0-21swapper/023:05:000
244402660,1sleep03381-21stress21:58:490
16519996614,35cyclictest0-21swapper/023:50:230
1651999639,43cyclictest0-21swapper/000:35:160
1651999639,43cyclictest0-21swapper/000:35:160
1651999626,40cyclictest0-21swapper/023:20:350
16519996015,21cyclictest0-21swapper/023:40:160
16519995915,41cyclictest0-21swapper/021:30:160
16519995714,40cyclictest0-21swapper/022:45:230
16519995713,21cyclictest0-21swapper/022:50:190
1651999569,44cyclictest0-21swapper/022:25:480
1651999569,44cyclictest0-21swapper/021:16:070
1651999559,24cyclictest0-21swapper/021:50:210
1651999557,45cyclictest0-21swapper/000:31:420
1651999557,45cyclictest0-21swapper/000:31:420
16519995514,38cyclictest0-21swapper/022:37:550
16519995513,21cyclictest0-21swapper/021:28:470
16519995512,40cyclictest0-21swapper/022:58:190
1651999549,42cyclictest0-21swapper/000:16:530
1651999536,19cyclictest0-21swapper/023:35:180
1651999535,30cyclictest0-21swapper/023:30:200
16519995313,37cyclictest0-21swapper/022:30:130
16519995312,38cyclictest0-21swapper/022:00:110
1651999526,23cyclictest0-21swapper/000:00:300
1651999526,23cyclictest0-21swapper/000:00:300
1651999526,19cyclictest0-21swapper/023:25:170
1651999526,19cyclictest0-21swapper/023:25:170
16519995213,19cyclictest0-21swapper/023:17:240
1651999519,18cyclictest0-21swapper/021:45:160
1651999517,18cyclictest0-21swapper/022:05:260
1651999516,21cyclictest0-21swapper/022:20:140
1651999516,21cyclictest0-21swapper/020:20:220
1651999516,19cyclictest0-21swapper/023:05:310
16519995114,34cyclictest0-21swapper/000:25:150
1651999496,40cyclictest0-21swapper/023:10:140
1651999496,22cyclictest0-21swapper/020:05:060
1651999496,18cyclictest0-21swapper/021:40:110
1651999496,18cyclictest0-21swapper/021:40:110
16519994910,36cyclictest0-21swapper/022:15:210
16519994910,20cyclictest0-21swapper/021:05:160
16519994910,20cyclictest0-21swapper/021:05:160
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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