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2026-02-17 - 22:05
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackaslot8.osadl.org (updated Tue Feb 17, 2026 12:44:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
212152272242,20sleep10-21swapper/107:07:381
212722268237,20sleep20-21swapper/207:08:172
213002267206,18sleep00-21swapper/007:08:380
211972258227,20sleep30-21swapper/307:07:253
298212650,0sleep00-21swapper/010:00:150
298212650,0sleep00-21swapper/010:00:150
306482590,0sleep00-21swapper/009:40:370
220272590,1sleep20-21swapper/207:10:122
315502560,0sleep20-21swapper/209:41:182
149942560,0sleep00-21swapper/012:29:030
193912180,0sleep30-21swapper/310:53:283
268562170,0sleep20-21swapper/207:20:132
133552150,0sleep30-21swapper/308:00:173
252842140,0sleep10-21swapper/112:15:151
261922130,0sleep00-21swapper/012:35:150
104092130,0sleep20-21swapper/210:08:272
2152899129,2cyclictest34-21ksoftirqd/309:35:003
2152899125,5cyclictest34-21ksoftirqd/310:05:023
2152899125,5cyclictest34-21ksoftirqd/310:05:023
240202110,0sleep20-21swapper/209:36:502
2152899119,1cyclictest34-21ksoftirqd/312:00:013
2152899119,1cyclictest34-21ksoftirqd/312:00:013
21528991110,1cyclictest34-21ksoftirqd/311:40:013
21528991110,1cyclictest331rcuc/312:15:013
2152399119,2cyclictest28-21ksoftirqd/210:35:012
2152399111,2cyclictest28-21ksoftirqd/212:00:102
21523991110,1cyclictest28-21ksoftirqd/211:40:012
21523991110,1cyclictest28-21ksoftirqd/210:00:022
21523991110,1cyclictest28-21ksoftirqd/207:30:012
2152899108,1cyclictest34-21ksoftirqd/311:20:003
2152899107,2cyclictest34-21ksoftirqd/311:55:013
2152899107,2cyclictest34-21ksoftirqd/311:05:013
2152899107,2cyclictest34-21ksoftirqd/310:20:023
2152899107,2cyclictest34-21ksoftirqd/309:20:003
2152899102,4cyclictest34-21ksoftirqd/311:10:133
2152399109,1cyclictest28-21ksoftirqd/212:00:012
2152399109,1cyclictest28-21ksoftirqd/212:00:012
143622100,0sleep30-21swapper/310:10:203
2922290,3sleep334-21ksoftirqd/312:21:043
215289998,1cyclictest34-21ksoftirqd/307:25:013
215289997,2cyclictest34-21ksoftirqd/308:40:003
215289997,1cyclictest34-21ksoftirqd/312:29:593
215289997,1cyclictest34-21ksoftirqd/308:15:013
215289997,1cyclictest34-21ksoftirqd/307:15:003
215289996,2cyclictest34-21ksoftirqd/312:20:013
215289996,2cyclictest34-21ksoftirqd/311:00:013
215289992,5cyclictest34-21ksoftirqd/308:45:193
215289991,5cyclictest34-21ksoftirqd/310:40:193
215289990,6cyclictest0-21swapper/309:45:443
215289990,4cyclictest491-21systemd-logind10:49:463
215239998,1cyclictest28-21ksoftirqd/212:24:592
215239998,1cyclictest28-21ksoftirqd/208:39:592
215239997,1cyclictest28-21ksoftirqd/212:10:002
215239997,1cyclictest28-21ksoftirqd/210:05:022
215239997,1cyclictest28-21ksoftirqd/210:05:022
215239997,1cyclictest28-21ksoftirqd/207:55:002
215239997,1cyclictest271rcuc/211:20:002
215239997,1cyclictest271rcuc/209:55:022
215239994,3cyclictest275-21systemd-journal08:43:092
215239991,3cyclictest30383-21cut10:40:152
215199994,3cyclictest275-21systemd-journal08:05:011
588280,0sleep30-21swapper/309:22:463
28460280,2sleep1221ksoftirqd/108:35:151
215289987,1cyclictest34-21ksoftirqd/309:40:003
215289987,1cyclictest34-21ksoftirqd/308:30:003
215289986,2cyclictest34-21ksoftirqd/311:10:013
215289986,2cyclictest34-21ksoftirqd/310:40:003
215289986,1cyclictest34-21ksoftirqd/308:59:593
215289985,2cyclictest34-21ksoftirqd/312:00:013
215289985,2cyclictest34-21ksoftirqd/307:50:013
215289983,1cyclictest141rcu_preempt09:50:073
215289983,0cyclictest141rcu_preempt09:12:483
215289982,4cyclictest34-21ksoftirqd/308:20:213
215289982,3cyclictest34-21ksoftirqd/309:58:033
215289981,5cyclictest34-21ksoftirqd/311:40:173
215289981,4cyclictest34-21ksoftirqd/311:20:243
215289980,4cyclictest34-21ksoftirqd/308:15:123
215239987,1cyclictest28-21ksoftirqd/210:55:012
215239987,1cyclictest28-21ksoftirqd/210:40:012
215239987,1cyclictest28-21ksoftirqd/210:20:012
215239987,1cyclictest28-21ksoftirqd/208:20:012
215239987,1cyclictest28-21ksoftirqd/208:00:012
215239987,1cyclictest28-21ksoftirqd/207:40:012
215239987,1cyclictest28-21ksoftirqd/207:20:012
215239986,1cyclictest28-21ksoftirqd/207:50:002
215239983,3cyclictest275-21systemd-journal10:49:322
215239980,5cyclictest28-21ksoftirqd/211:30:192
215239980,3cyclictest11974-1kworker/u9:012:33:442
215199983,3cyclictest275-21systemd-journal07:15:101
215159982,3cyclictest27681-21munin-plugin-st09:19:590
215159980,7cyclictest26911-21ssh10:18:330
27526270,0sleep00-21swapper/012:16:260
215289976,1cyclictest34-21ksoftirqd/307:15:003
215289975,1cyclictest34-21ksoftirqd/308:54:593
215289974,2cyclictest34-21ksoftirqd/309:05:003
215289973,3cyclictest658-21snmpd08:40:013
215289973,1cyclictest141rcu_preempt10:06:153
215289973,1cyclictest141rcu_preempt09:26:103
215289972,4cyclictest331rcuc/310:30:173
215289972,3cyclictest34-21ksoftirqd/310:26:123
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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