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2026-03-03 - 00:43
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackaslot8.osadl.org (updated Mon Mar 02, 2026 12:44:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
306152314286,19sleep10-21swapper/107:05:581
306212277245,21sleep20-21swapper/207:06:032
309292275245,19sleep00-21swapper/007:09:590
307792256229,18sleep30-21swapper/307:08:053
28202660,0sleep20-21swapper/210:34:172
211902560,0sleep10-21swapper/112:01:371
59212550,0sleep30-21swapper/309:57:463
102682520,0sleep00-21swapper/010:00:150
274642190,0sleep00-21swapper/011:26:480
197202180,0sleep30-21swapper/312:39:473
3103099104,4cyclictest28-21ksoftirqd/210:42:452
3103099102,4cyclictest28-21ksoftirqd/211:11:002
3103099102,4cyclictest28-21ksoftirqd/210:54:412
3103099101,5cyclictest28-21ksoftirqd/211:20:212
3103099101,4cyclictest0-21swapper/210:20:012
3103099100,8cyclictest0-21swapper/211:05:242
3102799106,3cyclictest658-21snmpd11:44:371
310349998,1cyclictest34-21ksoftirqd/311:00:003
310349998,1cyclictest34-21ksoftirqd/309:20:003
310349998,1cyclictest34-21ksoftirqd/307:15:013
310349993,3cyclictest34-21ksoftirqd/308:53:443
310349992,5cyclictest34-21ksoftirqd/310:53:213
310349992,5cyclictest34-21ksoftirqd/310:49:363
310349992,5cyclictest34-21ksoftirqd/310:37:083
310349992,5cyclictest34-21ksoftirqd/307:35:153
310349991,6cyclictest34-21ksoftirqd/310:44:123
310349991,5cyclictest34-21ksoftirqd/309:40:193
310349991,4cyclictest34-21ksoftirqd/312:15:013
310349990,7cyclictest34-21ksoftirqd/311:29:433
310309992,5cyclictest28-21ksoftirqd/211:04:352
310309992,5cyclictest28-21ksoftirqd/210:15:432
310309992,4cyclictest28-21ksoftirqd/211:45:012
310309992,4cyclictest28-21ksoftirqd/210:35:542
310309992,4cyclictest28-21ksoftirqd/209:35:582
310309992,4cyclictest12034-21kworker/2:212:02:162
310309992,4cyclictest0-21swapper/210:57:082
310309991,5cyclictest28-21ksoftirqd/212:35:382
310309991,5cyclictest28-21ksoftirqd/211:50:482
310309991,5cyclictest28-21ksoftirqd/210:28:282
310309991,5cyclictest28-21ksoftirqd/209:22:572
310309991,5cyclictest0-21swapper/210:45:102
310309991,5cyclictest0-21swapper/209:52:512
310349987,1cyclictest34-21ksoftirqd/311:00:013
310349983,3cyclictest34-21ksoftirqd/312:01:153
310349983,1cyclictest141rcu_preempt10:17:253
310349982,4cyclictest663-21runrttasks07:15:523
310349982,4cyclictest5718-21ssh11:14:303
310349982,4cyclictest5446-21ssh12:30:283
310349982,4cyclictest34-21ksoftirqd/312:25:183
310349982,4cyclictest34-21ksoftirqd/311:50:133
310349982,4cyclictest34-21ksoftirqd/309:50:083
310349982,4cyclictest34-21ksoftirqd/309:45:383
310349982,4cyclictest34-21ksoftirqd/309:21:013
310349982,4cyclictest34-21ksoftirqd/308:36:383
310349982,4cyclictest34-21ksoftirqd/308:10:153
310349982,4cyclictest34-21ksoftirqd/307:20:183
310349982,4cyclictest31949-21ssh11:30:023
310349982,4cyclictest31272-21ssh09:35:003
310349982,4cyclictest28539-21ssh10:10:273
310349982,4cyclictest24459-21ssh11:05:283
310349982,4cyclictest23168-21ssh09:10:293
310349982,4cyclictest19924-21ssh10:05:333
310349982,4cyclictest19636-21ssh10:25:073
310349982,4cyclictest19027-21ssh12:20:013
310349982,4cyclictest11231-21ssh11:55:283
310349982,4cyclictest10392-21ssh11:35:473
310349982,3cyclictest34-21ksoftirqd/312:10:063
310349982,3cyclictest141rcu_preempt10:30:183
310349981,5cyclictest34-21ksoftirqd/312:08:513
310349981,5cyclictest34-21ksoftirqd/311:41:263
310349981,5cyclictest34-21ksoftirqd/310:00:113
310349981,5cyclictest34-21ksoftirqd/309:32:073
310349981,5cyclictest14121-21ssh10:21:093
310349981,4cyclictest34-21ksoftirqd/311:45:313
310349981,4cyclictest34-21ksoftirqd/311:20:333
310349981,1cyclictest141rcu_preempt08:00:203
310349980,6cyclictest0-21swapper/309:25:383
310309987,1cyclictest271rcuc/209:40:012
310309983,1cyclictest141rcu_preempt12:10:162
310309982,4cyclictest28-21ksoftirqd/210:00:102
310309982,4cyclictest0-21swapper/209:57:102
310309982,1cyclictest141rcu_preempt12:25:372
310309981,5cyclictest28-21ksoftirqd/211:16:062
310309981,5cyclictest28-21ksoftirqd/209:45:532
310309981,5cyclictest28-21ksoftirqd/209:25:042
310309981,5cyclictest28-21ksoftirqd/209:15:242
310309981,5cyclictest28-21ksoftirqd/209:10:332
310309981,5cyclictest0-21swapper/211:43:362
310309981,5cyclictest0-21swapper/211:35:052
310309981,5cyclictest0-21swapper/210:07:262
310309981,4cyclictest28-21ksoftirqd/212:15:242
310309981,4cyclictest28-21ksoftirqd/211:55:382
310309981,4cyclictest28-21ksoftirqd/211:31:242
310309981,4cyclictest28-21ksoftirqd/209:30:052
310309981,4cyclictest28-21ksoftirqd/207:35:092
310309981,4cyclictest0-21swapper/212:30:442
310309981,4cyclictest0-21swapper/211:25:252
310309981,4cyclictest0-21swapper/210:11:212
310309981,1cyclictest28-21ksoftirqd/212:20:192
310309980,7cyclictest27417-21ssh12:05:172
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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