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2026-04-10 - 07:50

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #a, slot #8

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackaslot8s.osadl.org (updated Fri Apr 10, 2026 00:45:16)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
277472178164,8sleep10-21swapper/119:08:571
27688217298,25sleep20-21swapper/219:08:102
3044621640,1sleep30-21swapper/322:56:513
275882144103,34sleep30-21swapper/319:06:543
277012138101,25sleep00-21swapper/019:08:210
257792780,1sleep00-21swapper/021:40:470
267422700,2sleep10-21swapper/122:54:521
66572660,1sleep00-21swapper/021:50:420
208202610,2sleep00-21swapper/023:38:220
107252600,2sleep20-21swapper/221:30:192
7782590,1sleep00-21swapper/000:11:120
218232590,2sleep00-21swapper/021:38:340
129112570,2sleep10-21swapper/123:32:091
129112570,2sleep10-21swapper/123:32:081
104902570,1sleep10-21swapper/122:41:561
70982550,1sleep10-21swapper/123:51:551
302142530,1sleep10-21swapper/122:56:371
116762530,2sleep30-21swapper/322:19:283
240552510,1sleep20-21swapper/200:05:122
239292510,2sleep20-21swapper/222:28:172
321682500,1chrt0-21swapper/121:45:301
309512500,2sleep20-21swapper/200:34:252
52532490,2chrt0-21swapper/100:39:261
206032480,1sleep20-21swapper/220:05:192
54442450,1sleep00-21swapper/022:14:540
300822450,2sleep00-21swapper/021:20:200
12902450,1sleep20-21swapper/222:10:432
34662440,1sleep30-21swapper/319:25:233
65932430,2chrt0-21swapper/022:39:470
63712430,1sleep30-21swapper/300:15:243
15642400,1sleep30-21swapper/300:35:433
92982320,2chrt0-21swapper/100:18:041
2810399303,19cyclictest4650-21ssh21:50:112
314312290,2sleep00-21swapper/023:21:360
2810399296,11cyclictest28-21ksoftirqd/221:37:332
2810399296,10cyclictest28-21ksoftirqd/221:47:502
265982290,2sleep20-21swapper/222:05:252
2810399288,9cyclictest28-21ksoftirqd/223:32:192
2810399288,9cyclictest28-21ksoftirqd/223:32:192
2810399278,4cyclictest28-21ksoftirqd/221:21:022
2810399276,10cyclictest28-21ksoftirqd/223:58:352
2810399274,12cyclictest28-21ksoftirqd/221:25:242
2810399271,24cyclictest0-21swapper/219:10:482
28103992711,4cyclictest28-21ksoftirqd/223:03:012
28103992710,4cyclictest28-21ksoftirqd/221:43:082
2810399266,10cyclictest28-21ksoftirqd/222:51:012
2810399265,9cyclictest28-21ksoftirqd/200:16:052
2810399262,8cyclictest28-21ksoftirqd/200:25:012
2810399261,7cyclictest28-21ksoftirqd/223:15:242
2810299261,24cyclictest0-21swapper/119:10:361
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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