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2026-02-22 - 22:59
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

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Default latency plot of shadow in rack #a, slot #8

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackaslot8s.osadl.org (updated Sun Feb 22, 2026 12:45:20)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17217217198,24sleep20-21swapper/207:09:472
153242152101,25sleep00-21swapper/007:05:050
170422150113,26sleep30-21swapper/307:07:323
169112142106,24sleep10-21swapper/107:05:491
265312630,1sleep20-21swapper/211:00:372
47542620,8sleep012-21ksoftirqd/009:57:260
325902580,4sleep232564-21awk11:05:212
277752580,2sleep30-21swapper/307:30:273
27352580,2sleep30-21swapper/311:31:163
27352580,2sleep30-21swapper/311:31:163
224112580,2sleep00-21swapper/009:22:260
49892560,2sleep20-21swapper/210:20:592
37842550,2sleep20-21swapper/209:05:222
265282510,2sleep00-21swapper/012:13:370
258652510,2sleep10-21swapper/112:36:431
308142500,2sleep00-21swapper/009:52:490
112982500,4sleep0131rcuc/010:50:150
98272460,1sleep00-21swapper/008:05:170
209272460,2sleep30-21swapper/311:45:153
9442430,1sleep20-21swapper/211:30:172
9442430,1sleep20-21swapper/211:30:172
287192420,1sleep00-21swapper/012:15:150
128352420,2chrt0-21swapper/112:03:241
85472410,3chrt0-21swapper/312:24:373
70682410,1chrt0-21swapper/310:23:053
137422360,4sleep2271rcuc/212:28:052
17509993227,3cyclictest271rcuc/209:24:412
318802310,12sleep122-21ksoftirqd/110:17:131
1750999306,10cyclictest28-21ksoftirqd/211:18:522
309052290,2sleep30-21swapper/309:29:113
17509992910,12cyclictest28-21ksoftirqd/209:10:482
1750999281,5cyclictest28-21ksoftirqd/212:15:002
257052270,2sleep20-21swapper/211:25:052
248232270,2sleep10-21swapper/112:11:551
197202270,1sleep00-21swapper/012:08:330
1750999279,11cyclictest28-21ksoftirqd/212:03:132
305522260,2sleep30-21swapper/311:52:093
1750999268,10cyclictest28-21ksoftirqd/209:28:012
1750999263,8cyclictest28-21ksoftirqd/211:20:192
1750999263,10cyclictest28-21ksoftirqd/211:58:112
17509992622,3cyclictest271rcuc/212:32:502
1750899262,19cyclictest662-21kworker/u8:111:30:131
1750899262,19cyclictest662-21kworker/u8:111:30:121
1750899261,24cyclictest0-21swapper/107:10:441
36072250,2sleep00-21swapper/009:32:330
1750999257,9cyclictest28-21ksoftirqd/209:32:142
1750999257,11cyclictest28-21ksoftirqd/209:17:002
1750999255,11cyclictest28-21ksoftirqd/212:05:312
1750999254,7cyclictest28-21ksoftirqd/210:41:492
1750999253,9cyclictest28-21ksoftirqd/211:13:532
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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