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2026-11-10 - 23:12

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #b, slot #2

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackbslot2s.osadl.org (updated Tue Nov 10, 2026 12:45:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
10198699592,56cyclictest0-21swapper/310:48:207
10198699572,48cyclictest0-21swapper/310:14:247
17424725310,9sleep120-21swapper/1209:22:424
17424725310,9sleep120-21swapper/1209:22:414
10199599531,45cyclictest0-21swapper/511:20:209
10198699533,17cyclictest0-21swapper/310:40:377
10198699523,42cyclictest0-21swapper/312:39:557
10198699522,40cyclictest0-21swapper/312:01:027
10198699522,40cyclictest0-21swapper/312:01:017
10198699512,40cyclictest0-21swapper/310:00:187
10198699512,16cyclictest0-21swapper/310:35:007
10198699512,16cyclictest0-21swapper/309:54:347
4084342504,14sleep70-21swapper/711:07:1811
4084342504,14sleep70-21swapper/711:07:1811
10199599501,40cyclictest0-21swapper/509:22:069
10199599501,40cyclictest0-21swapper/509:22:059
10198699503,40cyclictest0-21swapper/311:41:077
10198699503,39cyclictest0-21swapper/311:30:257
3633712494,4sleep120-21swapper/1210:46:494
10198699493,40cyclictest0-21swapper/309:26:377
10198699492,41cyclictest0-21swapper/309:42:017
10198699492,23cyclictest0-21swapper/311:26:317
10198699492,16cyclictest0-21swapper/311:01:047
22031824815,9sleep90-21swapper/909:44:5113
10199599481,40cyclictest0-21swapper/508:06:479
10199599481,29cyclictest0-21swapper/510:31:239
10198699483,16cyclictest0-21swapper/308:00:547
10198699482,9cyclictest0-21swapper/309:45:137
10198699482,45cyclictest0-21swapper/310:39:597
10198699482,45cyclictest0-21swapper/309:16:577
10198699482,19cyclictest0-21swapper/311:05:467
10198699482,19cyclictest0-21swapper/311:05:457
10198699482,17cyclictest0-21swapper/310:20:587
10198699482,16cyclictest0-21swapper/308:20:377
101986994811,14cyclictest0-21swapper/309:10:157
101978994811,23cyclictest366-21jbd2/nvme0n1p2-811:40:591
10198699473,4cyclictest0-21swapper/307:20:587
10198699473,3cyclictest0-21swapper/309:20:477
10198699473,3cyclictest0-21swapper/309:20:477
10198699472,33cyclictest0-21swapper/309:00:477
10198699472,16cyclictest0-21swapper/312:32:007
2643502464,9sleep70-21swapper/710:03:5711
10199599461,38cyclictest0-21swapper/509:35:049
10199599461,38cyclictest0-21swapper/509:15:219
10199599461,37cyclictest0-21swapper/511:25:179
10199599461,34cyclictest0-21swapper/510:35:069
10199599461,21cyclictest0-21swapper/509:42:299
10198699464,17cyclictest0-21swapper/308:40:277
10198699463,37cyclictest0-21swapper/310:52:447
10198699463,30cyclictest0-21swapper/311:53:207
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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