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2026-02-14 - 04:01
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Sat Feb 14, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2508621750,5sleep92732299cyclictest00:40:2915
2982821420,2sleep10-21swapper/122:47:291
26611212792,30sleep50-21swapper/519:07:4511
567821240,3sleep125682-21sshd22:57:504
3049721220,2sleep80-21swapper/821:55:2614
266082122106,12sleep20-21swapper/219:07:428
26634212095,19sleep90-21swapper/919:08:0515
1263321200,1sleep70-21swapper/723:54:4313
1263321200,1sleep70-21swapper/723:54:4313
266392115103,6sleep120-21swapper/1219:08:084
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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