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2026-03-15 - 01:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Sat Mar 14, 2026 00:43:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
140882131115,10sleep00-21swapper/019:06:500
38621280,1sleep80-21swapper/821:45:1514
14299212895,28sleep100-21swapper/1019:09:412
141972121105,12sleep10-21swapper/119:08:121
142532118104,9sleep20-21swapper/219:09:018
14322211391,18sleep140-21swapper/1419:10:016
14296211390,18sleep90-21swapper/919:09:4015
2314221120,4sleep41490099cyclictest22:14:2110
2314221120,4sleep41490099cyclictest22:14:2110
14316211191,15sleep80-21swapper/819:09:5514
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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