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2026-07-10 - 13:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Fri Jul 10, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1172821720,0sleep100-21swapper/1021:24:312
128921550,7sleep91677999cyclictest22:34:5015
2047421330,0sleep00-21swapper/022:45:550
2792621220,1sleep30-21swapper/322:40:219
160262120104,12sleep140-21swapper/1419:06:386
1503121160,2sleep51677299cyclictest22:20:2011
15977211191,16sleep40-21swapper/419:05:5610
210521080,1sleep00-21swapper/022:31:450
16328210894,10sleep120-21swapper/1219:10:044
2978021060,1sleep20-21swapper/222:34:278
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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