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2026-07-13 - 14:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Mon Jul 13, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
399221800,3sleep12701799cyclictest23:27:224
399221800,3sleep12701799cyclictest23:27:224
1655621540,5sleep12701799cyclictest00:29:414
2021921450,6sleep0700099cyclictest21:42:040
3198421390,0sleep30-21swapper/300:08:419
5344212691,28sleep100-21swapper/1019:05:332
63972124103,17sleep130-21swapper/1319:08:175
63472122103,15sleep140-21swapper/1419:07:296
6249212190,26sleep110-21swapper/1119:06:063
6428211493,17sleep60-21swapper/619:08:4212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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