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2025-11-26 - 00:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Tue Nov 25, 2025 00:43:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3124021420,2sleep3391rcuc/300:40:039
210932132102,25sleep140-21swapper/1419:10:146
210932132102,25sleep140-21swapper/1419:10:146
20962212690,31sleep40-21swapper/419:08:4410
20962212690,31sleep40-21swapper/419:08:4410
2356721230,7sleep112178199cyclictest23:17:323
212772115102,9sleep150-21swapper/1519:12:077
212772115102,9sleep150-21swapper/1519:12:077
20986211592,18sleep20-21swapper/219:08:588
20986211592,18sleep20-21swapper/219:08:588
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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