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2025-06-29 - 00:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Sat Jun 28, 2025 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
80442135120,10sleep60-21swapper/619:09:4712
78172130104,21sleep140-21swapper/1419:07:156
11390991250,112rtkit-daemon0-21swapper/1319:08:115
80842120104,11sleep70-21swapper/719:10:2013
609821160,2sleep882-21ksoftirqd/819:05:4714
7850211588,23sleep110-21swapper/1119:07:443
2946021140,5sleep774-21ksoftirqd/721:44:2113
1435821100,6sleep3855699cyclictest22:26:169
2202321080,1sleep30-21swapper/319:25:469
7968210689,13sleep00-21swapper/019:09:250
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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