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2026-04-30 - 19:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Thu Apr 30, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3078621850,24sleep131189999cyclictest23:09:285
1852421770,4sleep151190199cyclictest21:35:387
11054213395,33sleep30-21swapper/319:07:509
3064521270,5sleep111189699cyclictest23:44:133
112702124104,16sleep140-21swapper/1419:10:586
11093212492,27sleep20-21swapper/219:08:228
110912123102,17sleep00-21swapper/019:08:200
110922121103,13sleep10-21swapper/119:08:211
11104211990,25sleep120-21swapper/1219:08:324
11247211784,28sleep90-21swapper/919:10:3715
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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