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2026-01-13 - 17:18
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Tue Jan 13, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1413121850,6sleep32566099cyclictest22:56:469
248912127105,18sleep00-21swapper/019:06:290
24944211892,21sleep140-21swapper/1419:07:166
249292117103,9sleep10-21swapper/119:07:031
738821140,0sleep60-21swapper/623:56:2812
2957921120,1sleep90-21swapper/923:17:1215
1319521110,0sleep00-21swapper/021:18:020
1854321070,1sleep120-21swapper/1200:17:104
1854321070,1sleep120-21swapper/1200:17:104
25216210692,10sleep150-21swapper/1519:10:137
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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