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2026-07-31 - 20:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Fri Jul 31, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
634821280,1sleep06329-21sshd00:19:500
634821280,1sleep06329-21sshd00:19:500
285372125103,18sleep130-21swapper/1319:07:595
285372125103,18sleep130-21swapper/1319:07:595
284082123101,17sleep110-21swapper/1119:06:213
284082123101,17sleep110-21swapper/1119:06:213
953521120,0sleep140-21swapper/1400:30:306
28567211292,15sleep90-21swapper/919:08:2715
28567211292,15sleep90-21swapper/919:08:2715
2520221070,1sleep100-21swapper/1021:30:262
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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