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2026-04-04 - 00:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Fri Apr 03, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1942221870,6sleep43230199cyclictest23:25:3010
1412521400,3sleep93230999cyclictest23:55:3315
1532421210,1sleep40-21swapper/423:04:0710
1451521180,3sleep43230199cyclictest21:56:1010
1225521180,1sleep110-21swapper/1121:52:173
2895721150,5sleep13229299cyclictest22:17:471
1199121090,0sleep140-21swapper/1421:49:076
31559210592,8sleep80-21swapper/819:10:1214
2084121040,0sleep10-21swapper/121:16:321
2804721010,2sleep101041-21dbus-daemon22:44:412
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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