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2026-06-19 - 01:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Thu Jun 18, 2026 00:43:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
228652140115,21sleep50-21swapper/519:11:4711
226662132106,21sleep100-21swapper/1019:08:552
865321220,0sleep140-21swapper/1400:19:276
3134221140,2sleep141041-21dbus-daemon22:13:456
226462114104,6sleep70-21swapper/719:08:3613
2140721130,1sleep70-21swapper/722:19:3113
1041321120,0sleep30-21swapper/322:18:239
148321110,7sleep112343799cyclictest23:46:313
1927921100,7sleep52342899cyclictest23:15:2311
394521070,1sleep123950-21kworker/u34:123:10:414
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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