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2026-02-04 - 09:31
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Wed Feb 04, 2026 00:43:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2905721530,5sleep21574199cyclictest21:48:538
1839621490,4sleep21574199cyclictest00:03:578
685721400,6sleep81574899cyclictest22:09:1914
685721400,6sleep81574899cyclictest22:09:1914
15000212391,28sleep90-21swapper/919:06:5815
151392122103,14sleep10-21swapper/119:08:591
1683621160,1sleep60-21swapper/623:08:2312
15117211691,21sleep140-21swapper/1419:08:406
150442116102,10sleep150-21swapper/1519:07:367
700821110,1sleep30-21swapper/321:46:469
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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