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2026-02-08 - 11:50
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Sun Feb 08, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3168721680,4sleep9278799cyclictest21:19:0615
3168721680,4sleep9278799cyclictest21:19:0615
19882140104,31sleep150-21swapper/1519:07:077
22722125106,15sleep70-21swapper/719:10:1213
1005521170,2sleep140-21swapper/1421:26:406
2938421150,0sleep130-21swapper/1300:37:215
1963211385,23sleep00-21swapper/019:06:520
1063221130,6sleep14279499cyclictest23:01:056
1269121110,1sleep20-21swapper/223:24:098
2206221080,5sleep0277399cyclictest22:00:080
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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