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2026-03-21 - 23:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Sat Mar 21, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2032621370,0sleep150-21swapper/1522:23:447
199092136116,15sleep130-21swapper/1319:07:105
1835821320,4sleep142074099cyclictest23:11:036
200492122107,11sleep100-21swapper/1019:08:592
199842119103,12sleep10-21swapper/119:08:021
2728021170,1sleep100-21swapper/1022:58:092
20071211690,21sleep110-21swapper/1119:09:163
2437721100,6sleep32072499cyclictest22:07:139
20265211092,14sleep70-21swapper/719:11:2113
19929210992,13sleep140-21swapper/1419:07:276
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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