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2026-05-04 - 18:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Mon May 04, 2026 00:43:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1156621780,4sleep72798399cyclictest19:29:5913
1591721340,1sleep60-21swapper/623:25:5212
131821240,1sleep00-21swapper/022:26:550
131821240,1sleep00-21swapper/022:26:550
2659421180,0sleep60-21swapper/600:00:3812
1957421140,1sleep90-21swapper/922:16:3815
1957421140,1sleep90-21swapper/922:16:3815
3232021130,1sleep10-21swapper/122:38:421
2671621130,0sleep30-21swapper/321:28:569
1761221120,1sleep90-21swapper/923:20:0215
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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