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2026-03-11 - 19:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Wed Mar 11, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2154921520,7sleep151978899cyclictest23:05:337
276121350,0sleep10-21swapper/121:57:391
383921290,0sleep10-21swapper/123:13:361
191212127113,9sleep30-21swapper/319:08:429
3097421230,5sleep151978899cyclictest21:11:537
190542122102,15sleep100-21swapper/1019:07:452
191702118102,12sleep150-21swapper/1519:09:267
2575321160,1sleep90-21swapper/921:30:4615
448021120,0sleep130-21swapper/1321:41:325
19158211191,16sleep40-21swapper/419:09:1510
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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