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2026-01-09 - 15:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Fri Jan 09, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1476221700,3sleep634499cyclictest23:22:2512
1476221700,3sleep634499cyclictest23:22:2512
2965221690,4sleep834999cyclictest21:18:5314
323452132115,13sleep100-21swapper/1019:10:032
2727521320,1sleep140-21swapper/1423:27:056
2727521320,1sleep140-21swapper/1423:27:056
321822121101,14sleep90-21swapper/919:08:2615
321812115104,7sleep80-21swapper/819:08:2514
320872113101,8sleep40-21swapper/419:07:1710
220721130,1sleep150-21swapper/1523:14:487
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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