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2026-02-22 - 18:13
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Sun Feb 22, 2026 00:43:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1516821860,4sleep151189199cyclictest00:02:347
102092151134,10sleep90-21swapper/919:06:2615
111902144127,13sleep110-21swapper/1119:08:373
111892134118,11sleep100-21swapper/1019:08:362
132721300,1sleep130-21swapper/1300:31:255
11210212792,30sleep140-21swapper/1419:08:566
110372127103,19sleep60-21swapper/619:06:3912
11352211490,20sleep130-21swapper/1319:10:155
850421110,1sleep158483-21sshd23:01:517
11149211192,14sleep80-21swapper/819:08:1814
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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