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2026-03-04 - 18:45
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Wed Mar 04, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
163921750,6sleep11507799cyclictest00:33:301
144022137118,14sleep10-21swapper/119:08:031
143052135103,27sleep80-21swapper/819:06:5014
144292122101,17sleep110-21swapper/1119:08:293
144282120103,12sleep100-21swapper/1019:08:282
3070621170,6sleep990-21ksoftirqd/921:44:2015
14427211493,14sleep90-21swapper/919:08:2715
3155621100,0sleep10-21swapper/123:57:071
1822321090,1sleep20-21swapper/223:29:198
14554210892,12sleep40-21swapper/419:10:1410
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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