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2026-09-18 - 10:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Fri Sep 18, 2026 00:43:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1448721830,6sleep152216599cyclictest00:11:587
1448721830,6sleep152216599cyclictest00:11:587
778421570,5sleep82215499cyclictest00:31:0614
214242136116,15sleep140-21swapper/1419:07:546
600921320,0sleep140-21swapper/1422:56:316
216182125102,19sleep90-21swapper/919:10:2915
1710221120,2sleep417101-21sshd23:34:3610
21619211192,13sleep100-21swapper/1019:10:302
1045521090,1sleep140-21swapper/1423:18:596
1259721070,1sleep10-21swapper/122:53:381
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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