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2026-09-03 - 06:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Thu Sep 03, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
799121380,0sleep00-21swapper/023:29:480
868621190,1sleep30-21swapper/322:25:079
3182821190,6sleep4207699cyclictest22:38:4710
2644221190,0sleep100-21swapper/1022:01:582
2644221190,0sleep100-21swapper/1022:01:582
302211789,21sleep90-21swapper/919:06:1715
2395121160,0sleep140-21swapper/1421:36:376
2828721150,0sleep60-21swapper/622:16:2112
1604121150,1sleep00-21swapper/021:46:330
1579211192,12sleep80-21swapper/819:10:1614
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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