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2026-04-09 - 12:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Thu Apr 09, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2110621550,0sleep70-21swapper/723:40:3913
234842146126,15sleep30-21swapper/319:09:579
3062321240,1sleep100-21swapper/1022:32:452
233692121103,10sleep120-21swapper/1219:08:144
23445212091,25sleep150-21swapper/1519:09:217
1302621150,1sleep100-21swapper/1020:52:122
23304211385,23sleep90-21swapper/919:07:2315
920621110,2sleep01-21systemd23:01:290
1243321110,1sleep110-21swapper/1121:52:553
1243321110,1sleep110-21swapper/1121:52:553
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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