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2026-08-22 - 01:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Fri Aug 21, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2375821510,7sleep61350599cyclictest00:15:2612
130432133118,10sleep130-21swapper/1319:10:425
130432133118,10sleep130-21swapper/1319:10:425
2506721220,5sleep71350699cyclictest23:43:5313
127402122102,15sleep110-21swapper/1119:07:113
127402122102,15sleep110-21swapper/1119:07:113
12893211792,21sleep100-21swapper/1019:09:182
12893211792,21sleep100-21swapper/1019:09:182
2914121150,1sleep150-21swapper/1500:16:077
2495621140,3sleep101351099cyclictest21:46:152
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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