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2026-02-18 - 17:18
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Wed Feb 18, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
646521540,6sleep143165799cyclictest23:38:246
2454521460,5sleep113165399cyclictest00:07:153
3228921390,6sleep113165399cyclictest23:44:143
311522135105,25sleep30-21swapper/319:10:179
30837212791,31sleep80-21swapper/819:06:3714
1952821210,0sleep40-21swapper/422:03:5010
31171211794,19sleep50-21swapper/519:10:3511
2464821140,1sleep140-21swapper/1421:38:036
1081321140,30sleep123165499cyclictest22:25:534
2779421130,1sleep30-21swapper/300:07:559
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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