You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-18 - 06:19
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Sun Jan 18, 2026 00:43:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
228812132117,11sleep130-21swapper/1319:08:235
229152123102,16sleep80-21swapper/819:08:5014
227902117103,9sleep110-21swapper/1119:07:173
1492521130,2sleep61041-21dbus-daemon21:53:1412
22789211190,16sleep100-21swapper/1019:07:162
716521100,1sleep50-21swapper/523:12:0711
2331421080,2sleep132358099cyclictest22:47:395
19519210893,10sleep50-21swapper/519:05:3411
1879221070,3sleep918794-21sshd23:35:4315
22955210491,9sleep140-21swapper/1419:09:286
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional