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2026-06-28 - 13:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Sun Jun 28, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1359321530,5sleep81028199cyclictest23:14:4614
95632127104,18sleep140-21swapper/1419:10:126
95632127104,18sleep140-21swapper/1419:10:126
2424721220,1sleep90-21swapper/923:23:0415
9649212094,21sleep70-21swapper/719:11:2513
9649212094,21sleep70-21swapper/719:11:2513
96812117103,9sleep20-21swapper/219:11:528
96812117103,9sleep20-21swapper/219:11:528
2414821130,4sleep91028399cyclictest00:10:5715
2414821130,4sleep91028399cyclictest00:10:5715
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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