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2026-06-03 - 17:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Wed Jun 03, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2696221600,4sleep91201399cyclictest23:02:2415
2069321360,0sleep110-21swapper/1123:07:473
2820121350,2sleep11200299cyclictest22:14:241
2301421310,3sleep31200699cyclictest21:45:179
668521160,1sleep10-21swapper/100:12:051
1467021130,0sleep150-21swapper/1523:20:097
11233211392,16sleep90-21swapper/919:08:2615
11226211381,27sleep20-21swapper/219:08:198
3247321120,7sleep51200899cyclictest21:58:5711
3247321120,7sleep51200899cyclictest21:58:5711
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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