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2026-05-12 - 10:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Tue May 12, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
647421410,1sleep100-21swapper/1023:08:492
1864521380,7sleep5744599cyclictest00:39:5611
1168521370,6sleep6744699cyclictest21:39:0912
1168521370,6sleep6744699cyclictest21:39:0912
2932621210,1sleep10-21swapper/121:56:271
6978211791,21sleep00-21swapper/019:11:440
6978211791,21sleep00-21swapper/019:11:440
66852116103,9sleep140-21swapper/1419:08:296
66852116103,9sleep140-21swapper/1419:08:296
6972211490,20sleep110-21swapper/1119:11:393
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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