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2026-06-12 - 20:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Fri Jun 12, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1614121560,3sleep12877499cyclictest23:08:444
1614121560,3sleep12877499cyclictest23:08:444
82092124103,16sleep140-21swapper/1419:11:356
79662124102,17sleep80-21swapper/819:08:1614
1459521240,2sleep114578-21sshd00:31:441
8120211895,19sleep00-21swapper/019:10:170
80672118103,10sleep90-21swapper/919:09:3715
505421150,3sleep9877199cyclictest23:27:2415
505421150,3sleep9877199cyclictest23:27:2415
3238021140,1sleep70-21swapper/721:27:0113
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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