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2026-08-06 - 22:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Thu Aug 06, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2152921780,5sleep102011599cyclictest00:00:432
2751521370,1sleep140-21swapper/1423:43:406
223821290,0sleep40-21swapper/422:24:2010
19464211089,16sleep30-21swapper/319:08:359
19546210992,9sleep110-21swapper/1119:09:483
19493210992,13sleep150-21swapper/1519:09:037
19474210691,10sleep130-21swapper/1319:08:455
2475021010,2sleep624744-21systemd23:08:3012
2475021010,2sleep624744-21systemd23:08:3012
1936921000,7sleep12010399cyclictest22:47:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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