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2025-05-09 - 05:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Fri May 09, 2025 00:43:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2330721630,2sleep82373499cyclictest20:33:1014
1940221470,6sleep62373199cyclictest23:52:2212
231732127105,16sleep150-21swapper/1519:16:337
222932119104,11sleep130-21swapper/1319:13:515
233092117103,10sleep50-21swapper/519:17:4411
233122116104,8sleep70-21swapper/719:17:4613
1097521150,1sleep130-21swapper/1322:35:125
23267211495,15sleep00-21swapper/019:17:060
590921130,1sleep40-21swapper/400:15:5210
3063421120,0sleep140-21swapper/1422:38:096
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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