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2026-02-15 - 19:00
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Sun Feb 15, 2026 00:43:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2024221530,6sleep72287899cyclictest21:51:1613
22240212492,27sleep100-21swapper/1019:09:012
262421230,1sleep30-21swapper/322:51:239
220632118102,11sleep140-21swapper/1419:06:416
903121150,2sleep90-21swapper/921:40:5215
2250321150,2sleep72287899cyclictest23:16:3513
22278211190,16sleep90-21swapper/919:09:3215
22089210787,15sleep60-21swapper/619:07:0512
1783921070,4sleep142288899cyclictest21:13:086
1783921070,4sleep142288899cyclictest21:13:086
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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