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2025-11-08 - 18:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Sat Nov 08, 2025 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
187012131117,9sleep90-21swapper/919:09:0015
187562128107,17sleep70-21swapper/719:09:3013
187892125106,14sleep10-21swapper/119:09:561
866421240,2sleep61351-21nfsd00:34:4012
18966211988,26sleep110-21swapper/1119:11:433
187932119103,12sleep50-21swapper/519:10:0011
433821180,1sleep30-21swapper/300:10:179
433821180,1sleep30-21swapper/300:10:179
18870211297,10sleep80-21swapper/819:11:0814
2721921080,1sleep00-21swapper/022:15:450
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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