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2025-08-27 - 21:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Wed Aug 27, 2025 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
6422131102,24sleep100-21swapper/1019:09:512
6692129102,22sleep120-21swapper/1219:10:094
590212494,26sleep140-21swapper/1419:09:076
5642124102,17sleep110-21swapper/1119:08:473
6952120103,13sleep00-21swapper/019:10:290
4022117109,4sleep80-21swapper/819:06:5214
566211390,19sleep130-21swapper/1319:08:495
1852221120,1sleep110-21swapper/1122:05:323
659210692,9sleep50-21swapper/519:10:0211
640921030,0sleep00-21swapper/021:41:170
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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