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2026-01-15 - 05:47
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Thu Jan 15, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2379921790,2sleep11013499cyclictest23:43:011
96642138117,16sleep150-21swapper/1519:10:147
96642138117,16sleep150-21swapper/1519:10:147
93972134117,13sleep50-21swapper/519:07:0811
93972134117,13sleep50-21swapper/519:07:0811
2077021290,0sleep40-21swapper/400:34:4110
93292127102,21sleep120-21swapper/1219:06:104
93292127102,21sleep120-21swapper/1219:06:104
95472120103,13sleep70-21swapper/719:09:1813
95472120103,13sleep70-21swapper/719:09:1813
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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