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2026-08-19 - 00:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Tue Aug 18, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
913721350,0sleep60-21swapper/600:28:1312
1327121320,7sleep62765699cyclictest00:12:5812
268832118103,11sleep90-21swapper/919:06:4915
269232117103,9sleep30-21swapper/319:07:159
1252521150,1sleep10-21swapper/123:49:531
27173211194,12sleep110-21swapper/1119:10:043
1594321110,1sleep70-21swapper/723:25:5413
1594321110,1sleep70-21swapper/723:25:5413
2894821090,1sleep40-21swapper/423:55:3310
1476421080,3sleep152766999cyclictest21:21:407
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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