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2026-08-28 - 03:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Thu Aug 27, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3096121740,7sleep72094599cyclictest21:51:2213
2660721460,7sleep82094799cyclictest22:07:2614
20190212791,31sleep10-21swapper/119:07:061
1451221210,1sleep12114-21ksoftirqd/1200:15:384
203752120103,13sleep00-21swapper/019:09:460
202532120105,11sleep90-21swapper/919:08:0215
204792115103,8sleep130-21swapper/1319:10:315
204802114103,6sleep140-21swapper/1419:10:326
20252211293,14sleep80-21swapper/819:08:0114
770621090,1sleep140-21swapper/1422:12:216
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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