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2026-05-03 - 18:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Sun May 03, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2663021450,0sleep100-21swapper/1021:40:572
282952131103,23sleep90-21swapper/919:09:3615
283822119104,10sleep60-21swapper/619:10:5312
282262119104,10sleep120-21swapper/1219:08:514
28195211293,15sleep150-21swapper/1519:08:227
28507210692,10sleep40-21swapper/419:11:5510
2679521060,1sleep20-21swapper/223:36:228
2679521060,1sleep20-21swapper/223:36:228
1026121060,1sleep30-21swapper/321:48:199
28515210592,8sleep110-21swapper/1119:12:023
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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