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2026-08-31 - 04:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Mon Aug 31, 2026 00:43:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1425321780,6sleep33077299cyclictest22:48:379
2607721390,0sleep90-21swapper/900:21:3215
2607721390,0sleep90-21swapper/900:21:3215
115321310,0sleep120-21swapper/1200:03:404
301612127106,15sleep30-21swapper/319:09:379
299422123104,15sleep10-21swapper/119:06:381
30182211894,18sleep40-21swapper/419:09:5410
30020211691,20sleep80-21swapper/819:07:3414
301662115103,8sleep70-21swapper/719:09:4113
301642115103,8sleep50-21swapper/519:09:3911
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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