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2026-07-22 - 17:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Wed Jul 22, 2026 00:43:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2697921860,4sleep112545899cyclictest23:59:513
2457121450,15sleep00-21swapper/019:05:460
2196221370,0sleep90-21swapper/923:16:4515
24668213092,33sleep20-21swapper/219:06:218
246692122103,14sleep30-21swapper/319:06:229
24983211990,25sleep150-21swapper/1519:10:027
24799211795,16sleep120-21swapper/1219:08:074
247952117102,11sleep80-21swapper/819:08:0314
24711211590,20sleep140-21swapper/1419:06:496
77821100,1sleep80-21swapper/822:26:2714
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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