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2026-03-19 - 00:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Wed Mar 18, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
239822119103,12sleep140-21swapper/1419:08:296
239822119103,12sleep140-21swapper/1419:08:296
2023321180,6sleep62469499cyclictest22:26:1312
1382021180,2sleep813798-21sshd23:39:4814
23914211792,20sleep90-21swapper/919:07:5215
23914211792,20sleep90-21swapper/919:07:5215
2108421100,1sleep90-21swapper/921:59:4715
24243210990,14sleep00-21swapper/019:11:110
24243210990,14sleep00-21swapper/019:11:110
24209210892,12sleep40-21swapper/419:10:4310
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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