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2026-04-28 - 09:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Tue Apr 28, 2026 00:43:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2533921870,4sleep9117199cyclictest21:13:4515
2533921870,4sleep9117199cyclictest21:13:4515
92021750,4sleep4116599cyclictest23:25:1610
3013921660,6sleep13117899cyclictest23:03:295
48521640,0sleep50-21swapper/521:07:1611
48521640,0sleep50-21swapper/521:07:1611
665921620,1sleep66658-21systemd-cgroups22:55:0412
325872131106,20sleep70-21swapper/719:08:5213
327092127111,11sleep110-21swapper/1119:10:323
326452125101,19sleep30-21swapper/319:09:369
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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