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2026-01-25 - 06:57
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Sun Jan 25, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1899521850,5sleep12299699cyclictest21:36:044
2606121390,3sleep5298699cyclictest00:07:0411
1177521330,0sleep140-21swapper/1423:01:416
61321270,0sleep00-21swapper/023:26:030
61321270,0sleep00-21swapper/023:26:030
577821260,2sleep105757-21sshd22:48:152
1311921260,27sleep11299499cyclictest22:39:263
21762125103,16sleep10-21swapper/119:06:571
1544821210,1sleep100-21swapper/1000:36:342
1461121170,2sleep150-21swapper/1522:10:537
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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