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2026-05-08 - 18:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Fri May 08, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
977921830,2sleep41195299cyclictest22:12:4710
756121790,4sleep91195999cyclictest23:15:1215
1784721410,6sleep21194999cyclictest22:07:088
1166321410,5sleep121196399cyclictest00:05:314
114192131116,10sleep140-21swapper/1419:11:086
901421290,5sleep01194799cyclictest21:17:210
111692122102,16sleep30-21swapper/319:07:459
11350212192,24sleep10-21swapper/119:10:071
11407212095,20sleep20-21swapper/219:10:568
112992116103,8sleep60-21swapper/619:09:2412
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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