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2026-05-22 - 11:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Fri May 22, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3234621730,5sleep22216699cyclictest23:15:148
926521320,4sleep132218199cyclictest23:12:445
2820721300,0sleep120-21swapper/1200:17:274
2820721300,0sleep120-21swapper/1200:17:274
3252321220,3sleep102217799cyclictest22:34:102
1386821220,2sleep140-21swapper/1400:01:106
21488211792,21sleep10-21swapper/119:09:441
21488211792,21sleep10-21swapper/119:09:441
1665421170,2sleep516641-21sshd23:39:2111
216632112101,7sleep120-21swapper/1219:11:314
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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