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2025-09-14 - 07:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Sun Sep 14, 2025 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1825921470,1sleep11765499cyclictest23:12:073
66692133105,23sleep00-21swapper/019:07:160
68602125104,16sleep20-21swapper/219:09:428
67412119102,10sleep130-21swapper/1319:08:175
69982117101,12sleep120-21swapper/1219:10:564
3558211492,17sleep30-21swapper/319:06:319
411021110,1sleep10-21swapper/122:46:491
590321080,1sleep40-21swapper/421:33:1910
53221010,1sleep130-21swapper/1323:53:215
2838421010,1sleep150-21swapper/1521:43:087
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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