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2025-12-30 - 19:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Tue Dec 30, 2025 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
670221350,2sleep06710-2110-uname22:10:010
276122130103,23sleep140-21swapper/1419:08:586
2467121120,2sleep21-21systemd22:27:588
2139721110,1sleep721398-2110-uname23:35:2713
2139721110,1sleep721398-2110-uname23:35:2713
27471210891,12sleep150-21swapper/1519:07:077
27725210687,15sleep00-21swapper/019:09:480
27457210691,11sleep60-21swapper/619:06:5812
2177621040,1sleep10-21swapper/122:05:131
27602210290,8sleep50-21swapper/519:08:4911
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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