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2026-08-15 - 23:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Sat Aug 15, 2026 00:43:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2885321410,7sleep01333099cyclictest23:26:440
126832140118,17sleep130-21swapper/1319:08:225
127072128103,20sleep30-21swapper/319:08:449
128082118102,10sleep100-21swapper/1019:10:122
12590211892,21sleep140-21swapper/1419:07:036
3085721160,2sleep130-21swapper/1319:30:495
3252421150,1sleep131201rcuc/1322:17:095
12618211491,18sleep40-21swapper/419:07:2510
12654211193,14sleep50-21swapper/519:07:5811
2646321100,6sleep141335199cyclictest22:16:226
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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