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2025-12-29 - 10:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Mon Dec 29, 2025 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
176082136119,13sleep100-21swapper/1019:10:102
172362125106,14sleep40-21swapper/419:05:4710
1005521230,2sleep80-21swapper/822:24:4714
174412118101,13sleep80-21swapper/819:08:3214
61221140,5sleep01806799cyclictest20:05:360
17483211495,14sleep120-21swapper/1219:09:084
17610211085,20sleep110-21swapper/1119:10:113
17563210791,11sleep30-21swapper/319:09:319
17311210692,9sleep20-21swapper/219:06:498
17277210692,10sleep70-21swapper/719:06:2213
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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