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2026-09-13 - 11:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Sun Sep 13, 2026 00:43:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1181721630,5sleep142076599cyclictest22:27:506
2823221380,0sleep30-21swapper/300:04:129
202932130103,23sleep10-21swapper/119:10:491
201222129116,8sleep110-21swapper/1119:09:073
2768521260,0sleep00-21swapper/023:05:510
2153021240,1sleep150-21swapper/1500:34:387
20208212492,27sleep60-21swapper/619:10:2212
1087421210,1sleep120-21swapper/1223:21:504
1249621190,0sleep120-21swapper/1222:02:244
20306211693,18sleep120-21swapper/1219:11:004
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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