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2026-07-19 - 15:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Sun Jul 19, 2026 00:43:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2102521370,5sleep152781099cyclictest21:46:417
272562130106,19sleep110-21swapper/1119:09:403
1806721240,1sleep30-21swapper/323:32:249
271832123107,11sleep120-21swapper/1219:08:374
272182122104,14sleep90-21swapper/919:09:0615
249122118104,7sleep20-21swapper/219:05:308
271672115104,6sleep130-21swapper/1319:08:225
27224211389,20sleep150-21swapper/1519:09:127
27154211195,12sleep00-21swapper/019:08:090
2472721090,1sleep00-21swapper/022:57:510
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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