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2026-09-22 - 12:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Tue Sep 22, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1773321350,4sleep133084399cyclictest22:53:215
1773321350,4sleep133084399cyclictest22:53:215
300082128114,10sleep10-21swapper/119:06:401
3260821200,1sleep00-21swapper/021:53:130
301002117103,10sleep90-21swapper/919:07:5215
30175211593,17sleep30-21swapper/319:08:509
1914421150,1sleep40-21swapper/423:26:2210
28943211388,18sleep70-21swapper/719:06:3013
30383211092,14sleep120-21swapper/1219:11:084
1329021100,0sleep140-21swapper/1400:02:396
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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