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2026-02-19 - 17:42
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Thu Feb 19, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2866921540,9sleep141368499cyclictest23:29:036
3032521480,6sleep11366699cyclictest21:57:061
3032521480,6sleep11366699cyclictest21:57:061
1345521420,0sleep70-21swapper/723:57:3313
128792134106,23sleep100-21swapper/1019:06:562
131862130103,23sleep60-21swapper/619:10:3612
13181212692,29sleep10-21swapper/119:10:311
129562121103,14sleep140-21swapper/1419:08:046
2624321180,2sleep71367599cyclictest21:24:1813
121802118102,11sleep150-21swapper/1519:06:297
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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