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2026-03-20 - 01:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Thu Mar 19, 2026 00:43:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
378721610,5sleep72667099cyclictest23:42:2013
378721610,5sleep72667099cyclictest23:42:2013
261682144111,28sleep110-21swapper/1119:10:593
2098321410,7sleep82667299cyclictest21:19:4814
756221260,0sleep80-21swapper/821:51:3814
259892124106,14sleep130-21swapper/1319:09:095
259182118104,10sleep150-21swapper/1519:08:077
26024211593,18sleep140-21swapper/1419:09:426
25986210891,12sleep100-21swapper/1019:09:062
172021080,1sleep60-21swapper/622:21:0112
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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