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2026-04-01 - 19:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Tue Mar 31, 2026 00:43:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20612125103,18sleep90-21swapper/919:09:2415
19302124104,16sleep40-21swapper/419:07:4210
3160921220,2sleep150-21swapper/1519:06:487
19242118101,10sleep20-21swapper/219:07:408
20032115102,8sleep80-21swapper/819:08:3414
2146211492,17sleep100-21swapper/1019:10:292
2803321120,0sleep80-21swapper/821:43:5514
282921100,1sleep110-21swapper/1121:58:253
282921100,1sleep110-21swapper/1121:58:253
2066210387,11sleep140-21swapper/1419:09:296
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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