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2026-08-12 - 23:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Wed Aug 12, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
205362137118,14sleep60-21swapper/619:07:1612
775621340,1sleep10-21swapper/123:52:301
204562129101,23sleep10-21swapper/119:06:061
206912126103,19sleep00-21swapper/019:09:340
1405421110,1sleep60-21swapper/622:58:0212
2481421100,0sleep90-21swapper/900:19:5515
2390421100,1sleep1023905-21systemd-cgroups22:38:182
2391121090,0sleep100-21swapper/1022:52:132
20607210990,14sleep50-21swapper/519:08:1911
574421080,6sleep152127199cyclictest23:55:577
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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