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2026-05-28 - 15:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Thu May 28, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
846121430,6sleep8212099cyclictest22:55:0414
14592119105,10sleep150-21swapper/1519:10:357
14592119105,10sleep150-21swapper/1519:10:357
2391821180,3sleep6211699cyclictest21:26:3112
1410121160,1sleep90-21swapper/922:03:4415
13352116102,9sleep30-21swapper/319:08:469
13352116102,9sleep30-21swapper/319:08:469
940321140,1sleep79407-21uname23:43:4413
16252114102,8sleep120-21swapper/1219:12:084
16252114102,8sleep120-21swapper/1219:12:084
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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