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2026-08-03 - 21:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Mon Aug 03, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
78821590,7sleep13365299cyclictest23:25:035
2259121390,6sleep0363399cyclictest22:55:400
1330521360,7sleep1363499cyclictest23:19:301
2040721300,2sleep020404-21sshd00:08:420
436921270,0sleep90-21swapper/922:15:1015
2928212491,26sleep40-21swapper/419:07:0510
2928212491,26sleep40-21swapper/419:07:0510
2953211890,21sleep70-21swapper/719:07:2413
2953211890,21sleep70-21swapper/719:07:2413
763721030,0sleep130-21swapper/1323:36:015
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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