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2026-03-23 - 02:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Sun Mar 22, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
247802127102,20sleep140-21swapper/1419:09:206
24685211192,14sleep100-21swapper/1019:08:112
979221080,2sleep39789-21sshd22:45:449
24742210893,10sleep20-21swapper/219:08:518
1998021080,0sleep30-21swapper/323:06:529
1998021080,0sleep30-21swapper/323:06:529
24744210592,9sleep40-21swapper/419:08:5310
2064321030,1sleep140-21swapper/1421:52:576
1708021030,1sleep40-21swapper/422:42:4810
1599121010,2sleep1115988-21sshd22:49:373
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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