You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-14 - 05:48
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Wed Jan 14, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
158072139125,9sleep30-21swapper/319:09:309
754521360,6sleep13122-21ksoftirqd/1322:53:125
156392119101,14sleep20-21swapper/219:07:048
1241521140,0sleep00-21swapper/021:15:380
392521120,1sleep150-21swapper/1522:08:027
392521120,1sleep150-21swapper/1522:08:027
15930211285,23sleep140-21swapper/1419:10:296
15689211092,14sleep150-21swapper/1519:07:497
1038021090,2sleep14130-21ksoftirqd/1423:57:416
1600021080,1sleep100-21swapper/1023:19:542
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional