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2026-05-07 - 18:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Thu May 07, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3210921400,7sleep81986599cyclictest21:52:1614
3210921400,7sleep81986599cyclictest21:52:1614
192382132105,22sleep100-21swapper/1019:10:002
192382132105,22sleep100-21swapper/1019:10:002
191512128103,20sleep00-21swapper/019:08:460
191512128103,20sleep00-21swapper/019:08:460
590221220,1sleep150-21swapper/1521:22:107
194022122104,13sleep130-21swapper/1319:11:405
194022122104,13sleep130-21swapper/1319:11:405
192422121103,13sleep140-21swapper/1419:10:046
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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