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2026-02-16 - 07:58
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Mon Feb 16, 2026 00:43:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
93321890,6sleep4146999cyclictest21:13:3210
93321890,6sleep4146999cyclictest21:13:3210
1646721690,5sleep4146999cyclictest22:42:0410
1888821440,5sleep9147599cyclictest22:36:0015
7152127104,19sleep130-21swapper/1319:08:025
6212126100,21sleep30-21swapper/319:06:489
3243921240,1sleep90-21swapper/900:02:5515
299272118103,10sleep70-21swapper/719:06:0313
2361021150,0sleep20-21swapper/223:12:318
7382113101,8sleep150-21swapper/1519:08:207
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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