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2026-05-02 - 04:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Sat May 02, 2026 00:43:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3223121780,6sleep42026099cyclictest21:30:2510
3223121780,6sleep42026099cyclictest21:30:2510
1198021400,5sleep92027099cyclictest00:21:2415
193872136119,12sleep140-21swapper/1419:08:046
194542123104,15sleep130-21swapper/1319:08:525
195542121102,15sleep20-21swapper/219:10:178
3034921170,7sleep22025799cyclictest21:42:098
193632117104,8sleep120-21swapper/1219:07:464
19450211390,18sleep90-21swapper/919:08:4815
1291021130,1sleep130-21swapper/1323:22:065
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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