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2026-02-17 - 08:56
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Tue Feb 17, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
203262147120,22sleep130-21swapper/1319:08:515
20352212395,23sleep10-21swapper/119:09:111
2883821180,1sleep10-21swapper/123:28:021
20378211895,18sleep90-21swapper/919:09:3515
1774821120,2sleep140-21swapper/1400:17:126
1462621110,1sleep30-21swapper/300:36:489
17066211085,18sleep100-21swapper/1019:06:072
3119621090,0sleep10-21swapper/123:15:281
3119621090,0sleep10-21swapper/123:15:281
2163421090,1sleep120-21swapper/1221:42:184
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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