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2025-11-18 - 23:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Tue Nov 18, 2025 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1802121710,8sleep02128999cyclictest23:05:550
2716821660,6sleep92130999cyclictest22:02:0915
1222721220,4sleep22129799cyclictest00:03:118
1619121210,1sleep30-21swapper/320:22:349
206202117103,10sleep140-21swapper/1419:11:386
17209211190,12sleep80-21swapper/819:07:3214
2979421090,1sleep150-21swapper/1522:31:087
20565210987,17sleep90-21swapper/919:11:3315
20568210789,13sleep120-21swapper/1219:11:364
1744221070,1sleep00-21swapper/022:58:420
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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