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2026-05-25 - 14:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Mon May 25, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
356521800,6sleep81111599cyclictest00:19:5014
10454211892,22sleep00-21swapper/019:10:180
10454211892,22sleep00-21swapper/019:10:180
1224621170,0sleep80-21swapper/823:34:5414
10538211283,24sleep80-21swapper/819:11:3014
10538211283,24sleep80-21swapper/819:11:3014
645721110,1sleep80-21swapper/821:32:5614
645721110,1sleep80-21swapper/821:32:5614
2871921090,7sleep101111799cyclictest00:28:252
724021060,7sleep91111699cyclictest23:40:4815
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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