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2026-05-21 - 11:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Thu May 21, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2025421720,1sleep120-21swapper/1200:03:314
113321610,0sleep20-21swapper/223:48:548
461721600,5sleep131033199cyclictest00:29:455
96622126109,12sleep90-21swapper/919:10:0715
96622126109,12sleep90-21swapper/919:10:0715
97462125103,17sleep20-21swapper/219:11:208
97462125103,17sleep20-21swapper/219:11:208
96812119103,11sleep100-21swapper/1019:10:242
96812119103,11sleep100-21swapper/1019:10:242
98582116102,9sleep80-21swapper/819:12:1514
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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