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2026-01-12 - 16:54
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Mon Jan 12, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1710121460,7sleep21841099cyclictest21:28:128
176812134111,18sleep110-21swapper/1119:06:553
177222126103,18sleep140-21swapper/1419:07:306
177092123103,15sleep50-21swapper/519:07:2111
177812118106,8sleep40-21swapper/419:08:2410
1338521160,0sleep40-21swapper/421:33:5110
176662112102,6sleep130-21swapper/1319:06:415
17605211190,16sleep30-21swapper/319:05:599
17711210593,7sleep70-21swapper/719:07:2313
17710210492,8sleep60-21swapper/619:07:2212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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