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2025-12-10 - 01:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Tue Dec 09, 2025 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1642421880,6sleep152018799cyclictest23:22:467
1642421880,6sleep152018799cyclictest23:22:467
667521490,8sleep22016999cyclictest22:47:318
2830921420,6sleep132018599cyclictest22:19:215
19582211993,21sleep80-21swapper/819:11:0114
194692119102,13sleep00-21swapper/019:09:330
3243321170,7sleep102017999cyclictest22:04:512
197042115103,8sleep50-21swapper/519:12:0211
19605211392,17sleep140-21swapper/1419:11:236
1367621080,0sleep60-21swapper/623:10:5112
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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