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2026-01-28 - 07:46
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Wed Jan 28, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2835021400,6sleep9312699cyclictest23:01:0615
2835021400,6sleep9312699cyclictest23:01:0615
3031421380,1sleep1430286-21sd-pam23:52:326
22562130103,22sleep140-21swapper/1419:06:246
1302521260,0sleep120-21swapper/1223:12:234
1302521260,0sleep120-21swapper/1223:12:234
2732721200,0sleep90-21swapper/900:36:3515
24612117103,10sleep10-21swapper/119:08:521
1916721130,1sleep110-21swapper/1122:53:383
519321120,1sleep85165-21sshd00:06:2014
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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