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2025-11-15 - 19:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Sat Nov 15, 2025 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2283521460,0sleep10-21swapper/121:53:241
2283521460,0sleep10-21swapper/121:53:241
1843021400,1sleep123016699cyclictest23:52:364
294972138104,29sleep90-21swapper/919:09:5415
294972138104,29sleep90-21swapper/919:09:5415
295732129102,22sleep120-21swapper/1219:11:014
295732129102,22sleep120-21swapper/1219:11:014
294322127103,19sleep10-21swapper/119:08:571
294322127103,19sleep10-21swapper/119:08:571
294792126101,20sleep80-21swapper/819:09:3614
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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