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2026-03-01 - 18:33
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Sat Feb 28, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1107721680,6sleep14844399cyclictest21:49:586
77102123100,18sleep30-21swapper/319:08:179
77302121105,12sleep60-21swapper/619:08:3612
463521170,7sleep4842799cyclictest00:17:5810
77582116104,7sleep130-21swapper/1319:08:595
2868221150,1sleep50-21swapper/521:58:2211
1828621120,6sleep7843299cyclictest21:22:0213
7901210992,13sleep120-21swapper/1219:10:194
7651210992,13sleep00-21swapper/019:07:260
1225921060,2sleep1312260-21sshd23:13:565
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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