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2026-02-07 - 10:23
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Sat Feb 07, 2026 00:43:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
413821760,6sleep51699699cyclictest21:56:4411
164092140112,23sleep30-21swapper/319:09:199
1380321390,6sleep91700199cyclictest22:40:2415
2850821370,5sleep71699899cyclictest00:20:0713
1628021330,0sleep10-21swapper/121:29:071
1628021330,0sleep10-21swapper/121:29:071
163082130103,23sleep130-21swapper/1319:07:535
163822126103,19sleep140-21swapper/1419:08:586
16249212595,25sleep90-21swapper/919:07:0115
164332121105,12sleep100-21swapper/1019:09:422
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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