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2026-05-31 - 14:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Sun May 31, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
206712127102,19sleep100-21swapper/1019:11:052
205702115101,9sleep90-21swapper/919:09:4415
20770211191,16sleep50-21swapper/519:11:4811
2496121090,0sleep120-21swapper/1200:02:524
2496121090,0sleep120-21swapper/1200:02:524
20695210991,14sleep00-21swapper/019:11:270
729421050,1sleep77295-21systemd-cgroups22:52:5813
2449221010,1sleep50-21swapper/523:49:5511
295421000,1sleep140-21swapper/1423:12:056
1803921000,1sleep60-21swapper/622:54:0212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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