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2026-07-25 - 16:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Sat Jul 25, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1817221890,5sleep131438399cyclictest22:24:265
1817221890,5sleep131438399cyclictest22:24:265
3172321380,0sleep100-21swapper/1022:05:242
104552127103,18sleep00-21swapper/019:05:330
1263821200,1sleep110-21swapper/1122:30:333
1263821200,1sleep110-21swapper/1122:30:333
174221170,5sleep81437699cyclictest23:49:5614
13599210892,12sleep130-21swapper/1319:06:505
1300221070,1sleep20-21swapper/222:06:368
1517821060,4sleep449-21ksoftirqd/421:26:3110
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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