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2026-06-15 - 21:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Mon Jun 15, 2026 00:43:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
959921750,6sleep41060299cyclictest23:08:3410
3147021680,5sleep111061299cyclictest21:29:593
98472145114,26sleep110-21swapper/1119:11:293
2423021320,0sleep150-21swapper/1522:30:467
231021170,2sleep02268-21sshd21:30:200
97202116103,9sleep140-21swapper/1419:09:406
1111921160,2sleep70-21swapper/722:19:2413
9733211190,14sleep100-21swapper/1019:09:522
9845211092,12sleep90-21swapper/919:11:2715
2083621090,0sleep120-21swapper/1200:33:454
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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