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2026-05-24 - 13:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Sun May 24, 2026 00:43:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
490421670,6sleep91729199cyclictest00:02:1115
2316121640,5sleep131729899cyclictest19:17:425
167072130103,22sleep80-21swapper/819:11:1314
2180721210,1sleep130-21swapper/1300:41:185
168212120104,12sleep140-21swapper/1419:12:076
16708212095,20sleep90-21swapper/919:11:1415
16521212091,24sleep20-21swapper/219:08:428
2694421180,1sleep110-21swapper/1100:19:203
166402117102,10sleep150-21swapper/1519:10:167
16523211694,17sleep40-21swapper/419:08:4410
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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