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2026-05-06 - 18:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Wed May 06, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1597721700,2sleep71399299cyclictest21:14:4813
2443321360,0sleep70-21swapper/723:56:2113
13563212695,26sleep40-21swapper/419:12:0310
2714621240,1sleep20-21swapper/222:19:598
132752124104,16sleep100-21swapper/1019:08:402
9441211389,16sleep150-21swapper/1519:07:097
132772113101,8sleep120-21swapper/1219:08:424
13528211292,15sleep90-21swapper/919:11:3515
133352112101,7sleep140-21swapper/1419:09:326
956421080,1sleep10-21swapper/121:22:441
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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