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2026-02-09 - 13:56
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot0.osadl.org (updated Mon Feb 09, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
586021850,5sleep51056999cyclictest21:21:5911
586021850,5sleep51056999cyclictest21:21:5911
3022921460,1sleep930230-21sshd22:51:5615
754821210,0sleep50-21swapper/500:16:0711
2524821170,0sleep80-21swapper/823:37:0714
613521130,2sleep130-21swapper/1323:51:545
613521130,2sleep130-21swapper/1323:51:545
989321110,2sleep20-21swapper/221:45:138
2190321100,1sleep30-21swapper/321:23:509
2190321100,1sleep30-21swapper/321:23:509
1993421070,1sleep00-21swapper/022:44:490
643021050,1sleep10-21swapper/100:16:031
2489521050,6sleep141058199cyclictest00:00:296
2489521050,6sleep141058199cyclictest00:00:296
2173421050,0sleep50-21swapper/522:15:4511
9814210491,9sleep120-21swapper/1219:07:064
933221020,1sleep90-21swapper/921:51:1315
2799121000,1sleep91-21systemd22:58:3715
203512990,0sleep100-21swapper/1021:39:442
9452980,1sleep150-21swapper/1523:31:377
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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