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2025-06-28 - 22:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot0.osadl.org (updated Sat Jun 28, 2025 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
80442135120,10sleep60-21swapper/619:09:4712
78172130104,21sleep140-21swapper/1419:07:156
11390991250,112rtkit-daemon0-21swapper/1319:08:115
80842120104,11sleep70-21swapper/719:10:2013
609821160,2sleep882-21ksoftirqd/819:05:4714
7850211588,23sleep110-21swapper/1119:07:443
2946021140,5sleep774-21ksoftirqd/721:44:2113
1435821100,6sleep3855699cyclictest22:26:169
2202321080,1sleep30-21swapper/319:25:469
7968210689,13sleep00-21swapper/019:09:250
567821040,1sleep100-21swapper/1021:59:382
124821040,1sleep150-21swapper/1522:28:377
2917921020,1sleep40-21swapper/421:36:4810
1985921010,0sleep130-21swapper/1300:25:275
2163521000,1sleep90-21swapper/922:19:5715
216612990,0sleep80-21swapper/822:15:5514
263152960,2sleep30-21swapper/323:59:379
43672950,1sleep20-21swapper/222:40:108
125282950,2sleep70-21swapper/723:09:5613
312592930,1sleep140-21swapper/1421:48:126
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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