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2026-08-08 - 22:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot0.osadl.org (updated Sat Aug 08, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
495421820,4sleep42877899cyclictest22:33:5710
1852521670,31sleep198650irq/39-eth0-TxR23:53:041
46821350,8sleep22877599cyclictest00:39:378
280932133102,26sleep40-21swapper/419:07:3110
28293212592,28sleep50-21swapper/519:09:4011
283402122107,10sleep120-21swapper/1219:10:204
533821190,2sleep00-21swapper/021:48:570
28196211394,15sleep150-21swapper/1519:09:027
1073221060,0sleep110-21swapper/1123:45:123
28208210591,9sleep80-21swapper/819:09:1114
3258221030,1sleep00-21swapper/022:30:080
28330210390,8sleep20-21swapper/219:10:098
2997021000,1sleep60-21swapper/623:19:1112
2997021000,1sleep60-21swapper/623:19:1112
196421000,1sleep130-21swapper/1321:37:565
201892990,1sleep60-21swapper/621:39:5712
133932990,1sleep10-21swapper/121:11:471
125922990,2sleep140-21swapper/1422:59:476
248762980,1sleep140-21swapper/1400:31:476
155982970,1sleep140-21swapper/1421:22:106
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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