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2025-10-26 - 07:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot0.osadl.org (updated Sun Oct 26, 2025 00:43:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2326021430,0sleep50-21swapper/500:25:5311
191642128103,20sleep140-21swapper/1419:08:366
1686821240,2sleep0111ktimersoftd/019:07:160
193102123104,14sleep80-21swapper/819:10:2214
19123212185,31sleep110-21swapper/1119:08:013
19376211994,20sleep150-21swapper/1519:11:177
3206721180,7sleep101995899cyclictest21:33:432
1365421180,1sleep40-21swapper/422:28:2610
985121150,0sleep140-21swapper/1422:38:466
19469211193,12sleep20-21swapper/219:11:528
19125211091,14sleep130-21swapper/1319:08:035
350821060,2sleep23510-21sshd22:34:188
1764921040,1sleep130-21swapper/1322:36:055
56921030,0sleep00-21swapper/021:37:170
19279210390,9sleep120-21swapper/1219:09:544
19312210283,14sleep100-21swapper/1019:10:242
1976221000,1sleep10-21swapper/122:57:491
4432980,2sleep71068-21dbus-daemon21:19:4513
209872980,1sleep90-21swapper/923:30:1915
298962960,1sleep131211ktimersoftd/1321:16:065
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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