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2025-12-26 - 02:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot0.osadl.org (updated Thu Dec 25, 2025 00:43:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1340621330,6sleep142157799cyclictest00:22:296
210962121104,13sleep120-21swapper/1219:10:084
20814211595,16sleep70-21swapper/719:06:5113
20948211092,14sleep100-21swapper/1019:08:462
21091210590,9sleep80-21swapper/819:10:0414
921221040,6sleep62156699cyclictest22:20:2412
134142950,1sleep50-21swapper/521:35:1211
89512890,1sleep40-21swapper/422:01:0710
2104528981,4sleep30-21swapper/319:09:279
2074928981,4sleep110-21swapper/1119:06:073
2108928874,7sleep60-21swapper/619:10:0212
2088728880,4sleep50-21swapper/519:07:5311
162372880,1sleep150-21swapper/1523:35:587
87872870,1sleep150-21swapper/1500:01:557
2095128775,7sleep130-21swapper/1319:08:495
78632860,1sleep00-21swapper/000:20:390
184182860,1sleep13122-21ksoftirqd/1300:14:595
59792840,1sleep70-21swapper/700:10:3613
2097528375,4sleep20-21swapper/219:09:108
2060628372,6sleep10-21swapper/119:05:411
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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