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2025-12-10 - 17:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot0.osadl.org (updated Wed Dec 10, 2025 00:43:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
693321220,0sleep20-21swapper/222:08:298
307732119103,10sleep20-21swapper/219:09:208
31053211798,15sleep60-21swapper/619:12:3712
2948721170,2sleep449-21ksoftirqd/419:08:0110
30937210792,10sleep140-21swapper/1419:11:416
708821040,1sleep143152199cyclictest00:02:066
1213121030,1sleep120-21swapper/1222:23:544
2054221010,1sleep90-21swapper/920:53:1115
647121000,1sleep60-21swapper/622:19:3112
161122970,2sleep90-21swapper/923:02:3815
148152970,6sleep33150599cyclictest22:20:339
312992960,1sleep231300-21systemd-cgroups23:12:098
18252950,2sleep990-21ksoftirqd/922:00:1915
167492940,0sleep50-21swapper/522:47:3511
62722930,2sleep86273-21sshd22:50:0314
235282930,5sleep83151299cyclictest22:10:4414
223562910,1sleep922318-21sshd23:37:2415
223562910,1sleep922318-21sshd23:37:2415
162472900,1sleep80-21swapper/822:13:2414
312302890,0sleep60-21swapper/600:39:0812
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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