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2026-03-26 - 06:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot0.osadl.org (updated Thu Mar 26, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
46721310,0sleep50-21swapper/522:06:4011
1711021270,1sleep417109-21sh21:34:3410
80522124102,17sleep30-21swapper/319:08:509
8173211194,13sleep100-21swapper/1019:10:332
8083210490,10sleep130-21swapper/1319:09:165
8165210392,7sleep40-21swapper/419:10:2710
1016621030,1sleep140-21swapper/1423:12:056
2321321020,2sleep723218-2110-uname23:06:5313
1413821020,1sleep882-21ksoftirqd/823:29:3814
7935210172,24sleep00-21swapper/019:07:110
484021010,7sleep15897399cyclictest23:52:137
484021010,7sleep15897399cyclictest23:52:137
914621000,2sleep11041-21dbus-daemon21:23:331
792829991,4sleep110-21swapper/1119:07:063
313342990,0sleep120-21swapper/1223:11:154
195602990,1sleep8811ktimersoftd/821:37:5014
16092970,1sleep100-21swapper/1021:52:512
166772960,0sleep100-21swapper/1022:38:512
38072950,1sleep40-21swapper/422:54:3210
291392950,0sleep50-21swapper/521:42:2011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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