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2025-08-21 - 22:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot0.osadl.org (updated Thu Aug 21, 2025 00:43:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3059321250,3sleep131509899cyclictest00:03:455
135622124104,13sleep120-21swapper/1219:06:374
14441212392,26sleep130-21swapper/1319:09:355
2040921120,1sleep150-21swapper/1521:44:267
14347211075,30sleep140-21swapper/1419:08:166
521121090,6sleep121509699cyclictest21:42:304
2769421080,1sleep90-21swapper/922:46:2315
2943921070,1sleep40-21swapper/423:29:0510
1148321070,8sleep11508099cyclictest21:28:411
1564621040,1sleep20-21swapper/221:25:138
1947721030,1sleep70-21swapper/721:44:1813
14248210392,7sleep60-21swapper/619:06:4712
82202990,5sleep151510199cyclictest00:05:077
197612980,0sleep30-21swapper/323:51:009
1424629877,16sleep50-21swapper/519:06:4611
130582980,17sleep90-21swapper/900:15:1115
301842970,1sleep40-21swapper/423:32:5010
301842970,1sleep40-21swapper/423:32:5010
189082970,1sleep30-21swapper/322:14:439
325172950,1sleep50-21swapper/522:42:5011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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