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2026-05-10 - 15:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot0.osadl.org (updated Sun May 10, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
86082121104,13sleep100-21swapper/1019:09:212
85092121102,15sleep80-21swapper/819:07:5914
86942119102,12sleep110-21swapper/1119:10:273
85062118105,9sleep60-21swapper/619:07:5712
3067421180,7sleep9930499cyclictest21:32:0715
84982116103,8sleep150-21swapper/1519:07:507
8739211594,16sleep10-21swapper/119:11:051
8684211192,14sleep20-21swapper/219:10:188
2766221110,1sleep30-21swapper/322:55:449
1390721110,0sleep100-21swapper/1023:59:462
2131921060,2sleep1021302-21sshd22:07:582
8743210592,9sleep50-21swapper/519:11:0911
459221040,1sleep8801rcuc/800:26:4514
2297121020,1sleep00-21swapper/022:36:410
2297121020,1sleep00-21swapper/022:36:410
2269521020,1sleep99287-21cyclictest00:34:3115
2830621000,2sleep0121rcuc/021:13:300
1699321000,6sleep990-21ksoftirqd/921:43:0515
48982990,1sleep7731ktimersoftd/723:49:3313
850329885,9sleep30-21swapper/319:07:549
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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