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2026-01-21 - 05:38
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot3.osadl.org (updated Wed Jan 21, 2026 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
81810rcu_preempt19979-21munin-run20:41:441
81780rcu_preempt0-21swapper/122:05:141
81780rcu_preempt0-21swapper/121:56:571
81770rcu_preempt19-21ksoftirqd/122:20:431
81760rcu_preempt0-21swapper/120:27:001
81750rcu_preempt0-21swapper/120:51:561
81730rcu_preempt28328-21sort19:06:441
81730rcu_preempt21109-21awk20:42:090
81730rcu_preempt0-21swapper/021:07:060
81720rcu_preempt0-21swapper/122:10:101
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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