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2026-03-03 - 00:25
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot3.osadl.org (updated Mon Mar 02, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
81810rcu_preempt19-21ksoftirqd/110:11:471
81790rcu_preempt28007-21ssh09:18:530
81790rcu_preempt19-21ksoftirqd/110:28:501
81790rcu_preempt0-21swapper/107:13:011
89850770irq/17-ehci_hcd0-21swapper/112:16:011
81760rcu_preempt6370-21ssh09:38:480
81750rcu_preempt0-21swapper/111:18:291
81740rcu_preempt24674-21diskmemload10:47:441
81740rcu_preempt0-21swapper/012:28:470
81730rcu_preempt5659-21ntp_states11:38:560
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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