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2026-01-26 - 08:00
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot3.osadl.org (updated Mon Jan 26, 2026 00:43:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
81940rcu_preempt22030-21ssh00:33:071
81820rcu_preempt10477-21awk19:07:151
81780rcu_preempt0-21swapper/022:45:460
81770rcu_preempt0-21swapper/122:21:521
81760rcu_preempt0-21swapper/121:27:121
81740rcu_preempt0-21swapper/123:27:281
81730rcu_preempt14913-21ssh00:21:411
81730rcu_preempt0-21swapper/123:32:141
81730rcu_preempt0-21swapper/122:02:541
81730rcu_preempt0-21swapper/100:23:341
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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