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2026-01-30 - 23:43
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot3.osadl.org (updated Fri Jan 30, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
81750rcu_preempt19725-21diskmemload11:40:181
89850740irq/17-ehci_hcd3-21ksoftirqd/010:39:220
81740rcu_preempt12843-21missed_timers09:57:300
81730rcu_preempt9409-21latency_hist09:52:101
81730rcu_preempt24917-21latency_hist12:22:101
81730rcu_preempt15816-21sh12:03:570
81730rcu_preempt0-21swapper/108:57:291
81720rcu_preempt8034-21sh10:48:271
81720rcu_preempt29895-21ssh09:29:091
81720rcu_preempt15212-21df_abs10:02:231
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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