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2026-02-03 - 01:21
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot3.osadl.org (updated Mon Feb 02, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
81760rcu_preempt0-21swapper/107:11:591
81740rcu_preempt5788-21needreboot08:27:391
81740rcu_preempt474-21uname08:07:371
81740rcu_preempt27571-21rm10:32:011
81730rcu_preempt15520-21sh11:11:281
81730rcu_preempt0-21swapper/109:27:401
81720rcu_preempt31881-21ssh12:42:180
81720rcu_preempt30416-21date10:37:181
81720rcu_preempt0-21swapper/012:09:220
81710rcu_preempt0-21swapper/111:27:461
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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