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2026-02-27 - 21:54
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot3.osadl.org (updated Fri Feb 27, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
81770rcu_preempt13183-21diskstats07:08:401
81750rcu_preempt31167-21timerwakeupswit11:48:511
147950750irq/31-eth0-tx-41ktimersoftd/011:11:260
81740rcu_preempt4180-21uname10:58:451
81740rcu_preempt1749-21mailstats08:28:501
81730rcu_preempt31033-21latency_hist09:48:261
81730rcu_preempt28122-21latency_hist08:08:250
81710rcu_preempt9035-21sh10:07:181
81710rcu_preempt8545-21ssh11:08:170
81710rcu_preempt0-21swapper/012:13:520
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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