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2026-02-27 - 07:58
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot3.osadl.org (updated Fri Feb 27, 2026 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
81820rcu_preempt10481-21mailstats00:13:500
81760rcu_preempt16845-21ntp_states23:23:460
81750rcu_preempt31693-1kworker/1:2H00:37:381
81750rcu_preempt21305-21sh23:33:280
81750rcu_preempt1271-21munin-run20:33:251
147850750irq/30-eth0-tx-0-21swapper/019:09:050
81730rcu_preempt0-21swapper/021:56:080
147650730irq/28-eth0-rx-0-21swapper/119:11:211
81720rcu_preempt0-21swapper/121:03:451
81710rcu_preempt3-21ksoftirqd/021:58:450
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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