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2026-01-27 - 20:43
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot3.osadl.org (updated Tue Jan 27, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
81800rcu_preempt14925-21diskmemload10:07:141
81780rcu_preempt0-21swapper/011:56:510
147950760irq/31-eth0-tx-0-21swapper/110:40:101
81700rcu_preempt0-21swapper/012:23:350
81700rcu_preempt0-21swapper/009:37:200
81650rcu_preempt15967-21fw_forwarded_lo07:07:170
81650rcu_preempt0-21swapper/111:22:171
81650rcu_preempt0-21swapper/111:07:271
81650rcu_preempt0-21swapper/110:51:581
81650rcu_preempt0-21swapper/109:16:361
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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