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2026-02-24 - 12:43
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot3.osadl.org (updated Tue Feb 24, 2026 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
81830rcu_preempt31233-21if_wlan023:13:351
81830rcu_preempt18449-21grep21:48:401
81810rcu_preempt0-21swapper/023:44:360
81790rcu_preempt0-21swapper/119:08:301
147950780irq/31-eth0-tx-41ktimersoftd/022:48:170
81770rcu_preempt19-21ksoftirqd/123:03:091
81750rcu_preempt19-21ksoftirqd/123:29:121
81740rcu_preempt19-21ksoftirqd/122:45:221
81740rcu_preempt19-21ksoftirqd/122:28:041
81740rcu_preempt19-21ksoftirqd/100:37:111
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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