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2026-01-26 - 20:16
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot3.osadl.org (updated Mon Jan 26, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
81830rcu_preempt19-21ksoftirqd/111:18:541
81820rcu_preempt19-21ksoftirqd/111:43:031
81780rcu_preempt0-21swapper/010:42:160
81730rcu_preempt20042-21ssh10:16:090
81730rcu_preempt0-21swapper/112:36:321
81730rcu_preempt0-21swapper/010:27:230
81720rcu_preempt30750-21ssh10:35:480
81720rcu_preempt0-21swapper/011:38:470
81710rcu_preempt24803-21sh10:23:450
81710rcu_preempt21472-21ssh12:17:550
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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