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2026-02-04 - 01:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot3.osadl.org (updated Tue Feb 03, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
811020rcu_preempt19-21ksoftirqd/111:11:121
81810rcu_preempt28308-21munin-run10:32:211
81810rcu_preempt2320-21k10sensors11:42:451
81810rcu_preempt11926-21munin-run12:02:211
81800rcu_preempt0-21swapper/110:52:561
81790rcu_preempt17465-21ssh10:12:121
147950780irq/31-eth0-tx-181ktimersoftd/111:52:241
81740rcu_preempt14924-21cat10:07:211
81740rcu_preempt0-21swapper/110:15:351
81740rcu_preempt0-21swapper/109:53:241
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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