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2026-01-29 - 23:16
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot3.osadl.org (updated Thu Jan 29, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
89850870irq/17-ehci_hcd4040-21ssh12:27:551
81870rcu_preempt23473-1kworker/0:1H11:06:110
81840rcu_preempt15743-21ssh11:50:250
81740rcu_preempt3107-21sh10:27:071
81740rcu_preempt21684-1kworker/1:0H12:14:441
81720rcu_preempt0-21swapper/111:52:331
81710rcu_preempt29961-21ssh11:17:190
81710rcu_preempt0-21swapper/112:33:351
81710rcu_preempt0-21swapper/111:57:331
81710rcu_preempt0-21swapper/110:32:201
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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