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2026-02-22 - 10:02
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot3.osadl.org (updated Sun Feb 22, 2026 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
81780rcu_preempt0-21swapper/121:53:111
81770rcu_preempt19-21ksoftirqd/100:41:181
81710rcu_preempt32642-21sh22:20:380
81710rcu_preempt29913-21/usr/sbin/munin19:08:350
81710rcu_preempt0-21swapper/123:49:241
81710rcu_preempt0-21swapper/023:43:560
81710rcu_preempt0-21swapper/019:43:100
81700rcu_preempt2137-21sh23:24:580
81700rcu_preempt0-21swapper/022:58:330
81700rcu_preempt0-21swapper/022:49:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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