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2026-03-04 - 01:06
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot3.osadl.org (updated Tue Mar 03, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
81710rcu_preempt0-21swapper/011:48:360
81710rcu_preempt0-21swapper/011:03:490
81710rcu_preempt0-21swapper/010:42:020
89850700irq/17-ehci_hcd945-21usb-storage10:21:110
81700rcu_preempt11858-21sh10:38:280
81700rcu_preempt0-21swapper/011:53:540
81690rcu_preempt753-21apt07:13:360
81690rcu_preempt0-21swapper/108:58:531
81680rcu_preempt0-21swapper/111:32:181
81680rcu_preempt0-21swapper/111:23:121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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