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2026-02-08 - 04:35
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot3.osadl.org (updated Sun Feb 08, 2026 00:43:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
147750930irq/29-eth0-rx-26743-21kworker/1:219:10:311
81750rcu_preempt32612-21irqstats00:22:520
81730rcu_preempt0-21swapper/021:35:130
81710rcu_preempt29671-21munin-run19:12:320
81710rcu_preempt0-21swapper/023:56:220
81710rcu_preempt0-21swapper/019:32:490
81700rcu_preempt1743-21fw_forwarded_lo22:22:500
81700rcu_preempt0-21swapper/023:27:330
81700rcu_preempt0-21swapper/022:33:030
81700rcu_preempt0-21swapper/022:19:500
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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