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2026-02-25 - 06:36
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot3.osadl.org (updated Wed Feb 25, 2026 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
147850840irq/30-eth0-tx-0-21swapper/019:13:150
81800rcu_preempt0-21swapper/022:30:500
81790rcu_preempt6160-21diskmemload00:10:461
81790rcu_preempt0-21swapper/120:13:441
81740rcu_preempt8522-21missed_timers23:13:400
81730rcu_preempt3699-21memory22:03:400
81720rcu_preempt0-21swapper/000:27:290
81710rcu_preempt0-21swapper/023:53:190
81710rcu_preempt0-21swapper/022:50:520
81710rcu_preempt0-21swapper/022:23:430
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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