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2026-03-01 - 11:46
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot3.osadl.org (updated Sun Mar 01, 2026 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
81790rcu_preempt0-21swapper/119:09:041
81780rcu_preempt19-21ksoftirqd/122:41:291
81760rcu_preempt19-21ksoftirqd/123:56:431
81760rcu_preempt19-21ksoftirqd/121:49:371
81760rcu_preempt19-21ksoftirqd/121:49:371
81750rcu_preempt19-21ksoftirqd/123:36:201
81750rcu_preempt19-21ksoftirqd/122:46:061
81750rcu_preempt0-21swapper/121:22:511
81730rcu_preempt0-21swapper/022:28:030
81720rcu_preempt0-21swapper/021:13:450
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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