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2026-02-22 - 22:28
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot3.osadl.org (updated Sun Feb 22, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
81850rcu_preempt0-21swapper/007:08:270
81760rcu_preempt3335-21memory07:08:311
81730rcu_preempt9051-21ssh12:28:251
81730rcu_preempt19-21ksoftirqd/110:13:031
81730rcu_preempt16669-21ssh09:38:350
81720rcu_preempt22511-21ssh09:48:440
81700rcu_preempt6160-21sh11:21:090
81690rcu_preempt15607-21df07:58:270
81690rcu_preempt0-21swapper/007:43:250
81680rcu_preempt2138-21snmpd11:31:490
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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