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2026-08-26 - 13:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackcslot3.osadl.org (updated Wed Aug 26, 2026 00:43:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
81770rcu_preempt17567-21/usr/sbin/munin20:35:311
81770rcu_preempt0-21swapper/021:50:080
81760rcu_preempt762-21if_err_eth019:30:131
81750rcu_preempt6654-21munin-run19:54:561
81740rcu_preempt26262-21latency21:10:160
81740rcu_preempt12699-21cpuspeed_turbos22:55:091
81740rcu_preempt0-21swapper/022:05:590
81730rcu_preempt10895-21/usr/sbin/munin22:50:200
81730rcu_preempt10895-21/usr/sbin/munin22:50:200
81730rcu_preempt0-21swapper/019:25:200
81720rcu_preempt4739-21ssh22:39:481
81710rcu_preempt9572-21ssh23:51:331
81710rcu_preempt0-21swapper/122:45:201
81710rcu_preempt0-21swapper/119:25:181
81710rcu_preempt0-21swapper/023:55:190
81710rcu_preempt0-21swapper/022:18:590
81710rcu_preempt0-21swapper/020:34:570
81710rcu_preempt0-21swapper/000:00:130
81700rcu_preempt6617-21ssh22:42:270
81700rcu_preempt28108-21diskmemload00:06:251
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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