You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-13 - 19:25
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Default latency plot of shadow in rack #c, slot #3

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
Special  All - All RT - Optimization - Ethernet - Thumbnails - Next
  
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot3s.osadl.org (updated Fri Feb 13, 2026 12:43:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
96252341319,5sleep20-21swapper/207:05:062
114642319305,11sleep00-21swapper/007:07:040
11962993180,315cyclictest19481-21kworker/u16:3+efi_rts_wq08:55:143
115992317311,4sleep30-21swapper/307:08:473
96312314307,5sleep10-21swapper/107:05:091
11959993120,311cyclictest15468-21kworker/u16:2+efi_rts_wq08:32:450
11962993100,309cyclictest16161-21kworker/u16:2+efi_rts_wq11:50:133
11962993100,307cyclictest19481-21kworker/u16:3+efi_rts_wq07:30:103
11961993100,309cyclictest15468-21kworker/u16:2+efi_rts_wq10:23:082
11960993100,309cyclictest15468-21kworker/u16:2+efi_rts_wq09:27:551
11959993090,308cyclictest15468-21kworker/u16:2+efi_rts_wq08:25:120
11962993080,307cyclictest3612-21kworker/u16:1+efi_rts_wq11:00:133
11962993080,307cyclictest19481-21kworker/u16:3+efi_rts_wq07:57:383
11960993080,307cyclictest3612-21kworker/u16:1+efi_rts_wq11:28:221
11960993080,307cyclictest3612-21kworker/u16:1+efi_rts_wq11:00:121
11962993070,306cyclictest15468-21kworker/u16:2+efi_rts_wq09:05:133
11960993070,306cyclictest15468-21kworker/u16:2+efi_rts_wq09:30:121
11960993060,305cyclictest15468-21kworker/u16:2+efi_rts_wq08:10:131
11962993050,304cyclictest15468-21kworker/u16:2+efi_rts_wq09:58:023
11962993050,304cyclictest15468-21kworker/u16:2+efi_rts_wq08:30:113
11962993050,304cyclictest15468-21kworker/u16:2+efi_rts_wq07:25:133
11962993040,303cyclictest19481-21kworker/u16:3+efi_rts_wq08:15:143
11960993040,303cyclictest3612-21kworker/u16:1+efi_rts_wq12:28:341
11960993040,303cyclictest3612-21kworker/u16:1+efi_rts_wq10:55:121
11959993040,303cyclictest15468-21kworker/u16:2+efi_rts_wq10:05:110
11960993030,302cyclictest19481-21kworker/u16:3+efi_rts_wq07:30:111
11960993020,301cyclictest19481-21kworker/u16:3+efi_rts_wq09:20:131
11962993010,300cyclictest3612-21kworker/u16:1+efi_rts_wq11:30:123
11960993010,300cyclictest15468-21kworker/u16:2+efi_rts_wq08:05:121
11959993010,298cyclictest15468-21kworker/u16:2+efi_rts_wq08:45:110
11962992960,295cyclictest15468-21kworker/u16:2+efi_rts_wq07:15:143
11961992960,295cyclictest15296-21kworker/u16:0+efi_rts_wq10:35:132
11959992960,295cyclictest19481-21kworker/u16:3+efi_rts_wq07:52:380
11959992950,293cyclictest16161-21kworker/u16:2+efi_rts_wq11:50:120
11962992940,293cyclictest24833-21kworker/u16:2+efi_rts_wq11:05:113
11962992930,292cyclictest15468-21kworker/u16:2+efi_rts_wq10:05:123
11961992920,291cyclictest19481-21kworker/u16:3+efi_rts_wq07:45:132
11960992920,291cyclictest15468-21kworker/u16:2+efi_rts_wq08:00:131
11960992920,291cyclictest15296-21kworker/u16:0+efi_rts_wq09:50:121
11959992920,291cyclictest15296-21kworker/u16:0+efi_rts_wq09:50:110
11959992910,290cyclictest16161-21kworker/u16:2+efi_rts_wq12:30:140
11961992900,289cyclictest15468-21kworker/u16:2+efi_rts_wq08:12:412
11959992900,289cyclictest19481-21kworker/u16:3+efi_rts_wq08:40:140
11960992890,288cyclictest15296-21kworker/u16:0+efi_rts_wq10:00:121
11960992890,288cyclictest15296-21kworker/u16:0+efi_rts_wq10:00:121
11961992870,286cyclictest3612-21kworker/u16:1+efi_rts_wq12:15:102
11959992870,286cyclictest15468-21kworker/u16:2+efi_rts_wq08:02:390
11961992850,284cyclictest16161-21kworker/u16:2+efi_rts_wq12:35:132
11960992850,284cyclictest3612-21kworker/u16:1+efi_rts_wq11:10:121
11960992850,284cyclictest19481-21kworker/u16:3+efi_rts_wq07:50:121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional