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2026-02-06 - 18:36
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #c, slot #3

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot3s.osadl.org (updated Fri Feb 06, 2026 12:43:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
168602334311,5sleep10-21swapper/107:07:111
169072320313,4sleep30-21swapper/307:07:503
170052317309,5sleep20-21swapper/207:09:052
169682316308,5sleep00-21swapper/007:08:340
17341993150,314cyclictest27599-21kworker/u16:2+efi_rts_wq07:20:111
17341993140,311cyclictest10451-21kworker/u16:1+efi_rts_wq08:25:121
17342993110,310cyclictest1661-21kworker/u16:2+efi_rts_wq11:05:142
17341993110,310cyclictest25977-21kworker/u16:0+efi_rts_wq07:40:121
17343993090,308cyclictest4026-21kworker/u16:0+efi_rts_wq08:12:103
17341993090,308cyclictest11086-21kworker/u16:3+efi_rts_wq11:55:131
17341993081,306cyclictest17457-21kworker/u16:4+efi_rts_wq12:20:141
17342993070,306cyclictest1661-21kworker/u16:2+efi_rts_wq09:55:132
17342993020,301cyclictest17457-21kworker/u16:4+efi_rts_wq12:30:122
17340993020,301cyclictest27362-21kworker/u16:0+efi_rts_wq09:12:200
17340993020,301cyclictest17381-21kworker/u16:0+efi_rts_wq11:00:130
17341993010,300cyclictest31916-21kworker/u16:0+efi_rts_wq11:30:131
17340993010,300cyclictest17457-21kworker/u16:4+efi_rts_wq12:05:140
17340993000,299cyclictest27362-21kworker/u16:0+efi_rts_wq08:50:120
17341992980,297cyclictest32121-21kworker/u16:2+efi_rts_wq08:05:121
17342992970,296cyclictest4034-21kworker/u16:4+efi_rts_wq09:22:212
17341992960,295cyclictest11073-21kworker/u16:3+efi_rts_wq07:27:021
17340992960,295cyclictest1661-21kworker/u16:2+efi_rts_wq10:55:120
17343992950,294cyclictest32121-21kworker/u16:2+efi_rts_wq08:15:103
17343992950,294cyclictest11086-21kworker/u16:3+efi_rts_wq12:00:133
17341992950,294cyclictest1661-21kworker/u16:2+efi_rts_wq09:35:131
17343992940,293cyclictest17457-21kworker/u16:4+efi_rts_wq12:25:123
17342992940,293cyclictest1661-21kworker/u16:2+efi_rts_wq10:27:332
17341992940,293cyclictest1048-21kworker/u16:3+efi_rts_wq10:45:121
17343992930,292cyclictest4034-21kworker/u16:4+efi_rts_wq09:30:133
17343992930,292cyclictest20819-21kworker/u16:0+efi_rts_wq10:07:293
17341992930,292cyclictest1811-21kworker/u16:1+efi_rts_wq07:47:071
17342992920,291cyclictest4034-21kworker/u16:4+efi_rts_wq09:15:132
17343992900,289cyclictest32121-21kworker/u16:2+efi_rts_wq08:30:133
17343992890,288cyclictest11073-21kworker/u16:3+efi_rts_wq07:15:123
17341992890,288cyclictest4034-21kworker/u16:4+efi_rts_wq09:40:121
17342992880,287cyclictest17457-21kworker/u16:4+efi_rts_wq11:20:122
17341992880,287cyclictest27362-21kworker/u16:0+efi_rts_wq08:50:121
17341992880,287cyclictest17457-21kworker/u16:4+efi_rts_wq12:12:541
17341992860,285cyclictest1661-21kworker/u16:2+efi_rts_wq11:15:091
17343992850,284cyclictest11073-21kworker/u16:3+efi_rts_wq08:00:113
17340992840,283cyclictest31833-21kworker/u16:1+efi_rts_wq12:35:120
17341992830,280cyclictest11073-21kworker/u16:3+efi_rts_wq08:00:121
17340992820,281cyclictest1811-21kworker/u16:1+efi_rts_wq07:50:130
17340992820,281cyclictest10451-21kworker/u16:1+efi_rts_wq08:45:120
17342992810,280cyclictest27362-21kworker/u16:0+efi_rts_wq09:02:182
17342992800,279cyclictest10451-21kworker/u16:1+efi_rts_wq08:35:132
17343992790,278cyclictest4034-21kworker/u16:4+efi_rts_wq09:40:123
17343992790,278cyclictest1661-21kworker/u16:2+efi_rts_wq11:05:133
17341992790,277cyclictest1661-21kworker/u16:2+efi_rts_wq11:10:121
17342992780,277cyclictest32121-21kworker/u16:2+efi_rts_wq08:30:122
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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