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2025-08-30 - 00:44

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #c, slot #3

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot3s.osadl.org (updated Fri Aug 29, 2025 12:43:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
319782324317,5sleep30-21swapper/307:08:393
318302319304,5sleep00-21swapper/007:06:420
319362315307,5sleep10-21swapper/107:08:041
317382313305,5sleep20-21swapper/207:05:322
32355992960,295cyclictest5111-21kworker/u16:0+efi_rts_wq07:27:143
32354992960,295cyclictest5111-21kworker/u16:0+efi_rts_wq10:10:112
32354992960,295cyclictest24081-21kworker/u16:1+efi_rts_wq11:40:132
32355992950,294cyclictest24081-21kworker/u16:1+efi_rts_wq12:03:023
32353992930,292cyclictest21028-21kworker/u16:2+efi_rts_wq08:40:191
32355992920,291cyclictest21028-21kworker/u16:2+efi_rts_wq08:00:143
32355992910,290cyclictest5111-21kworker/u16:0+efi_rts_wq10:40:123
32353992910,290cyclictest21028-21kworker/u16:2+efi_rts_wq09:05:131
32355992870,286cyclictest5111-21kworker/u16:0+efi_rts_wq09:00:143
32353992870,286cyclictest5111-21kworker/u16:0+efi_rts_wq10:02:411
32353992850,284cyclictest21028-21kworker/u16:2+efi_rts_wq07:57:191
32352992840,283cyclictest24081-21kworker/u16:1+efi_rts_wq11:00:140
32355992830,282cyclictest5111-21kworker/u16:0+efi_rts_wq09:10:123
32353992830,282cyclictest21028-21kworker/u16:2+efi_rts_wq07:52:191
32353992820,281cyclictest5111-21kworker/u16:0+efi_rts_wq07:10:141
32354992800,279cyclictest21028-21kworker/u16:2+efi_rts_wq10:25:182
32353992800,279cyclictest5111-21kworker/u16:0+efi_rts_wq09:45:131
32352992800,279cyclictest5111-21kworker/u16:0+efi_rts_wq07:20:130
32353992790,278cyclictest21028-21kworker/u16:2+efi_rts_wq08:25:131
32354992780,277cyclictest24081-21kworker/u16:1+efi_rts_wq11:05:172
32354992770,276cyclictest5111-21kworker/u16:0+efi_rts_wq08:10:132
32354992770,276cyclictest24081-21kworker/u16:1+efi_rts_wq10:45:142
32352992770,276cyclictest5111-21kworker/u16:0+efi_rts_wq09:40:160
32352992770,276cyclictest21028-21kworker/u16:2+efi_rts_wq09:07:300
32355992760,275cyclictest21028-21kworker/u16:2+efi_rts_wq08:25:143
32354992760,275cyclictest21028-21kworker/u16:2+efi_rts_wq08:55:122
32352992760,275cyclictest21028-21kworker/u16:2+efi_rts_wq09:35:130
32354992750,274cyclictest21028-21kworker/u16:2+efi_rts_wq08:47:272
32355992740,273cyclictest21028-21kworker/u16:2+efi_rts_wq09:15:153
32354992740,271cyclictest21028-21kworker/u16:2+efi_rts_wq08:15:142
32353992740,273cyclictest1663-21kworker/u16:2+efi_rts_wq11:15:141
32355992730,272cyclictest5111-21kworker/u16:0+efi_rts_wq08:10:133
32355992730,272cyclictest21028-21kworker/u16:2+efi_rts_wq10:30:133
32352992730,272cyclictest21028-21kworker/u16:2+efi_rts_wq08:20:140
32353992710,270cyclictest5111-21kworker/u16:0+efi_rts_wq09:25:131
32352992710,270cyclictest21028-21kworker/u16:2+efi_rts_wq08:00:140
32354992700,269cyclictest5111-21kworker/u16:0+efi_rts_wq07:35:152
32354992690,268cyclictest21028-21kworker/u16:2+efi_rts_wq08:52:292
32352992680,267cyclictest30134-21kworker/u16:0+efi_rts_wq12:25:140
32352992680,267cyclictest1663-21kworker/u16:2+efi_rts_wq11:35:130
32353992670,266cyclictest5111-21kworker/u16:0+efi_rts_wq08:05:131
32353992660,265cyclictest30134-21kworker/u16:0+efi_rts_wq12:08:031
32355992630,261cyclictest24081-21kworker/u16:1+efi_rts_wq11:20:133
32355992620,261cyclictest21028-21kworker/u16:2+efi_rts_wq10:00:143
32353992620,261cyclictest21028-21kworker/u16:2+efi_rts_wq10:15:161
32354992610,260cyclictest24081-21kworker/u16:1+efi_rts_wq11:25:142
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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