You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-14 - 13:10
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Default latency plot of shadow in rack #c, slot #3

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
Special  All - All RT - Optimization - Ethernet - Thumbnails - Next
  
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot3s.osadl.org (updated Sat Feb 14, 2026 00:43:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31092329303,24sleep10-21swapper/119:07:441
32292324317,5sleep20-21swapper/219:09:172
3554993210,318cyclictest25472-21kworker/u16:0+efi_rts_wq23:55:152
31702318310,5sleep00-21swapper/019:08:300
32702317309,5sleep30-21swapper/319:09:503
3553993150,314cyclictest3758-21kworker/u16:3+efi_rts_wq22:35:291
3552993150,314cyclictest8882-21kworker/u16:4+efi_rts_wq20:20:140
3554993130,312cyclictest1749-21kworker/u16:0+efi_rts_wq20:15:132
3554993120,311cyclictest4718-21kworker/u16:1+efi_rts_wq21:00:142
3554993120,311cyclictest25472-21kworker/u16:0+efi_rts_wq21:20:142
3555993090,308cyclictest3758-21kworker/u16:3+efi_rts_wq22:20:273
3555993090,308cyclictest3758-21kworker/u16:3+efi_rts_wq22:20:263
3555993090,308cyclictest3758-21kworker/u16:3+efi_rts_wq00:25:133
3552993090,308cyclictest4718-21kworker/u16:1+efi_rts_wq21:05:140
3554993070,306cyclictest8882-21kworker/u16:4+efi_rts_wq19:40:112
3555993060,305cyclictest8882-21kworker/u16:4+efi_rts_wq20:05:143
3555993060,305cyclictest4529-21kworker/u16:2+efi_rts_wq19:25:133
3555993050,304cyclictest4529-21kworker/u16:2+efi_rts_wq19:20:133
3554993050,304cyclictest4183-21kworker/u16:2+efi_rts_wq23:40:112
3553993050,304cyclictest25472-21kworker/u16:0+efi_rts_wq21:50:111
3553993040,302cyclictest29642-21kworker/u16:1+efi_rts_wq22:50:331
3553993030,302cyclictest4529-21kworker/u16:2+efi_rts_wq19:15:141
3555993020,301cyclictest3758-21kworker/u16:3+efi_rts_wq22:35:113
3554993020,300cyclictest25472-21kworker/u16:0+efi_rts_wq22:40:312
3552993020,301cyclictest25472-21kworker/u16:0+efi_rts_wq23:45:130
3555993000,297cyclictest3758-21kworker/u16:3+efi_rts_wq22:25:123
3554992990,298cyclictest8882-21kworker/u16:4+efi_rts_wq19:45:122
3552992990,298cyclictest3758-21kworker/u16:3+efi_rts_wq23:20:110
3552992990,298cyclictest25472-21kworker/u16:0+efi_rts_wq22:00:220
3555992980,297cyclictest8882-21kworker/u16:4+efi_rts_wq19:45:133
3552992980,297cyclictest4529-21kworker/u16:2+efi_rts_wq19:44:560
3552992980,297cyclictest25472-21kworker/u16:0+efi_rts_wq23:55:160
3554992960,295cyclictest8882-21kworker/u16:4+efi_rts_wq19:50:132
3554992960,295cyclictest3758-21kworker/u16:3+efi_rts_wq23:05:132
3552992960,295cyclictest8882-21kworker/u16:4+efi_rts_wq21:00:110
3552992960,295cyclictest4183-21kworker/u16:2+efi_rts_wq00:30:120
3553992950,294cyclictest4529-21kworker/u16:2+efi_rts_wq20:10:121
3552992950,294cyclictest3758-21kworker/u16:3+efi_rts_wq21:35:180
3555992940,293cyclictest4529-21kworker/u16:2+efi_rts_wq19:15:143
3555992940,293cyclictest25472-21kworker/u16:0+efi_rts_wq21:15:123
3555992930,292cyclictest4529-21kworker/u16:2+efi_rts_wq20:10:123
3555992930,292cyclictest4183-21kworker/u16:2+efi_rts_wq00:00:133
3552992930,292cyclictest3758-21kworker/u16:3+efi_rts_wq23:10:120
3555992920,291cyclictest4183-21kworker/u16:2+efi_rts_wq00:10:123
3555992920,291cyclictest25472-21kworker/u16:0+efi_rts_wq23:40:433
3553992920,290cyclictest4183-21kworker/u16:2+efi_rts_wq23:50:121
3552992920,291cyclictest4718-21kworker/u16:1+efi_rts_wq20:40:110
3552992910,290cyclictest8882-21kworker/u16:4+efi_rts_wq19:55:120
3555992900,288cyclictest4718-21kworker/u16:1+efi_rts_wq20:55:093
3553992900,289cyclictest8882-21kworker/u16:4+efi_rts_wq20:10:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional