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2026-02-14 - 20:49
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #c, slot #3

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot3s.osadl.org (updated Sat Feb 14, 2026 12:43:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
304252325318,5sleep00-21swapper/007:09:070
304182319313,4sleep30-21swapper/307:09:033
301502318311,5sleep10-21swapper/107:05:351
302282317303,5sleep20-21swapper/207:06:372
30839993130,312cyclictest2585-21kworker/u16:1+efi_rts_wq07:17:333
30832993130,312cyclictest30334-21kworker/u16:3+efi_rts_wq08:45:122
30820993130,312cyclictest2585-21kworker/u16:1+efi_rts_wq10:00:120
30832993120,311cyclictest2585-21kworker/u16:1+efi_rts_wq10:50:132
30832993120,311cyclictest2585-21kworker/u16:1+efi_rts_wq10:50:132
30832993110,310cyclictest2585-21kworker/u16:1+efi_rts_wq08:35:132
30820993110,310cyclictest2585-21kworker/u16:1+efi_rts_wq07:10:130
30832993100,309cyclictest30334-21kworker/u16:3+efi_rts_wq10:05:112
30825993100,309cyclictest4124-21kworker/u16:3+efi_rts_wq11:50:111
30825993100,309cyclictest12292-21kworker/u16:3+efi_rts_wq11:10:131
30832993090,308cyclictest30334-21kworker/u16:3+efi_rts_wq07:30:102
30825993090,308cyclictest21193-21kworker/u16:1+efi_rts_wq11:55:111
30839993080,307cyclictest21193-21kworker/u16:1+efi_rts_wq12:20:113
30832993070,306cyclictest21193-21kworker/u16:1+efi_rts_wq11:40:132
30825993070,306cyclictest21193-21kworker/u16:1+efi_rts_wq12:05:121
30832993060,305cyclictest2585-21kworker/u16:1+efi_rts_wq11:00:122
30825993060,305cyclictest2585-21kworker/u16:1+efi_rts_wq10:03:021
30839993050,304cyclictest2585-21kworker/u16:1+efi_rts_wq10:10:143
30825993050,304cyclictest30334-21kworker/u16:3+efi_rts_wq10:30:121
30832993030,302cyclictest2585-21kworker/u16:1+efi_rts_wq07:55:132
30839993020,301cyclictest2585-21kworker/u16:1+efi_rts_wq08:10:123
30825993020,301cyclictest11225-21kworker/u16:2+efi_rts_wq12:03:261
30825993010,300cyclictest11225-21kworker/u16:2+efi_rts_wq12:25:131
30820993010,300cyclictest2585-21kworker/u16:1+efi_rts_wq07:40:120
30839993000,299cyclictest30334-21kworker/u16:3+efi_rts_wq09:25:123
30839993000,299cyclictest30334-21kworker/u16:3+efi_rts_wq07:50:123
30832993000,299cyclictest2585-21kworker/u16:1+efi_rts_wq07:27:352
30832993000,299cyclictest25623-21kworker/u16:2+efi_rts_wq11:30:142
30820993000,299cyclictest30334-21kworker/u16:3+efi_rts_wq09:25:130
30820993000,297cyclictest2585-21kworker/u16:1+efi_rts_wq10:35:140
30839992990,298cyclictest30334-21kworker/u16:3+efi_rts_wq08:02:393
30839992990,298cyclictest25623-21kworker/u16:2+efi_rts_wq11:45:143
30832992990,298cyclictest30334-21kworker/u16:3+efi_rts_wq10:38:102
30820992990,298cyclictest2585-21kworker/u16:1+efi_rts_wq10:40:130
30820992990,298cyclictest2585-21kworker/u16:1+efi_rts_wq10:40:120
30832992980,297cyclictest30334-21kworker/u16:3+efi_rts_wq09:00:122
30832992980,297cyclictest30334-21kworker/u16:3+efi_rts_wq08:00:142
30825992980,297cyclictest2585-21kworker/u16:1+efi_rts_wq07:25:131
30839992970,296cyclictest30334-21kworker/u16:3+efi_rts_wq08:42:473
30839992970,296cyclictest30334-21kworker/u16:3+efi_rts_wq08:25:133
30839992970,294cyclictest2585-21kworker/u16:1+efi_rts_wq08:37:453
30825992970,296cyclictest30334-21kworker/u16:3+efi_rts_wq10:23:061
30820992970,296cyclictest21193-21kworker/u16:1+efi_rts_wq12:30:130
30832992960,295cyclictest30334-21kworker/u16:3+efi_rts_wq08:07:402
30820992960,295cyclictest30334-21kworker/u16:3+efi_rts_wq09:12:520
30839992950,293cyclictest12292-21kworker/u16:3+efi_rts_wq11:15:143
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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