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2026-01-13 - 06:03
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #c, slot #3

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot3s.osadl.org (updated Tue Jan 13, 2026 00:43:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
285452332325,4sleep30-21swapper/319:05:373
287672319308,9sleep20-21swapper/219:08:282
285372317303,5sleep00-21swapper/019:05:300
29152993140,313cyclictest26676-21kworker/u16:2+efi_rts_wq23:20:132
286842314306,5sleep10-21swapper/119:07:231
29152993130,312cyclictest2368-21kworker/u16:3+efi_rts_wq21:35:122
29153993110,310cyclictest26676-21kworker/u16:2+efi_rts_wq23:45:123
29151993110,310cyclictest2368-21kworker/u16:3+efi_rts_wq21:10:121
29150993110,310cyclictest8614-21kworker/u16:2+efi_rts_wq19:29:480
29152993080,307cyclictest8614-21kworker/u16:2+efi_rts_wq20:00:132
29152993080,307cyclictest8614-21kworker/u16:2+efi_rts_wq20:00:132
29152993080,307cyclictest8614-21kworker/u16:2+efi_rts_wq19:40:132
29150993080,306cyclictest25307-21kworker/u16:4+efi_rts_wq00:35:130
29151993070,306cyclictest8614-21kworker/u16:2+efi_rts_wq21:00:111
29151993070,306cyclictest12688-21kworker/u16:0+efi_rts_wq20:30:131
29151993070,306cyclictest12688-21kworker/u16:0+efi_rts_wq20:20:121
29153993060,305cyclictest8614-21kworker/u16:2+efi_rts_wq20:14:563
29152993060,305cyclictest8614-21kworker/u16:2+efi_rts_wq21:00:112
29151993050,304cyclictest25307-21kworker/u16:4+efi_rts_wq00:25:411
29153993040,303cyclictest8614-21kworker/u16:2+efi_rts_wq21:50:123
29150993040,303cyclictest25307-21kworker/u16:4+efi_rts_wq00:30:130
29153993030,302cyclictest8614-21kworker/u16:2+efi_rts_wq22:00:133
29152993030,302cyclictest8614-21kworker/u16:2+efi_rts_wq20:25:122
29150993030,302cyclictest8614-21kworker/u16:2+efi_rts_wq19:44:510
29150993020,301cyclictest2368-21kworker/u16:3+efi_rts_wq21:05:120
29153993010,300cyclictest2368-21kworker/u16:3+efi_rts_wq21:35:123
29153993000,299cyclictest12688-21kworker/u16:0+efi_rts_wq19:20:113
29151993000,299cyclictest12688-21kworker/u16:0+efi_rts_wq19:50:131
29150993000,299cyclictest8614-21kworker/u16:2+efi_rts_wq20:05:130
29150993000,299cyclictest12688-21kworker/u16:0+efi_rts_wq20:50:130
29152992980,297cyclictest12688-21kworker/u16:0+efi_rts_wq19:10:162
29152992970,296cyclictest8614-21kworker/u16:2+efi_rts_wq20:35:132
29152992970,296cyclictest8614-21kworker/u16:2+efi_rts_wq19:35:112
29152992970,296cyclictest21670-21kworker/u16:0+efi_rts_wq23:40:132
29151992970,296cyclictest12688-21kworker/u16:0+efi_rts_wq19:10:161
29152992960,295cyclictest26676-21kworker/u16:2+efi_rts_wq23:45:342
29152992960,295cyclictest2368-21kworker/u16:3+efi_rts_wq22:45:112
29151992960,295cyclictest26676-21kworker/u16:2+efi_rts_wq23:10:261
29151992960,295cyclictest12688-21kworker/u16:0+efi_rts_wq19:55:141
29153992950,294cyclictest2368-21kworker/u16:3+efi_rts_wq22:30:133
29151992940,293cyclictest25200-21kworker/u16:1+efi_rts_wq00:20:131
29152992930,292cyclictest2368-21kworker/u16:3+efi_rts_wq22:30:132
29150992930,292cyclictest8614-21kworker/u16:2+efi_rts_wq20:00:130
29150992930,292cyclictest8614-21kworker/u16:2+efi_rts_wq20:00:130
29152992890,288cyclictest8614-21kworker/u16:2+efi_rts_wq21:20:122
29151992890,288cyclictest8614-21kworker/u16:2+efi_rts_wq19:40:131
29151992870,286cyclictest21670-21kworker/u16:0+efi_rts_wq22:55:141
29150992870,286cyclictest25200-21kworker/u16:1+efi_rts_wq00:05:140
29152992850,284cyclictest2368-21kworker/u16:3+efi_rts_wq21:30:122
29151992850,284cyclictest8614-21kworker/u16:2+efi_rts_wq22:25:191
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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