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2026-01-29 - 14:58
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #c, slot #3

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot3s.osadl.org (updated Thu Jan 29, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
313182318312,4sleep10-21swapper/107:07:291
315042316308,5sleep00-21swapper/007:09:530
313032316309,5sleep30-21swapper/307:07:193
312972316308,5sleep20-21swapper/207:07:142
31781993150,314cyclictest7176-21kworker/u16:3+efi_rts_wq07:10:121
31783993130,312cyclictest6138-21kworker/u16:0+efi_rts_wq10:05:133
31781993130,312cyclictest7176-21kworker/u16:3+efi_rts_wq08:22:531
31781993130,312cyclictest2827-21kworker/u16:0+efi_rts_wq08:35:141
31783993120,311cyclictest11554-21kworker/u16:1+efi_rts_wq10:30:123
31781993120,309cyclictest7176-21kworker/u16:3+efi_rts_wq08:00:121
31783993090,308cyclictest7176-21kworker/u16:3+efi_rts_wq08:45:133
31783993090,308cyclictest28564-21kworker/u16:2+efi_rts_wq08:25:123
31783993090,308cyclictest28564-21kworker/u16:2+efi_rts_wq07:27:423
31783993090,308cyclictest26989-21kworker/u16:1+efi_rts_wq12:10:103
31782993090,308cyclictest28564-21kworker/u16:2+efi_rts_wq08:25:132
31783993080,307cyclictest13246-21kworker/u16:0+efi_rts_wq11:40:123
31781993080,307cyclictest27345-21kworker/u16:3+efi_rts_wq09:53:121
31780993080,307cyclictest13246-21kworker/u16:0+efi_rts_wq12:00:130
31783993070,306cyclictest22852-21kworker/u16:2+efi_rts_wq12:38:423
31782993070,306cyclictest22852-21kworker/u16:2+efi_rts_wq12:33:392
31782993070,305cyclictest5447-21kworker/u16:0+efi_rts_wq12:20:142
31781993070,306cyclictest13246-21kworker/u16:0+efi_rts_wq11:40:121
31781993060,305cyclictest5687-21kworker/u16:2+efi_rts_wq09:10:121
31782993050,304cyclictest26989-21kworker/u16:1+efi_rts_wq12:35:142
31781993050,304cyclictest5687-21kworker/u16:2+efi_rts_wq09:30:131
31781993050,304cyclictest5687-21kworker/u16:2+efi_rts_wq09:30:121
31781993050,304cyclictest28564-21kworker/u16:2+efi_rts_wq07:45:131
31780993050,303cyclictest16561-21kworker/u16:3+efi_rts_wq10:50:120
31783993040,303cyclictest26989-21kworker/u16:1+efi_rts_wq12:23:383
31783993040,303cyclictest11554-21kworker/u16:1+efi_rts_wq10:20:133
31781993040,303cyclictest7176-21kworker/u16:3+efi_rts_wq08:42:571
31780993030,302cyclictest26989-21kworker/u16:1+efi_rts_wq12:13:370
31781993020,301cyclictest11554-21kworker/u16:1+efi_rts_wq09:20:111
31780993020,301cyclictest27345-21kworker/u16:3+efi_rts_wq09:40:120
31783993010,300cyclictest11554-21kworker/u16:1+efi_rts_wq10:10:113
31783992980,296cyclictest16561-21kworker/u16:3+efi_rts_wq10:50:103
31783992970,296cyclictest7176-21kworker/u16:3+efi_rts_wq07:32:443
31783992970,296cyclictest27345-21kworker/u16:3+efi_rts_wq09:50:113
31782992970,296cyclictest7176-21kworker/u16:3+efi_rts_wq08:05:142
31781992970,296cyclictest28564-21kworker/u16:2+efi_rts_wq08:30:121
31781992960,294cyclictest13246-21kworker/u16:0+efi_rts_wq11:55:131
31781992940,293cyclictest7176-21kworker/u16:3+efi_rts_wq07:25:141
31781992940,293cyclictest27345-21kworker/u16:3+efi_rts_wq09:40:121
31781992940,293cyclictest26989-21kworker/u16:1+efi_rts_wq12:30:111
31780992920,291cyclictest11554-21kworker/u16:1+efi_rts_wq10:10:120
31780992920,291cyclictest11554-21kworker/u16:1+efi_rts_wq09:15:140
31783992910,290cyclictest11554-21kworker/u16:1+efi_rts_wq09:00:133
31781992910,289cyclictest7176-21kworker/u16:3+efi_rts_wq07:35:131
31783992900,289cyclictest16561-21kworker/u16:3+efi_rts_wq11:20:113
31783992890,288cyclictest15547-21kworker/u16:4+efi_rts_wq11:28:293
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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