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2026-08-07 - 20:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Fri Aug 07, 2026 12:44:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30376362274231,27sleep00-21swapper/007:08:460
30374652258191,52sleep10-21swapper/107:06:561
303787799194188,4cyclictest3109961-21kworker/u8:010:23:050
315657521600,2sleep10-21swapper/110:38:561
30975892620,3chrt0-21swapper/009:20:200
32285932580,5sleep03228589-21ssh12:15:130
108999580,4rtkit-daemon1088-21rtkit-daemon07:45:001
31233012560,4sleep13123298-21idleruntime-cro09:55:011
108999560,4rtkit-daemon1088-21rtkit-daemon10:20:031
108999540,4rtkit-daemon1088-21rtkit-daemon08:22:101
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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