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2026-06-07 - 17:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sun Jun 07, 2026 12:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
39759932321280,27sleep00-21swapper/007:09:210
39756672262192,56sleep10-21swapper/107:05:521
179699640,4rtkit-daemon1795-21rtkit-daemon10:15:200
41284792600,7sleep14128480-21latency_hist11:30:011
179699580,4rtkit-daemon1795-21rtkit-daemon11:05:170
179699570,4rtkit-daemon1795-21rtkit-daemon12:30:100
179699570,4rtkit-daemon1795-21rtkit-daemon12:09:550
179699570,4rtkit-daemon1795-21rtkit-daemon11:17:130
179699560,4rtkit-daemon1795-21rtkit-daemon12:14:320
179699560,4rtkit-daemon1795-21rtkit-daemon10:02:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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