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2026-04-25 - 09:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sat Apr 25, 2026 00:44:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
35143942306271,20sleep10-21swapper/119:06:181
35143942306271,20sleep10-21swapper/119:06:181
35145982245203,28sleep00-21swapper/019:08:290
35145982245203,28sleep00-21swapper/019:08:290
179699770,25rtkit-daemon3685213-21ssh23:47:060
35358352480,1chrt3535539-21/usr/sbin/munin20:00:161
179699440,3rtkit-daemon0-21swapper/000:33:190
179699410,3rtkit-daemon0-21swapper/019:38:010
36815382390,1sleep00-21swapper/023:42:010
36800422390,4sleep13680044-21kernelversion23:40:191
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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