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2026-08-23 - 17:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sun Aug 23, 2026 12:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
35274132263189,59sleep00-21swapper/007:09:430
35273222263187,20sleep10-21swapper/107:08:471
353849021320,2sleep10-21swapper/107:35:061
35275879910498,4cyclictest3603741-21kworker/u8:310:14:130
36880212690,4sleep10-21swapper/111:44:081
352758999683,44cyclictest3595476-21apt-get09:35:141
352758999672,45cyclictest3653462-21apt-get10:55:131
352758999663,43cyclictest3546467-21apt-get07:55:141
352758999663,43cyclictest3532248-21apt-get07:20:151
352758999652,42cyclictest3617288-21apt-get10:05:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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