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2026-04-24 - 20:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Fri Apr 24, 2026 12:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
18497862266190,27sleep00-21swapper/007:07:160
18500372258183,59sleep10-21swapper/107:09:561
179699590,4rtkit-daemon1795-21rtkit-daemon07:43:320
179699580,4rtkit-daemon1795-21rtkit-daemon09:11:171
179699580,4rtkit-daemon1795-21rtkit-daemon09:11:171
20050692570,4sleep02005067-21unixbench_singl11:25:240
179699530,3rtkit-daemon1795-21rtkit-daemon10:38:311
179699510,4rtkit-daemon1795-21rtkit-daemon11:20:401
179699510,3rtkit-daemon1795-21rtkit-daemon09:34:530
179699500,4rtkit-daemon1795-21rtkit-daemon07:11:121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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