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2026-06-23 - 16:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Tue Jun 23, 2026 12:44:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
21122612263202,46sleep00-21swapper/007:06:430
21122562254182,19sleep10-21swapper/107:06:401
214245121530,6sleep12141662-21/usr/sbin/munin08:20:201
21807072740,3chrt0-21swapper/009:35:220
179699600,5rtkit-daemon2161029-21diskmemload11:28:290
179699590,3rtkit-daemon0-21swapper/009:25:170
179699580,4rtkit-daemon0-21swapper/010:04:000
179699570,3rtkit-daemon0-21swapper/009:32:020
179699570,3rtkit-daemon0-21swapper/007:50:290
179699560,3rtkit-daemon0-21swapper/010:10:590
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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