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2026-09-03 - 09:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Thu Sep 03, 2026 00:44:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1508852258185,29sleep10-21swapper/119:07:101
1503392257188,53sleep00-21swapper/019:05:300
2173272910,1chrt217310-21/usr/sbin/munin21:35:011
2493432670,4sleep1249335-21cpuspeed_turbos22:20:141
136599640,3rtkit-daemon1364-21rtkit-daemon20:50:020
2337272630,5sleep10-21swapper/121:56:201
136599630,1rtkit-daemon1364-21rtkit-daemon22:55:190
2941352620,2sleep126-21ksoftirqd/123:25:011
136599620,4rtkit-daemon1364-21rtkit-daemon23:29:471
136599600,4rtkit-daemon1364-21rtkit-daemon23:15:461
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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