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2026-09-08 - 07:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Tue Sep 08, 2026 00:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
39293392283221,48sleep00-21swapper/019:09:160
39289972266191,59sleep10-21swapper/119:05:341
392953299172167,3cyclictest2634323-21kworker/u8:119:34:191
40271842750,3sleep1251rcuc/122:18:251
40455482720,8sleep04045547-21wc22:45:000
40327972670,4chrt4031995-21/usr/sbin/munin22:25:211
136599560,3rtkit-daemon0-21swapper/121:05:501
136599550,4rtkit-daemon1364-21rtkit-daemon20:04:331
136599550,3rtkit-daemon0-21swapper/120:53:121
136599550,3rtkit-daemon0-21swapper/119:46:271
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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