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2026-07-24 - 11:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Fri Jul 24, 2026 00:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
21241192264188,61sleep10-21swapper/119:06:131
21244112256185,20sleep00-21swapper/019:09:200
2124628998377,4cyclictest2305094-21kworker/u8:100:01:120
22856682640,4sleep12285671-21timerandwakeup23:35:221
106799630,7rtkit-daemon1066-21rtkit-daemon22:20:130
22137192570,1sleep12213718-21ssh22:01:261
106799530,4rtkit-daemon1066-21rtkit-daemon21:33:550
106799530,3rtkit-daemon1066-21rtkit-daemon20:29:200
106799500,4rtkit-daemon1066-21rtkit-daemon20:08:430
106799490,3rtkit-daemon1066-21rtkit-daemon00:23:400
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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