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2026-05-20 - 06:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Wed May 20, 2026 00:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19541422326277,35sleep10-21swapper/119:07:511
19540882294252,28sleep00-21swapper/019:07:140
195471421580,7sleep01954601-21/usr/sbin/munin19:10:170
20621872680,3sleep10-21swapper/122:26:031
20012402590,5sleep00-21swapper/021:05:000
179699580,3rtkit-daemon1795-21rtkit-daemon19:45:131
179699540,3rtkit-daemon1795-21rtkit-daemon20:40:111
179699540,3rtkit-daemon0-21swapper/123:55:151
179699540,3rtkit-daemon0-21swapper/121:10:351
179699540,3rtkit-daemon0-21swapper/121:10:351
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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