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2026-07-12 - 23:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sun Jul 12, 2026 12:44:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17956572256182,59sleep00-21swapper/007:06:520
17958872255183,58sleep10-21swapper/107:09:191
179699900,10rtkit-daemon1795-21rtkit-daemon09:48:591
179699610,4rtkit-daemon1795-21rtkit-daemon07:49:291
179699610,4rtkit-daemon1795-21rtkit-daemon07:49:281
19474422550,4sleep00-21swapper/011:20:180
19084662540,4sleep00-21swapper/010:30:220
19084662540,4sleep00-21swapper/010:30:210
179699520,4rtkit-daemon1795-21rtkit-daemon08:30:331
179699510,4rtkit-daemon1795-21rtkit-daemon09:59:261
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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