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2025-12-08 - 18:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Mon Dec 08, 2025 12:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
34876292263187,60sleep10-21swapper/107:08:331
34874652243202,27sleep00-21swapper/007:06:470
34878969918486,86cyclictest3675906-21cstates12:15:161
348789199173131,30cyclictest3675878-21ssh12:15:160
34878969915188,51cyclictest3679440-21expr12:20:181
3487896991404,123cyclictest3665535-21head12:00:211
34878919913648,76cyclictest3679712-21head12:20:210
34878919913628,83cyclictest3668629-21cstates12:05:180
34878969912845,71cyclictest3605694-21cat10:40:171
34878919912740,75cyclictest3605705-21ls10:40:160
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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