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2026-07-22 - 07:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Wed Jul 22, 2026 00:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
38626812270199,25sleep10-21swapper/119:07:071
38627182262188,19sleep00-21swapper/019:07:310
38704702650,4sleep126-21ksoftirqd/119:25:221
106799550,3rtkit-daemon1066-21rtkit-daemon23:56:191
38681482540,4sleep0161rcuc/019:20:170
106799530,3rtkit-daemon1066-21rtkit-daemon19:52:021
39721162480,6sleep13972118-21grep22:25:181
106799480,4rtkit-daemon1066-21rtkit-daemon19:12:221
106799470,3rtkit-daemon1066-21rtkit-daemon22:44:221
106799470,3rtkit-daemon1066-21rtkit-daemon22:07:311
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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