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2026-07-10 - 06:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Fri Jul 10, 2026 00:44:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
190222923420,20sleep126-21ksoftirqd/119:05:291
190213223270,10sleep00-21swapper/019:05:280
179699710,3rtkit-daemon1795-21rtkit-daemon23:59:380
19035862680,5sleep11903580-21gltestperf19:10:181
20483582660,4sleep013-21ksoftirqd/023:08:580
21132212590,10sleep013-21ksoftirqd/000:30:220
179699570,4rtkit-daemon1795-21rtkit-daemon22:08:251
179699560,6rtkit-daemon1795-21rtkit-daemon00:17:230
179699560,6rtkit-daemon1795-21rtkit-daemon00:17:230
179699520,3rtkit-daemon1795-21rtkit-daemon21:10:431
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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