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2026-06-10 - 14:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Wed Jun 10, 2026 00:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
38139492316274,28sleep10-21swapper/119:09:021
38139182258194,43sleep00-21swapper/019:08:420
179699560,5rtkit-daemon1795-21rtkit-daemon22:57:351
179699540,4rtkit-daemon1795-21rtkit-daemon21:59:281
179699510,4rtkit-daemon1795-21rtkit-daemon21:20:021
179699510,4rtkit-daemon1795-21rtkit-daemon20:10:151
179699500,4rtkit-daemon1795-21rtkit-daemon22:20:491
179699500,4rtkit-daemon1795-21rtkit-daemon00:36:181
179699490,4rtkit-daemon1795-21rtkit-daemon22:03:330
179699470,4rtkit-daemon1795-21rtkit-daemon20:53:231
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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