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2026-07-08 - 19:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Wed Jul 08, 2026 12:44:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11312822272185,29sleep00-21swapper/007:07:590
11312822272185,29sleep00-21swapper/007:07:580
11311992256216,27sleep10-21swapper/107:07:051
11311992256216,27sleep10-21swapper/107:07:041
13255172550,4sleep10-21swapper/112:10:011
179699530,2rtkit-daemon1795-21rtkit-daemon08:48:390
179699490,3rtkit-daemon1795-21rtkit-daemon11:26:551
179699480,4rtkit-daemon1795-21rtkit-daemon09:52:561
179699470,3rtkit-daemon1795-21rtkit-daemon11:43:540
179699440,3rtkit-daemon0-21swapper/108:18:181
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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