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2026-08-05 - 20:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Wed Aug 05, 2026 12:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14016302322280,27sleep00-21swapper/007:06:570
14017142316275,27sleep10-21swapper/107:07:511
140204699142136,4cyclictest1476534-21kworker/u8:310:50:261
106799780,22rtkit-daemon0-21swapper/011:33:000
106799690,4rtkit-daemon1066-21rtkit-daemon12:31:451
106799600,4rtkit-daemon1569195-21ssh12:35:491
15494122550,5sleep00-21swapper/012:10:180
106799540,4rtkit-daemon1066-21rtkit-daemon09:32:291
106799510,4rtkit-daemon1066-21rtkit-daemon11:20:070
106799490,4rtkit-daemon1066-21rtkit-daemon08:31:410
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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