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2026-09-07 - 17:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Mon Sep 07, 2026 12:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
22954172274214,45sleep10-21swapper/107:07:551
22951892244192,37sleep00-21swapper/007:05:330
136599680,4rtkit-daemon1364-21rtkit-daemon07:15:070
136599660,3rtkit-daemon1364-21rtkit-daemon08:09:030
136599570,4rtkit-daemon1364-21rtkit-daemon12:31:310
136599550,3rtkit-daemon1364-21rtkit-daemon09:56:060
136599530,4rtkit-daemon1364-21rtkit-daemon12:10:381
136599510,4rtkit-daemon1364-21rtkit-daemon10:49:191
136599510,4rtkit-daemon1364-21rtkit-daemon07:11:390
136599500,4rtkit-daemon1364-21rtkit-daemon09:20:311
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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