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2026-08-15 - 07:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sat Aug 15, 2026 00:44:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
10179672317274,29sleep00-21swapper/019:06:320
10180892262194,52sleep10-21swapper/119:07:491
101841799116111,3cyclictest1212624-21kworker/u8:300:35:120
10708842740,4sleep10-21swapper/121:14:211
10268642650,4chrt1026860-21unin-run19:30:001
101842199652,42cyclictest1188628-21apt-get00:00:131
101842199652,42cyclictest1156816-21apt-get23:15:101
101842199623,39cyclictest1128399-21apt-get22:35:141
101842199621,40cyclictest1103465-21apt-get22:00:131
101842199613,39cyclictest1021114-21apt-get19:15:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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