You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2025-12-26 - 22:27
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Fri Dec 26, 2025 12:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17281902273195,28sleep10-21swapper/107:05:501
17282982255187,53sleep00-21swapper/007:06:590
179699590,6rtkit-daemon0-21swapper/109:32:521
179699590,4rtkit-daemon1795-21rtkit-daemon11:26:270
179699580,4rtkit-daemon1795-21rtkit-daemon07:24:250
179699560,4rtkit-daemon1795-21rtkit-daemon10:34:420
18466282550,10sleep126-21ksoftirqd/110:37:441
179699550,4rtkit-daemon1795-21rtkit-daemon09:02:400
179699550,3rtkit-daemon1795-21rtkit-daemon09:19:450
179699540,4rtkit-daemon1795-21rtkit-daemon10:40:470
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional