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2026-05-30 - 03:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sat May 30, 2026 00:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11650012261183,28sleep00-21swapper/019:09:080
11648672237196,27sleep10-21swapper/119:07:421
179699510,9rtkit-daemon0-21swapper/021:18:560
179699510,3rtkit-daemon1795-21rtkit-daemon22:41:141
179699500,3rtkit-daemon1795-21rtkit-daemon23:46:321
179699490,3rtkit-daemon1795-21rtkit-daemon00:08:140
179699480,9rtkit-daemon0-21swapper/022:18:270
179699470,4rtkit-daemon1795-21rtkit-daemon20:06:531
179699470,3rtkit-daemon1795-21rtkit-daemon21:29:340
12504602470,1sleep01250461-21sh21:58:160
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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