You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-08-19 - 20:58
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Wed Aug 19, 2026 12:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30553662277217,46sleep10-21swapper/107:09:141
30554272258189,53sleep00-21swapper/007:09:540
305553699189183,4cyclictest3096350-21kworker/u8:108:53:240
32289142610,4sleep10-21swapper/112:05:201
31473112570,4sleep10-21swapper/110:08:531
136599550,4rtkit-daemon1364-21rtkit-daemon10:43:421
32193242530,3sleep00-21swapper/011:50:560
136599480,4rtkit-daemon1364-21rtkit-daemon07:24:441
136599470,4rtkit-daemon1364-21rtkit-daemon07:38:090
136599460,3rtkit-daemon1364-21rtkit-daemon11:33:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional