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2026-07-15 - 22:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Wed Jul 15, 2026 12:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
321608523500,11sleep00-21swapper/007:05:330
32165702273196,28sleep10-21swapper/107:09:501
3216715996057,2cyclictest3254962-21kworker/u8:008:49:571
106799570,4rtkit-daemon1066-21rtkit-daemon07:55:381
106799560,5rtkit-daemon1066-21rtkit-daemon10:30:200
321670899543,8cyclictest3334069-21apt-get10:35:150
321670899522,9cyclictest3401441-21apt-get12:00:140
106799520,4rtkit-daemon1066-21rtkit-daemon10:57:331
106799520,4rtkit-daemon1066-21rtkit-daemon09:29:221
106799510,4rtkit-daemon1066-21rtkit-daemon09:24:111
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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