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2026-05-29 - 20:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Fri May 29, 2026 12:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
37251972326285,27sleep00-21swapper/007:05:370
37253632318275,29sleep10-21swapper/107:07:241
179699670,5rtkit-daemon3773216-21latency_hist09:25:010
38067702560,3sleep13806773-21fschecks_count10:10:171
179699560,4rtkit-daemon1795-21rtkit-daemon10:34:330
179699540,4rtkit-daemon1795-21rtkit-daemon12:12:570
179699540,3rtkit-daemon0-21swapper/111:54:000
179699540,3rtkit-daemon0-21swapper/108:18:060
179699530,4rtkit-daemon1795-21rtkit-daemon12:25:240
38227102510,2sleep10-21swapper/110:30:281
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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