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2026-08-21 - 12:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Fri Aug 21, 2026 00:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
37663162264189,59sleep10-21swapper/119:08:481
37663512256190,51sleep00-21swapper/019:09:100
387092721470,3sleep00-21swapper/022:28:560
38984892530,4sleep00-21swapper/023:08:430
38613952510,6sleep00-21swapper/022:15:160
136599500,3rtkit-daemon0-21swapper/120:04:410
136599490,4rtkit-daemon1364-21rtkit-daemon20:37:511
136599490,3rtkit-daemon1364-21rtkit-daemon21:50:361
136599490,3rtkit-daemon1364-21rtkit-daemon19:40:421
136599480,3rtkit-daemon1364-21rtkit-daemon22:40:431
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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