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2026-06-13 - 19:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sat Jun 13, 2026 12:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
27386342325282,29sleep00-21swapper/007:08:310
27387562273209,50sleep10-21swapper/107:09:491
28151192870,1chrt2813930-21/usr/sbin/munin09:45:240
273894799752,44cyclictest2882436-21apt-get11:20:130
179699670,3rtkit-daemon1795-21rtkit-daemon10:42:411
179699650,4rtkit-daemon1795-21rtkit-daemon12:10:121
273894799641,32cyclictest2904264-21apt-get11:50:210
179699630,4rtkit-daemon1795-21rtkit-daemon11:47:180
179699620,4rtkit-daemon0-21swapper/009:34:431
179699610,4rtkit-daemon1795-21rtkit-daemon09:14:070
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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