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2026-07-05 - 18:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sun Jul 05, 2026 12:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
37644692256194,48sleep00-21swapper/007:06:260
37645332250181,52sleep10-21swapper/107:07:081
383486321570,3sleep10-21swapper/109:35:231
38282202540,7sleep00-21swapper/009:27:240
179699470,3rtkit-daemon0-21swapper/112:08:461
179699460,3rtkit-daemon0-21swapper/108:16:591
179699450,3rtkit-daemon0-21swapper/112:33:231
179699450,3rtkit-daemon0-21swapper/108:32:291
179699450,3rtkit-daemon0-21swapper/107:59:221
179699440,3rtkit-daemon0-21swapper/108:35:121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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