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2026-08-20 - 03:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Thu Aug 20, 2026 00:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
5058782262187,59sleep10-21swapper/119:09:301
5057082259188,55sleep00-21swapper/019:07:410
136599680,3rtkit-daemon1364-21rtkit-daemon20:49:060
136599630,16rtkit-daemon1364-21rtkit-daemon22:47:471
50603699612,39cyclictest558107-21apt-get21:15:121
50603699601,32cyclictest694405-21apt-get00:30:151
50603699572,36cyclictest635897-21apt-get23:05:121
6896092560,2sleep10-21swapper/100:22:311
6596602560,4sleep10-21swapper/123:38:241
6596602560,4sleep10-21swapper/123:38:231
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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