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2026-07-09 - 09:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Thu Jul 09, 2026 00:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
27868052264182,19sleep10-21swapper/119:05:271
27875912254214,26sleep00-21swapper/019:08:320
284012121240,4sleep02787819-21cyclictest21:13:570
179699600,4rtkit-daemon1795-21rtkit-daemon23:15:200
179699600,3rtkit-daemon0-21swapper/021:42:190
179699570,3rtkit-daemon0-21swapper/000:38:450
179699560,3rtkit-daemon0-21swapper/022:07:580
179699540,4rtkit-daemon1795-21rtkit-daemon21:17:460
179699530,5rtkit-daemon1795-21rtkit-daemon00:12:040
179699530,3rtkit-daemon0-21swapper/023:23:050
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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