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2026-08-31 - 08:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Mon Aug 31, 2026 00:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
28457482265197,52sleep10-21swapper/119:06:411
28456852253183,54sleep00-21swapper/019:06:030
136599580,6rtkit-daemon1364-21rtkit-daemon21:10:011
28471522550,3sleep10-21swapper/119:10:181
136599550,4rtkit-daemon1364-21rtkit-daemon23:05:300
136599550,4rtkit-daemon1364-21rtkit-daemon21:01:470
136599520,3rtkit-daemon0-21swapper/020:10:130
136599510,4rtkit-daemon1364-21rtkit-daemon21:10:220
136599500,3rtkit-daemon1364-21rtkit-daemon20:31:440
136599490,3rtkit-daemon1364-21rtkit-daemon23:22:500
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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