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2026-08-26 - 13:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Wed Aug 26, 2026 00:44:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
32973662309274,20sleep10-21swapper/119:08:361
32973932291257,19sleep00-21swapper/019:08:530
136599640,4rtkit-daemon1364-21rtkit-daemon22:55:110
136599620,4rtkit-daemon1364-21rtkit-daemon21:15:401
136599580,26rtkit-daemon3406798-21python322:35:020
136599570,3rtkit-daemon0-21swapper/120:35:280
136599570,3rtkit-daemon0-21swapper/120:35:270
136599560,4rtkit-daemon1364-21rtkit-daemon21:34:450
136599560,4rtkit-daemon1364-21rtkit-daemon00:25:130
136599550,3rtkit-daemon1364-21rtkit-daemon23:10:431
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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