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2026-07-12 - 10:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sun Jul 12, 2026 00:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1456392259184,60sleep10-21swapper/119:07:001
1455582259185,59sleep00-21swapper/019:06:060
14607099612,38cyclictest318597-21apt-get23:45:121
14607099602,38cyclictest259020-21apt-get22:30:111
14607099601,38cyclictest177323-21apt-get20:25:151
14607099593,35cyclictest286641-21apt-get23:05:141
14607099591,38cyclictest306829-21apt-get23:30:121
14607099572,34cyclictest294669-21apt-get23:15:161
14607099572,34cyclictest294669-21apt-get23:15:151
14607099552,34cyclictest215183-21apt-get21:35:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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