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2026-08-29 - 15:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sat Aug 29, 2026 12:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
21363632260185,59sleep00-21swapper/007:06:400
21365852257190,51sleep10-21swapper/107:09:041
2136797998176,3cyclictest2153303-21kworker/u8:007:57:070
136599700,4rtkit-daemon1364-21rtkit-daemon07:34:021
136599680,4rtkit-daemon1364-21rtkit-daemon09:37:241
136599660,4rtkit-daemon1364-21rtkit-daemon10:57:241
136599620,4rtkit-daemon1364-21rtkit-daemon11:18:140
213680299612,7cyclictest2239406-21apt-get10:25:151
213680299592,8cyclictest2193476-21apt-get09:20:131
213680299592,7cyclictest2225161-21apt-get10:05:151
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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