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2026-08-02 - 09:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sun Aug 02, 2026 00:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
25122582291251,26sleep00-21swapper/019:08:350
25120532263189,58sleep10-21swapper/119:06:221
2512546997565,8cyclictest2616379-21fwupd22:21:001
25476122680,3chrt2547079-21/usr/sbin/munin20:35:170
26207732610,2sleep00-21swapper/022:27:100
2512543996056,3cyclictest2599248-21kworker/u8:222:21:000
106799600,9rtkit-daemon2647068-21ssh23:00:521
25775182580,2sleep10-21swapper/121:30:201
106799550,3rtkit-daemon0-21swapper/123:52:211
106799550,3rtkit-daemon0-21swapper/122:52:411
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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