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2026-07-08 - 12:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Wed Jul 08, 2026 00:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
36714542262183,19sleep00-21swapper/019:09:500
36714432250169,29sleep10-21swapper/119:09:431
37538512680,1chrt3753850-21/usr/sbin/munin21:50:261
37538512680,1chrt3753850-21/usr/sbin/munin21:50:251
179699550,5rtkit-daemon1795-21rtkit-daemon20:55:341
179699520,4rtkit-daemon1795-21rtkit-daemon23:42:421
179699520,4rtkit-daemon1795-21rtkit-daemon21:19:231
179699500,4rtkit-daemon1795-21rtkit-daemon23:16:451
179699500,4rtkit-daemon1795-21rtkit-daemon21:08:571
179699500,4rtkit-daemon1795-21rtkit-daemon20:12:051
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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