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2025-11-04 - 09:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Tue Nov 04, 2025 00:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19015212259187,57sleep10-21swapper/119:09:341
19012552255187,53sleep00-21swapper/019:06:440
125899640,3rtkit-daemon1257-21rtkit-daemon21:24:490
19780532580,3sleep00-21swapper/021:45:280
19680002520,4sleep10-21swapper/121:32:311
125899520,4rtkit-daemon1257-21rtkit-daemon22:36:540
125899510,4rtkit-daemon1257-21rtkit-daemon22:23:050
125899510,3rtkit-daemon1257-21rtkit-daemon22:57:320
19292962490,4sleep11929300-21switchtime20:15:261
19969252480,4sleep10-21swapper/122:10:271
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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