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2026-07-18 - 18:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sat Jul 18, 2026 12:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
6112272271229,26sleep00-21swapper/007:05:510
6115692256189,51sleep10-21swapper/107:09:331
8133082880,3sleep00-21swapper/012:20:180
611715996858,8cyclictest674589-21fwupd09:27:110
6666792590,1sleep10-21swapper/109:17:081
6917682500,3sleep00-21swapper/009:48:270
611715995016,7cyclictest13-21ksoftirqd/012:15:010
611715995014,5cyclictest13-21ksoftirqd/010:25:000
7544972480,3sleep0754500-21timerwakeupswit11:05:250
611715994614,5cyclictest13-21ksoftirqd/009:45:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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