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2026-09-06 - 07:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sun Sep 06, 2026 00:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15924062261185,60sleep00-21swapper/019:07:100
15908952260195,50sleep10-21swapper/119:05:031
1592955999590,4cyclictest1717463-21kworker/u8:123:16:091
136599570,7rtkit-daemon1364-21rtkit-daemon23:20:140
136599560,3rtkit-daemon0-21swapper/021:27:500
136599540,6rtkit-daemon2812-21urbackupserver:00:07:160
136599540,3rtkit-daemon0-21swapper/023:58:540
136599540,3rtkit-daemon0-21swapper/022:49:340
136599530,3rtkit-daemon0-21swapper/000:23:280
136599530,1rtkit-daemon1364-21rtkit-daemon20:15:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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