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2026-08-06 - 08:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Thu Aug 06, 2026 00:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30215532259184,60sleep10-21swapper/119:08:561
30213872257181,60sleep00-21swapper/019:07:070
106799630,3rtkit-daemon1066-21rtkit-daemon19:28:390
31481172550,5sleep10-21swapper/122:50:251
106799550,4rtkit-daemon1066-21rtkit-daemon00:19:531
106799520,4rtkit-daemon1066-21rtkit-daemon22:30:181
106799510,4rtkit-daemon1066-21rtkit-daemon22:40:391
106799510,4rtkit-daemon1066-21rtkit-daemon21:40:041
106799510,4rtkit-daemon1066-21rtkit-daemon20:32:301
106799510,3rtkit-daemon1066-21rtkit-daemon20:59:371
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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