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2026-06-01 - 05:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Mon Jun 01, 2026 00:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
35488912262188,27sleep10-21swapper/119:09:501
35485542262185,62sleep00-21swapper/019:06:150
359119621720,4sleep03591194-21seq20:55:000
360595821700,8sleep013-21ksoftirqd/021:20:190
36037682770,3sleep10-21swapper/121:17:191
36753312700,4sleep03596924-21diskmemload22:55:170
179699620,5rtkit-daemon3637003-21ssh22:03:011
179699590,4rtkit-daemon3737770-21sh00:22:421
179699590,3rtkit-daemon0-21swapper/122:18:151
179699580,4rtkit-daemon0-21swapper/120:00:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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