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2026-06-08 - 21:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Mon Jun 08, 2026 12:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30901312309267,28sleep10-21swapper/107:09:171
30899592264192,27sleep00-21swapper/007:07:260
3090319995813,14cyclictest3282634-21sed12:25:011
31617002570,4sleep013-21ksoftirqd/009:40:140
3090319995513,12cyclictest3273004-21grep12:10:221
179699550,3rtkit-daemon1795-21rtkit-daemon08:39:391
3090319995413,11cyclictest3264428-21ls12:00:001
3090319995317,10cyclictest3287505-21/usr/sbin/munin12:30:231
3090319995313,9cyclictest3271744-21wc12:10:011
3090319995312,11cyclictest3116742-21latency_hist08:15:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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