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2026-08-16 - 22:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sun Aug 16, 2026 12:44:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17419232266182,68sleep00-21swapper/007:05:340
17430932262188,20sleep10-21swapper/107:08:171
174337299181175,4cyclictest1848689-21kworker/u8:010:39:091
17809522720,2sleep013-21ksoftirqd/008:40:190
19096872620,3sleep00-21swapper/011:55:190
136599570,3rtkit-daemon1364-21rtkit-daemon11:15:370
136599570,3rtkit-daemon0-21swapper/108:56:101
136599560,4rtkit-daemon1364-21rtkit-daemon11:03:261
136599550,4rtkit-daemon1845401-21ssh10:24:331
136599550,4rtkit-daemon1364-21rtkit-daemon11:15:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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