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2026-06-03 - 09:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Wed Jun 03, 2026 00:44:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17271362288225,47sleep00-21swapper/019:05:490
17272122261219,28sleep10-21swapper/119:06:391
179699620,3rtkit-daemon0-21swapper/023:33:191
179699620,3rtkit-daemon0-21swapper/023:33:191
179699590,7rtkit-daemon1795-21rtkit-daemon19:20:080
179699540,4rtkit-daemon1795-21rtkit-daemon22:42:271
179699530,4rtkit-daemon1795-21rtkit-daemon19:13:550
179699500,4rtkit-daemon1795-21rtkit-daemon00:13:580
18878762490,1chrt1887875-21/usr/sbin/munin23:45:241
179699440,5rtkit-daemon1771608-21diskmemload22:28:451
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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