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2026-08-06 - 23:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Thu Aug 06, 2026 12:44:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4618412270209,46sleep10-21swapper/107:08:411
4615872251184,52sleep00-21swapper/007:05:530
5953952560,4sleep1595398-21cpuspeed_turbos11:05:151
6372772530,4sleep0637280-21grep12:00:240
106799500,3rtkit-daemon1066-21rtkit-daemon08:20:350
106799490,4rtkit-daemon1066-21rtkit-daemon12:09:060
5472902470,4sleep10-21swapper/110:00:241
106799460,5rtkit-daemon620734-21ssh11:39:411
462084994516,6cyclictest605807-21taskset11:19:360
106799450,11rtkit-daemon1066-21rtkit-daemon08:18:320
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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