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2025-12-03 - 21:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Wed Dec 03, 2025 12:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
41475572280219,47sleep00-21swapper/007:06:130
41475302252211,26sleep10-21swapper/107:05:561
125899690,4rtkit-daemon1257-21rtkit-daemon08:43:210
125899620,4rtkit-daemon1257-21rtkit-daemon08:23:561
125899560,3rtkit-daemon1257-21rtkit-daemon11:08:280
125899520,4rtkit-daemon1257-21rtkit-daemon09:31:450
125899510,4rtkit-daemon1257-21rtkit-daemon12:15:530
125899490,4rtkit-daemon1257-21rtkit-daemon08:56:321
125899480,4rtkit-daemon1257-21rtkit-daemon09:25:551
125899470,4rtkit-daemon1257-21rtkit-daemon07:22:081
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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