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2026-06-10 - 00:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Tue Jun 09, 2026 12:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
21607592324281,29sleep00-21swapper/007:08:140
21607482274231,29sleep10-21swapper/107:08:061
234221221660,8sleep1251rcuc/112:05:221
23545442610,7sleep00-21swapper/012:22:550
22437712590,4sleep10-21swapper/109:53:241
22447492560,3sleep00-21swapper/009:55:140
179699560,3rtkit-daemon0-21swapper/112:20:211
179699550,3rtkit-daemon0-21swapper/112:37:031
179699550,3rtkit-daemon0-21swapper/109:26:211
22456912540,4sleep12245662-21ssh09:55:231
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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