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2026-04-29 - 19:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Wed Apr 29, 2026 12:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
16060982267184,29sleep00-21swapper/007:07:060
16063472261185,61sleep10-21swapper/107:09:461
17058092770,1chrt1705808-21/usr/sbin/munin10:15:221
179699680,9rtkit-daemon1676100-21sed09:35:241
16964752580,4sleep10-21swapper/110:03:201
179699530,3rtkit-daemon1795-21rtkit-daemon09:15:551
179699500,2rtkit-daemon1795-21rtkit-daemon11:26:561
179699490,4rtkit-daemon1795-21rtkit-daemon10:59:301
179699470,3rtkit-daemon1795-21rtkit-daemon09:07:551
16384092440,2sleep01638407-21awk08:25:220
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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