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2026-08-25 - 04:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Tue Aug 25, 2026 00:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
564612313278,20sleep00-21swapper/019:05:380
565992282214,53sleep10-21swapper/119:07:081
136599640,3rtkit-daemon1364-21rtkit-daemon22:40:501
136599570,3rtkit-daemon1364-21rtkit-daemon21:05:101
1042452540,6sleep096-21kswapd021:03:200
779992520,4sleep0161rcuc/019:59:590
136599520,4rtkit-daemon1364-21rtkit-daemon23:41:371
136599500,4rtkit-daemon1364-21rtkit-daemon00:23:261
136599500,3rtkit-daemon1364-21rtkit-daemon23:47:411
136599500,17rtkit-daemon1364-21rtkit-daemon23:10:250
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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