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2025-11-29 - 11:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sat Nov 29, 2025 00:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
22577952269187,28sleep00-21swapper/019:06:150
22577902264182,19sleep10-21swapper/119:06:121
125899650,3rtkit-daemon1257-21rtkit-daemon00:05:221
23281432620,4sleep12328135-21cron21:40:011
125899620,5rtkit-daemon2391909-21ntp_states23:10:231
125899590,4rtkit-daemon1257-21rtkit-daemon23:01:360
125899570,5rtkit-daemon1257-21rtkit-daemon22:39:231
22818992560,4sleep0161rcuc/020:05:220
125899560,4rtkit-daemon1257-21rtkit-daemon22:55:421
125899550,4rtkit-daemon1257-21rtkit-daemon23:59:511
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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