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2026-07-17 - 22:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Fri Jul 17, 2026 12:46:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15193902273207,51sleep10-21swapper/107:05:371
15194052261218,28sleep00-21swapper/007:05:460
164026921520,4sleep00-21swapper/010:46:370
17027222720,1chrt1578068-21PipeFile:09:34:541
106799710,1rtkit-daemon1066-21rtkit-daemon12:36:090
106799650,4rtkit-daemon1066-21rtkit-daemon12:02:270
151993999621,6cyclictest1601532-21192.168.115.12009:53:441
151993999602,17cyclictest1578068-21PipeFile:09:34:541
151993999601,13cyclictest1622973-21192.168.115.12010:22:221
106799600,6rtkit-daemon1066-21rtkit-daemon11:40:591
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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