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2026-08-25 - 17:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Tue Aug 25, 2026 12:44:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
168805023480,9sleep01688051-21fschecks_time07:05:190
16893042277218,45sleep10-21swapper/107:08:101
136599760,3rtkit-daemon1364-21rtkit-daemon12:21:141
136599570,6rtkit-daemon1364-21rtkit-daemon09:05:120
136599550,3rtkit-daemon1364-21rtkit-daemon11:56:221
136599510,4rtkit-daemon1364-21rtkit-daemon07:30:290
136599510,3rtkit-daemon1364-21rtkit-daemon10:50:351
136599500,3rtkit-daemon1364-21rtkit-daemon11:13:031
18547752470,1chrt1854774-21/usr/sbin/munin11:55:210
18610382450,2sleep10-21swapper/112:05:171
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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