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2026-08-07 - 05:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Fri Aug 07, 2026 00:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13784422269186,27sleep00-21swapper/019:08:120
13782232264222,28sleep10-21swapper/119:05:521
137874199157151,4cyclictest1385177-21kworker/u8:220:04:441
140219821410,5sleep00-21swapper/020:05:160
14627662640,5sleep00-21swapper/021:55:200
14689852570,7sleep1251rcuc/122:04:341
15645182560,3sleep10-21swapper/100:10:151
15161602500,3sleep01516156-21grep23:05:240
15058882450,3sleep00-21swapper/022:52:060
108999440,6rtkit-daemon1398196-21df19:55:150
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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