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2026-05-28 - 14:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Thu May 28, 2026 00:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
304974323980,9sleep00-21swapper/019:05:290
30503912263188,26sleep10-21swapper/119:09:271
179699770,3rtkit-daemon1795-21rtkit-daemon21:12:391
179699730,4rtkit-daemon1795-21rtkit-daemon20:26:441
179699730,3rtkit-daemon1795-21rtkit-daemon20:40:261
179699690,4rtkit-daemon1795-21rtkit-daemon20:37:070
31412712560,4sleep0161rcuc/022:05:150
179699540,4rtkit-daemon1795-21rtkit-daemon19:49:161
32527662520,3chrt0-21swapper/100:39:081
305060099509,10cyclictest3228429-21ls00:05:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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