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2026-07-10 - 20:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Fri Jul 10, 2026 12:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
355527823410,10sleep03554960-21python307:05:040
35570312271199,28sleep10-21swapper/107:06:171
179699740,3rtkit-daemon1795-21rtkit-daemon07:44:581
179699720,3rtkit-daemon1795-21rtkit-daemon12:29:591
179699700,4rtkit-daemon1795-21rtkit-daemon12:13:091
37110862680,4sleep13711084-21sensors_temp11:20:231
179699620,3rtkit-daemon1795-21rtkit-daemon08:55:380
35651112590,3sleep0161rcuc/007:25:270
179699530,4rtkit-daemon1795-21rtkit-daemon11:52:570
179699530,4rtkit-daemon1795-21rtkit-daemon11:44:530
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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