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2026-06-01 - 15:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Mon Jun 01, 2026 12:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9913132289248,27sleep10-21swapper/107:08:151
9914192262184,20sleep00-21swapper/007:09:220
179699580,4rtkit-daemon1795-21rtkit-daemon08:01:130
179699560,4rtkit-daemon1795-21rtkit-daemon11:53:261
179699540,3rtkit-daemon1795-21rtkit-daemon08:34:590
179699520,4rtkit-daemon1795-21rtkit-daemon10:57:461
179699520,4rtkit-daemon1795-21rtkit-daemon09:22:340
179699520,20rtkit-daemon991749-21apt-get07:10:121
179699500,4rtkit-daemon1795-21rtkit-daemon11:36:330
179699500,4rtkit-daemon1795-21rtkit-daemon11:26:200
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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