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2026-05-22 - 07:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Fri May 22, 2026 00:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1339972320279,27sleep10-21swapper/119:08:121
1340542316274,28sleep00-21swapper/019:08:500
2505652790,1chrt250563-21/usr/sbin/munin22:40:160
2809542650,4sleep1280951-21ssh23:20:221
179699490,3rtkit-daemon0-21swapper/022:55:450
179699470,3rtkit-daemon0-21swapper/022:46:200
2877922460,4sleep10-21swapper/123:30:151
179699460,3rtkit-daemon0-21swapper/019:14:470
179699440,5rtkit-daemon1795-21rtkit-daemon19:24:180
179699440,3rtkit-daemon0-21swapper/023:36:500
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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