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2026-08-11 - 08:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Tue Aug 11, 2026 00:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4710312268225,28sleep00-21swapper/019:09:270
4706872257194,47sleep10-21swapper/119:05:461
136599560,4rtkit-daemon1364-21rtkit-daemon21:06:351
136599540,4rtkit-daemon1364-21rtkit-daemon19:48:310
47120799519,10cyclictest657349-21munin-run00:20:010
136599510,4rtkit-daemon1364-21rtkit-daemon23:18:221
136599510,3rtkit-daemon1364-21rtkit-daemon21:27:310
136599500,3rtkit-daemon1364-21rtkit-daemon20:51:000
47120799499,11cyclictest617446-21python323:25:020
136599490,4rtkit-daemon1364-21rtkit-daemon23:29:051
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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