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2026-08-16 - 14:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sun Aug 16, 2026 00:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
762222327254,28sleep10-21swapper/119:05:371
765062267198,54sleep00-21swapper/019:08:400
19717821050,1chrt197176-21/usr/sbin/munin22:50:110
1933672810,11sleep126-21ksoftirqd/122:44:301
1940552780,1chrt193816-21/usr/sbin/munin22:45:150
136599700,4rtkit-daemon1364-21rtkit-daemon21:01:021
136599690,3rtkit-daemon1364-21rtkit-daemon00:38:511
136599680,4rtkit-daemon1364-21rtkit-daemon21:24:451
136599640,4rtkit-daemon1364-21rtkit-daemon23:38:210
1111392570,4sleep1251rcuc/120:35:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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