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2026-08-01 - 18:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sat Aug 01, 2026 12:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
8565082279244,20sleep10-21swapper/107:07:271
8566112261219,28sleep00-21swapper/007:08:330
106799730,4rtkit-daemon1066-21rtkit-daemon12:08:060
9931632700,3sleep10-21swapper/111:03:241
85685599622,40cyclictest1028136-21apt-get11:50:141
85685599613,38cyclictest986579-21apt-get10:55:161
85685599612,40cyclictest883634-21apt-get08:15:131
85685599600,4cyclictest905485-21diskmemload10:38:021
85685199603,9cyclictest909699-21apt-get09:15:140
856855995713,25cyclictest996952-21sh11:08:321
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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