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2026-04-22 - 07:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Wed Apr 22, 2026 00:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
205620923760,29sleep00-21swapper/019:05:220
20574242280239,27sleep10-21swapper/119:09:241
217819821500,1sleep00-21swapper/022:51:190
21245732630,8sleep1261ksoftirqd/121:35:231
179699610,3rtkit-daemon1795-21rtkit-daemon19:40:161
179699610,3rtkit-daemon1795-21rtkit-daemon19:40:151
179699600,8rtkit-daemon0-21swapper/020:06:540
21091492590,4sleep10-21swapper/121:14:501
179699570,4rtkit-daemon1795-21rtkit-daemon23:31:551
179699570,4rtkit-daemon1795-21rtkit-daemon20:25:521
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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