You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-07-01 - 20:47
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Wed Jul 01, 2026 12:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31858712277215,47sleep10-21swapper/107:05:371
31859072257187,55sleep00-21swapper/007:06:000
31982322600,4sleep10-21swapper/107:35:231
32851902530,2sleep00-21swapper/010:15:490
179699530,4rtkit-daemon1795-21rtkit-daemon12:16:171
179699520,4rtkit-daemon1795-21rtkit-daemon11:14:081
179699510,4rtkit-daemon1795-21rtkit-daemon09:37:011
179699500,4rtkit-daemon1795-21rtkit-daemon09:22:491
179699490,3rtkit-daemon1795-21rtkit-daemon08:04:291
179699460,4rtkit-daemon1795-21rtkit-daemon11:21:110
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional