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2026-08-24 - 07:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Mon Aug 24, 2026 00:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9743692285250,20sleep00-21swapper/019:09:240
9743672271230,27sleep10-21swapper/119:09:231
136599690,4rtkit-daemon1364-21rtkit-daemon22:49:470
136599660,3rtkit-daemon1364-21rtkit-daemon20:37:200
136599620,4rtkit-daemon1364-21rtkit-daemon19:56:271
97472799590,11cyclictest1071543-21sh22:15:131
136599570,6rtkit-daemon1364-21rtkit-daemon21:40:140
97472799562,6cyclictest1116879-21apt-get23:20:141
97472799542,5cyclictest1099126-21apt-get22:55:131
97472799542,5cyclictest1042975-21apt-get21:35:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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