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2026-07-28 - 03:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Tue Jul 28, 2026 00:44:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
27619702275191,20sleep10-21swapper/119:06:261
27619372258216,27sleep00-21swapper/019:06:050
276241899171166,3cyclictest2957027-21kworker/u8:000:37:060
106799750,3rtkit-daemon1066-21rtkit-daemon00:20:141
106799690,4rtkit-daemon1066-21rtkit-daemon20:48:450
106799690,4rtkit-daemon1066-21rtkit-daemon19:39:280
106799630,3rtkit-daemon1066-21rtkit-daemon20:23:540
106799620,3rtkit-daemon1066-21rtkit-daemon00:22:320
28459262570,5sleep00-21swapper/021:55:190
106799520,4rtkit-daemon1066-21rtkit-daemon23:30:370
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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