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2026-07-31 - 13:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Fri Jul 31, 2026 00:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1150102290255,20sleep10-21swapper/119:07:131
1148412274199,60sleep00-21swapper/019:05:330
11537799216210,4cyclictest274313-21kworker/u8:023:38:070
106799620,3rtkit-daemon1066-21rtkit-daemon23:30:401
11538299602,30cyclictest276337-21apt-get23:40:121
3082882580,3sleep10-21swapper/100:24:561
11538299572,34cyclictest294973-21apt-get00:05:151
11538299570,27cyclictest267601-21ssh23:28:161
106799530,4rtkit-daemon1066-21rtkit-daemon22:03:131
106799530,4rtkit-daemon1066-21rtkit-daemon21:48:571
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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