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2026-05-14 - 00:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Wed May 13, 2026 12:44:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15618952265185,29sleep00-21swapper/007:08:300
15620002264180,68sleep10-21swapper/107:09:371
17471162740,3sleep10-21swapper/112:13:201
179699640,4rtkit-daemon1795-21rtkit-daemon11:17:511
179699590,4rtkit-daemon1795-21rtkit-daemon07:16:520
17566682570,3sleep10-21swapper/112:25:241
17152062570,6sleep1251rcuc/111:30:191
17470492560,4sleep00-21swapper/012:13:100
17502772550,4sleep00-21swapper/012:17:230
179699540,4rtkit-daemon1795-21rtkit-daemon11:34:590
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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