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2026-04-23 - 01:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Wed Apr 22, 2026 12:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
36832512271192,29sleep00-21swapper/007:06:260
36833662259186,58sleep10-21swapper/107:07:411
37218292790,1chrt3720895-21/usr/sbin/munin08:40:231
38379532630,6sleep10-21swapper/111:39:561
179699430,3rtkit-daemon0-21swapper/008:51:450
368370399410,2cyclictest893-21snmpd10:57:221
3683703994036,2cyclictest3732448-21perf09:10:001
368370399380,2cyclictest3771550-21gpgv10:05:031
3683695993833,3cyclictest3679545-21kworker/0:007:20:170
38565632350,13sleep013-21ksoftirqd/012:05:160
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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