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2026-07-01 - 00:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Tue Jun 30, 2026 12:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
41027402270187,29sleep00-21swapper/007:06:330
41029122253187,51sleep10-21swapper/107:08:241
429262590,4sleep00-21swapper/011:05:360
410323999573,36cyclictest94902-21apt-get12:20:131
179699530,4rtkit-daemon1795-21rtkit-daemon10:36:531
410323999513,5cyclictest45058-21apt-get11:10:151
410323999512,9cyclictest52013-21apt-get11:20:141
410323999512,6cyclictest59141-21apt-get11:30:121
179699510,4rtkit-daemon1795-21rtkit-daemon07:51:421
410323999502,6cyclictest1600-21apt-get10:10:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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