You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-06-14 - 07:44
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sun Jun 14, 2026 00:44:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1895282264187,28sleep00-21swapper/019:06:320
1897202260220,26sleep10-21swapper/119:08:331
3508212650,5sleep00-21swapper/023:43:090
179699580,4rtkit-daemon1795-21rtkit-daemon22:00:450
179699560,4rtkit-daemon1795-21rtkit-daemon22:37:421
179699510,4rtkit-daemon1795-21rtkit-daemon19:29:120
179699500,4rtkit-daemon1795-21rtkit-daemon21:01:201
3686842490,5sleep1251rcuc/100:08:191
179699490,4rtkit-daemon1795-21rtkit-daemon20:59:201
179699470,4rtkit-daemon1795-21rtkit-daemon19:53:361
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional