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2026-07-24 - 18:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Fri Jul 24, 2026 12:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
376972123690,32sleep00-21swapper/007:05:290
37704732319275,29sleep10-21swapper/107:09:191
106799590,7rtkit-daemon1066-21rtkit-daemon11:25:130
3770656995552,2cyclictest3887450-21kworker/u8:011:04:571
106799510,4rtkit-daemon1066-21rtkit-daemon09:37:370
106799510,3rtkit-daemon1066-21rtkit-daemon10:07:190
106799500,4rtkit-daemon1066-21rtkit-daemon10:00:061
106799500,4rtkit-daemon1066-21rtkit-daemon09:17:001
106799500,4rtkit-daemon1066-21rtkit-daemon08:10:401
106799490,3rtkit-daemon1066-21rtkit-daemon09:11:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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