You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-07-07 - 23:46
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Tue Jul 07, 2026 12:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20108792317275,28sleep00-21swapper/007:08:550
20106882264187,28sleep10-21swapper/107:06:531
179699590,2rtkit-daemon1795-21rtkit-daemon12:09:150
179699580,4rtkit-daemon1795-21rtkit-daemon11:37:081
179699520,4rtkit-daemon1795-21rtkit-daemon10:13:010
179699520,4rtkit-daemon1795-21rtkit-daemon10:13:000
179699520,4rtkit-daemon1795-21rtkit-daemon09:43:060
179699500,4rtkit-daemon1795-21rtkit-daemon11:44:230
22163242490,4chrt2216323-21rm12:25:010
179699390,3rtkit-daemon0-21swapper/009:52:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional