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2026-07-16 - 12:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Thu Jul 16, 2026 00:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
68812423950,8sleep10-21swapper/119:05:181
6895762319277,27sleep00-21swapper/019:08:300
106799580,4rtkit-daemon1066-21rtkit-daemon20:30:590
8892312560,1chrt889232-21sensors_temp00:20:251
106799520,4rtkit-daemon1066-21rtkit-daemon23:52:521
106799520,4rtkit-daemon1066-21rtkit-daemon22:13:331
106799520,4rtkit-daemon1066-21rtkit-daemon19:38:050
106799440,3rtkit-daemon1066-21rtkit-daemon23:47:451
68987999427,7cyclictest26-21ksoftirqd/121:45:001
8336482400,4chrt833644-21http23:10:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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