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2026-06-25 - 10:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Thu Jun 25, 2026 00:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
28380192262188,27sleep10-21swapper/119:05:581
28382472251181,26sleep00-21swapper/019:08:270
291179121450,2sleep12911793-21ssh21:41:341
28735112560,5sleep12873510-21dump-pmu-power20:35:011
29742552530,2sleep02974257-21sh23:08:450
179699470,3rtkit-daemon0-21swapper/020:42:410
179699450,3rtkit-daemon0-21swapper/122:56:511
179699450,3rtkit-daemon0-21swapper/122:46:181
179699450,3rtkit-daemon0-21swapper/021:52:540
179699440,3rtkit-daemon0-21swapper/123:01:181
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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