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2026-08-29 - 08:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sat Aug 29, 2026 00:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
5125302277215,47sleep00-21swapper/019:07:120
5125072267194,28sleep10-21swapper/119:06:571
136599670,3rtkit-daemon1364-21rtkit-daemon19:14:531
136599610,4rtkit-daemon1364-21rtkit-daemon22:31:311
136599610,4rtkit-daemon1364-21rtkit-daemon19:55:000
136599610,4rtkit-daemon1364-21rtkit-daemon19:37:441
136599600,4rtkit-daemon1364-21rtkit-daemon23:40:560
136599580,5rtkit-daemon1364-21rtkit-daemon22:55:160
136599580,3rtkit-daemon1364-21rtkit-daemon19:32:001
5919382570,3sleep00-21swapper/021:52:040
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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