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2026-07-06 - 19:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Mon Jul 06, 2026 12:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
29007242255184,57sleep10-21swapper/107:09:031
28990562236192,28sleep00-21swapper/007:05:070
303150321540,4sleep1251rcuc/110:55:231
30134072660,3sleep00-21swapper/010:31:340
179699570,4rtkit-daemon1795-21rtkit-daemon10:16:551
29156132550,5sleep10-21swapper/107:45:151
179699520,4rtkit-daemon1795-21rtkit-daemon07:56:591
179699510,4rtkit-daemon1795-21rtkit-daemon09:30:411
179699490,4rtkit-daemon1795-21rtkit-daemon10:39:081
179699490,4rtkit-daemon1795-21rtkit-daemon09:11:500
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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