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2026-07-06 - 06:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Mon Jul 06, 2026 00:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
12592132260188,56sleep00-21swapper/019:08:270
12590202251192,44sleep10-21swapper/119:06:211
138145921110,4sleep01381458-21idleruntime-cro22:45:000
179699730,4rtkit-daemon1795-21rtkit-daemon21:52:371
125950999590,1cyclictest0-21swapper/121:15:111
125950999533,7cyclictest1408543-21apt-get23:20:151
179699520,4rtkit-daemon1795-21rtkit-daemon22:41:321
179699510,4rtkit-daemon1795-21rtkit-daemon23:08:130
179699510,3rtkit-daemon1795-21rtkit-daemon23:32:011
179699510,3rtkit-daemon1795-21rtkit-daemon21:41:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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