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2026-06-13 - 13:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sat Jun 13, 2026 00:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11009482313269,28sleep10-21swapper/119:06:581
11008702311268,28sleep00-21swapper/019:06:070
179699600,4rtkit-daemon0-21swapper/123:21:441
179699570,3rtkit-daemon0-21swapper/121:05:121
179699570,3rtkit-daemon0-21swapper/119:45:121
179699570,3rtkit-daemon0-21swapper/119:40:111
179699560,4rtkit-daemon1795-21rtkit-daemon22:19:281
179699560,3rtkit-daemon0-21swapper/120:36:371
179699540,4rtkit-daemon1795-21rtkit-daemon23:46:211
179699540,4rtkit-daemon1795-21rtkit-daemon23:46:201
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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