You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-08-21 - 19:10
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Fri Aug 21, 2026 12:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11841452262204,44sleep10-21swapper/107:07:541
11841642256214,27sleep00-21swapper/007:08:050
128198921550,2sleep10-21swapper/110:17:371
13292432770,5sleep01329246-21gltestperf11:25:170
136599720,3rtkit-daemon1364-21rtkit-daemon12:35:210
1184443996014,12cyclictest1247851-21/usr/sbin/munin09:30:010
1184443995914,11cyclictest1304303-21latency_hist10:50:010
1184443995814,11cyclictest1279558-21latency_hist10:15:010
1184443995715,11cyclictest1373644-21latency_hist12:30:010
1184443995714,12cyclictest1333460-21sed11:30:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional