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2026-06-08 - 09:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Mon Jun 08, 2026 00:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14395352239198,27sleep00-21swapper/019:07:340
14394242237195,28sleep10-21swapper/119:06:231
179699840,4rtkit-daemon1795-21rtkit-daemon20:50:240
179699740,13rtkit-daemon1795-21rtkit-daemon22:22:021
143988799592,38cyclictest1632169-21apt-get00:25:140
179699550,4rtkit-daemon1795-21rtkit-daemon22:31:180
143988799530,38cyclictest1487747-21diskmemload22:17:470
179699520,4rtkit-daemon1795-21rtkit-daemon22:22:390
179699520,3rtkit-daemon1795-21rtkit-daemon22:55:350
143988799522,33cyclictest1559156-21apt-get22:45:130
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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