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2026-09-05 - 15:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sat Sep 05, 2026 12:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
41308362274233,27sleep00-21swapper/007:09:240
41306512270186,20sleep10-21swapper/107:07:261
418193821590,4sleep10-21swapper/109:12:481
4131017997369,3cyclictest4161095-21kworker/u8:208:35:251
136599730,4rtkit-daemon1364-21rtkit-daemon12:30:321
136599710,4rtkit-daemon1364-21rtkit-daemon11:10:311
136599680,4rtkit-daemon1364-21rtkit-daemon12:16:161
136599510,3rtkit-daemon1364-21rtkit-daemon11:09:411
136599490,3rtkit-daemon1364-21rtkit-daemon09:09:561
41600052480,7sleep14160000-21fschecks_count08:20:181
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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