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2026-06-02 - 12:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Tue Jun 02, 2026 00:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26496742245211,19sleep10-21swapper/119:06:241
26495842237197,26sleep00-21swapper/019:05:330
179699580,4rtkit-daemon1795-21rtkit-daemon23:35:001
179699550,4rtkit-daemon1795-21rtkit-daemon22:38:551
179699520,4rtkit-daemon1795-21rtkit-daemon21:44:471
179699510,4rtkit-daemon1795-21rtkit-daemon19:33:591
179699510,4rtkit-daemon1795-21rtkit-daemon00:29:080
179699500,4rtkit-daemon1795-21rtkit-daemon20:56:290
179699500,4rtkit-daemon1795-21rtkit-daemon20:54:470
179699490,4rtkit-daemon1795-21rtkit-daemon20:29:580
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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