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2025-12-10 - 11:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Wed Dec 10, 2025 00:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
41756972265225,26sleep00-21swapper/019:06:470
41756342262186,61sleep10-21swapper/119:06:111
41761239914254,76cyclictest153055-21/usr/sbin/munin00:00:270
41761269913753,72cyclictest153085-21grep00:00:261
125899570,4rtkit-daemon1257-21rtkit-daemon23:53:300
125899560,4rtkit-daemon1257-21rtkit-daemon20:13:090
125899540,4rtkit-daemon1257-21rtkit-daemon20:25:480
125899510,7rtkit-daemon0-21swapper/100:34:221
125899510,4rtkit-daemon1257-21rtkit-daemon23:56:460
125899500,4rtkit-daemon1257-21rtkit-daemon20:07:310
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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