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2026-07-23 - 09:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Thu Jul 23, 2026 00:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30137382257189,52sleep00-21swapper/019:09:120
30134402250182,52sleep10-21swapper/119:05:591
106799530,8rtkit-daemon0-21swapper/019:49:060
106799520,3rtkit-daemon0-21swapper/021:58:360
30501262510,1chrt3050125-21/usr/sbin/munin20:35:181
31292512500,3sleep10-21swapper/122:38:331
106799500,3rtkit-daemon0-21swapper/020:04:280
106799470,3rtkit-daemon0-21swapper/020:46:020
31495692450,2sleep10-21swapper/123:05:141
32143672430,4sleep00-21swapper/000:34:590
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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