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2026-07-29 - 19:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Wed Jul 29, 2026 12:44:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
35444812269227,27sleep00-21swapper/007:09:520
35440972256181,60sleep10-21swapper/107:05:441
36005352750,3sleep10-21swapper/109:16:251
36232582520,3sleep00-21swapper/009:46:430
106799510,6rtkit-daemon3632544-21apt-get10:00:131
36352162490,4sleep00-21swapper/010:03:290
106799490,3rtkit-daemon0-21swapper/007:27:250
106799450,3rtkit-daemon0-21swapper/007:46:090
106799440,3rtkit-daemon0-21swapper/009:38:350
35455982420,5sleep03545601-21pmu-power07:10:220
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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