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2026-08-22 - 23:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sat Aug 22, 2026 12:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2412162273231,28sleep10-21swapper/107:09:401
2400692271204,52sleep00-21swapper/007:05:230
3730172790,8sleep0373021-21unixbench_multi11:05:250
136599590,4rtkit-daemon1364-21rtkit-daemon09:05:160
136599560,3rtkit-daemon0-21swapper/110:23:011
136599550,4rtkit-daemon1364-21rtkit-daemon08:58:180
136599550,4rtkit-daemon1364-21rtkit-daemon08:31:340
136599540,3rtkit-daemon0-21swapper/112:28:251
136599540,3rtkit-daemon0-21swapper/112:00:011
136599530,4rtkit-daemon1364-21rtkit-daemon10:02:360
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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