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2026-06-17 - 08:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Wed Jun 17, 2026 00:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
16719512270191,26sleep10-21swapper/119:06:531
16718572260219,27sleep00-21swapper/019:05:520
18063572790,4sleep10-21swapper/123:05:261
17812532720,5sleep00-21swapper/022:31:110
17510962700,1chrt1751098-21if_err_enp2s021:50:181
179699660,6rtkit-daemon1825020-21seq23:31:011
179699570,3rtkit-daemon0-21swapper/122:11:281
179699560,4rtkit-daemon0-21swapper/122:30:161
179699550,3rtkit-daemon0-21swapper/123:21:191
179699550,3rtkit-daemon0-21swapper/123:11:181
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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