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2026-07-31 - 19:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Fri Jul 31, 2026 12:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17704292271214,42sleep10-21swapper/107:08:431
17702652263190,27sleep00-21swapper/007:06:580
106799620,4rtkit-daemon1066-21rtkit-daemon07:47:031
19671672600,4sleep01572373-21urbackupserver:12:25:020
106799560,4rtkit-daemon1066-21rtkit-daemon11:19:041
106799560,4rtkit-daemon1066-21rtkit-daemon11:19:041
19736002550,2sleep00-21swapper/012:32:100
106799550,4rtkit-daemon1066-21rtkit-daemon12:20:541
106799540,4rtkit-daemon1066-21rtkit-daemon11:24:460
106799540,4rtkit-daemon1066-21rtkit-daemon07:14:461
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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