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2026-08-08 - 19:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sat Aug 08, 2026 12:44:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
21898062337262,20sleep10-21swapper/107:07:281
21899312315272,28sleep00-21swapper/007:08:460
22802172760,4sleep013-21ksoftirqd/010:04:190
22824422740,4sleep10-21swapper/110:05:571
108999580,4rtkit-daemon1088-21rtkit-daemon11:32:220
108999570,4rtkit-daemon1088-21rtkit-daemon07:51:230
23496182540,12sleep126-21ksoftirqd/111:35:181
108999530,5rtkit-daemon1088-21rtkit-daemon09:47:181
108999530,4rtkit-daemon1088-21rtkit-daemon10:11:160
108999530,4rtkit-daemon1088-21rtkit-daemon09:54:040
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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