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2026-08-24 - 16:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Mon Aug 24, 2026 12:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26258122322279,29sleep00-21swapper/007:06:510
26260562263195,53sleep10-21swapper/107:09:151
267648021440,4sleep10-21swapper/109:10:221
27872022630,4sleep02787200-21cut11:50:200
27725462610,4sleep02772544-21seq11:30:150
136599550,4rtkit-daemon1364-21rtkit-daemon07:46:550
27702262500,7sleep00-21swapper/011:25:260
136599460,3rtkit-daemon0-21swapper/008:05:000
136599450,3rtkit-daemon0-21swapper/007:44:390
136599430,3rtkit-daemon0-21swapper/008:18:470
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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