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2026-07-14 - 10:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Tue Jul 14, 2026 00:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139624424220,9sleep10-21swapper/119:05:231
13971102257183,58sleep00-21swapper/019:06:090
14138082700,5sleep10-21swapper/119:50:011
124499550,4rtkit-daemon1243-21rtkit-daemon23:51:201
124499520,4rtkit-daemon1243-21rtkit-daemon22:34:051
124499510,4rtkit-daemon1243-21rtkit-daemon20:30:441
124499510,4rtkit-daemon1243-21rtkit-daemon19:22:231
15602212500,1chrt1560222-21/usr/sbin/munin23:30:231
124499500,4rtkit-daemon1243-21rtkit-daemon22:40:080
124499500,4rtkit-daemon1243-21rtkit-daemon20:58:250
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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