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2025-11-02 - 18:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sun Nov 02, 2025 12:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11598362265187,19sleep10-21swapper/107:05:301
11603522248180,52sleep00-21swapper/007:08:450
122602621570,2sleep00-21swapper/009:30:470
125879121520,4sleep00-21swapper/010:14:130
132334621400,4sleep10-21swapper/111:35:281
125899630,6rtkit-daemon1257-21rtkit-daemon12:16:200
125899600,4rtkit-daemon0-21swapper/111:05:131
125899590,3rtkit-daemon0-21swapper/108:34:361
125899570,6rtkit-daemon1293559-21ntpd08:38:071
125899570,4rtkit-daemon1257-21rtkit-daemon11:02:530
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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