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2026-09-08 - 23:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Tue Sep 08, 2026 12:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
137734823390,10sleep00-21swapper/007:05:270
13781982258190,52sleep10-21swapper/107:09:221
137842999180175,3cyclictest1513078-21kworker/u8:111:57:180
136599740,4rtkit-daemon1364-21rtkit-daemon11:22:421
14788352720,3sleep00-21swapper/010:24:380
15271732530,5sleep10-21swapper/111:32:221
136599520,3rtkit-daemon1364-21rtkit-daemon09:40:351
14232102510,4sleep01423185-21fschecks_time09:00:160
136599510,4rtkit-daemon1364-21rtkit-daemon10:35:481
136599510,3rtkit-daemon1364-21rtkit-daemon10:43:040
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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