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2026-08-27 - 22:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Thu Aug 27, 2026 12:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
39720572264197,52sleep00-21swapper/007:09:070
39717402242199,29sleep10-21swapper/107:05:411
401526621350,3sleep10-21swapper/108:55:071
40204572750,4sleep14020430-21unixbench_multi09:05:241
41222342680,4sleep00-21swapper/011:33:220
136599560,4rtkit-daemon1364-21rtkit-daemon11:15:431
136599560,3rtkit-daemon0-21swapper/011:05:380
136599550,4rtkit-daemon1364-21rtkit-daemon11:23:220
136599550,3rtkit-daemon0-21swapper/012:19:150
136599550,3rtkit-daemon0-21swapper/009:59:540
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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