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2026-07-27 - 13:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Mon Jul 27, 2026 00:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
36519812274214,45sleep00-21swapper/019:06:040
36522472260185,59sleep10-21swapper/119:08:581
106799760,4rtkit-daemon1066-21rtkit-daemon22:16:381
106799710,4rtkit-daemon1066-21rtkit-daemon22:58:261
106799630,19rtkit-daemon1066-21rtkit-daemon21:45:470
38406802570,3sleep03840684-21needreboot00:15:210
38463312560,1sleep00-21swapper/000:22:410
106799560,3rtkit-daemon1066-21rtkit-daemon23:33:330
38132762510,4sleep03813275-21seq23:39:140
106799510,4rtkit-daemon1066-21rtkit-daemon19:17:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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