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2026-06-30 - 12:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Tue Jun 30, 2026 00:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
24653622281219,48sleep10-21swapper/119:08:341
24654412270188,28sleep00-21swapper/019:09:240
179699540,5rtkit-daemon1795-21rtkit-daemon00:25:121
25889112510,4sleep10-21swapper/122:53:041
179699500,3rtkit-daemon1795-21rtkit-daemon23:42:271
179699500,3rtkit-daemon1795-21rtkit-daemon22:05:531
179699500,3rtkit-daemon1795-21rtkit-daemon21:42:091
179699490,3rtkit-daemon1795-21rtkit-daemon20:04:561
179699470,3rtkit-daemon1795-21rtkit-daemon20:44:021
246562799462,11cyclictest2593413-21grep23:00:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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