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2026-08-03 - 18:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Mon Aug 03, 2026 12:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
32773212312267,29sleep00-21swapper/007:05:100
32788812267193,35sleep10-21swapper/107:07:491
106799740,4rtkit-daemon1066-21rtkit-daemon09:10:270
106799680,4rtkit-daemon1066-21rtkit-daemon07:41:360
327924599664,8cyclictest3407930-21apt-get10:55:151
33529032590,2sleep10-21swapper/109:40:431
34415372570,4sleep10-21swapper/111:40:151
34183232530,4sleep10-21swapper/111:08:541
106799530,3rtkit-daemon0-21swapper/009:49:110
106799500,3rtkit-daemon1066-21rtkit-daemon12:09:540
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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