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2026-06-12 - 08:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Fri Jun 12, 2026 00:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
200303223480,8sleep12002789-21/usr/sbin/munin19:05:201
20041772312270,28sleep00-21swapper/019:06:070
204164421580,3sleep126-21ksoftirqd/120:35:231
179699600,3rtkit-daemon1795-21rtkit-daemon20:20:151
179699560,3rtkit-daemon0-21swapper/023:46:531
179699540,4rtkit-daemon1795-21rtkit-daemon22:07:160
21211382510,5sleep02120992-21latency_hist22:40:010
179699480,4rtkit-daemon1795-21rtkit-daemon19:39:520
179699480,3rtkit-daemon1795-21rtkit-daemon22:21:131
20782292460,3sleep12054161-21diskmemload21:40:241
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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