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2026-09-12 - 01:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Fri Sep 11, 2026 12:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
28522802280221,44sleep00-21swapper/007:05:290
28528872267184,20sleep10-21swapper/107:06:231
136599690,3rtkit-daemon1364-21rtkit-daemon12:27:530
29687322670,3sleep10-21swapper/110:44:561
29120402670,5sleep10-21swapper/109:23:131
30290812590,3sleep13029080-21head12:10:211
29243032570,6sleep10-21swapper/109:40:201
136599520,3rtkit-daemon1364-21rtkit-daemon12:05:470
136599510,3rtkit-daemon1364-21rtkit-daemon09:34:480
136599490,3rtkit-daemon1364-21rtkit-daemon09:44:510
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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