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2026-05-26 - 11:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Tue May 26, 2026 00:44:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
67302423610,16sleep1251rcuc/119:05:181
6743292265187,28sleep00-21swapper/019:08:090
179699660,4rtkit-daemon1795-21rtkit-daemon22:07:590
7732432630,4sleep10-21swapper/122:16:361
179699630,4rtkit-daemon1795-21rtkit-daemon22:44:450
179699620,4rtkit-daemon1795-21rtkit-daemon21:47:240
7776272600,4sleep10-21swapper/122:23:081
179699580,4rtkit-daemon1795-21rtkit-daemon23:22:261
7030002570,4sleep0702995-21munin-plugin-st20:19:590
179699570,3rtkit-daemon1795-21rtkit-daemon23:19:030
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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