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2026-08-18 - 22:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Tue Aug 18, 2026 12:44:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
39886882262193,53sleep10-21swapper/107:09:061
39883872259182,62sleep00-21swapper/007:05:530
136599650,6rtkit-daemon4004801-21irqstats07:45:190
136599650,6rtkit-daemon4004801-21irqstats07:45:190
136599560,5rtkit-daemon4093699-21sh10:28:260
136599560,3rtkit-daemon0-21swapper/009:42:380
136599550,4rtkit-daemon0-21swapper/007:13:490
136599550,3rtkit-daemon0-21swapper/011:35:370
136599550,3rtkit-daemon0-21swapper/010:08:420
41614682540,6sleep10-21swapper/112:05:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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