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2026-06-16 - 19:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Tue Jun 16, 2026 12:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
296732280246,19sleep10-21swapper/107:08:221
295492276191,28sleep00-21swapper/007:07:020
179699780,3rtkit-daemon1795-21rtkit-daemon07:59:350
179699650,3rtkit-daemon1795-21rtkit-daemon09:58:371
1674452600,10sleep0161rcuc/011:09:370
179699560,4rtkit-daemon1795-21rtkit-daemon11:36:281
179699530,4rtkit-daemon1795-21rtkit-daemon09:34:051
1878232520,2sleep00-21swapper/011:36:050
179699520,4rtkit-daemon1795-21rtkit-daemon11:13:300
1498502520,4sleep0149286-21/usr/sbin/munin10:45:200
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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