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2026-04-25 - 16:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sat Apr 25, 2026 12:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9736582267185,68sleep10-21swapper/107:06:451
9736872238196,28sleep00-21swapper/007:07:050
110837621270,2sleep10-21swapper/110:59:201
97408499672,43cyclictest1136583-21apt-get11:35:140
179699630,6rtkit-daemon1795-21rtkit-daemon12:03:051
97408499612,41cyclictest989531-21apt-get07:45:160
97408499610,9cyclictest1129312-21memory11:25:200
97408499602,6cyclictest1174575-21apt-get12:25:140
179699600,3rtkit-daemon1795-21rtkit-daemon10:15:571
97408499572,8cyclictest1015350-21apt-get08:50:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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