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2026-06-26 - 18:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Fri Jun 26, 2026 12:44:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
35692942268226,28sleep10-21swapper/107:06:121
35693562260219,27sleep00-21swapper/007:06:520
37118872550,7sleep00-21swapper/011:22:590
179699540,4rtkit-daemon1795-21rtkit-daemon10:26:190
179699490,3rtkit-daemon1795-21rtkit-daemon12:33:260
179699480,4rtkit-daemon1795-21rtkit-daemon07:27:021
179699460,4rtkit-daemon3629021-21apt-get09:25:131
179699460,3rtkit-daemon1795-21rtkit-daemon10:02:360
179699460,3rtkit-daemon1795-21rtkit-daemon08:08:381
179699460,3rtkit-daemon1795-21rtkit-daemon08:08:381
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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