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2026-08-03 - 11:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Mon Aug 03, 2026 00:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
16142332287221,51sleep10-21swapper/119:05:231
16155352265189,43sleep00-21swapper/019:08:020
161583699199194,3cyclictest1643156-21kworker/u8:120:20:230
17733692580,4sleep10-21swapper/123:33:441
1615841995515,11cyclictest1664430-21diskmemload23:49:561
106799540,4rtkit-daemon1066-21rtkit-daemon19:45:311
1615841995317,11cyclictest1664430-21diskmemload23:27:121
1615841995313,13cyclictest1756696-21/usr/sbin/munin23:10:231
1615841995216,12cyclictest792-21runrttasks23:42:051
1615841995215,8cyclictest1-21systemd22:30:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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