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2026-05-28 - 21:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Thu May 28, 2026 12:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4822242265188,28sleep10-21swapper/107:08:161
4823892262189,19sleep00-21swapper/007:09:580
6050462660,5sleep10-21swapper/110:48:141
179699630,4rtkit-daemon1795-21rtkit-daemon11:48:200
6355712560,4sleep00-21swapper/011:29:420
179699540,4rtkit-daemon1795-21rtkit-daemon11:41:321
179699540,4rtkit-daemon1795-21rtkit-daemon07:42:431
5695662530,4sleep1569569-21gltestperf10:00:171
179699510,3rtkit-daemon1795-21rtkit-daemon09:48:421
179699500,4rtkit-daemon1795-21rtkit-daemon08:58:061
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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