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2026-08-10 - 11:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Mon Aug 10, 2026 00:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13432002281214,52sleep00-21swapper/019:05:200
13446472262189,27sleep10-21swapper/119:09:321
134484999126120,4cyclictest1419946-21kworker/u8:121:57:251
14710322630,3sleep10-21swapper/122:51:571
134484999583,8cyclictest1525201-21apt-get00:05:191
134484999542,7cyclictest1377014-21apt-get20:30:131
134484999542,6cyclictest1357361-21apt-get19:40:121
134484499542,7cyclictest1385285-21apt-get20:50:110
134484499542,6cyclictest1449864-21apt-get22:25:130
134484499542,5cyclictest1465119-21apt-get22:45:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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