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2026-06-18 - 14:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Thu Jun 18, 2026 00:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7592442266185,29sleep10-21swapper/119:08:141
7590662243201,27sleep00-21swapper/019:06:160
179699540,4rtkit-daemon1795-21rtkit-daemon21:50:211
8138152530,4chrt0-21swapper/021:15:270
179699510,3rtkit-daemon1795-21rtkit-daemon19:47:430
179699500,3rtkit-daemon1795-21rtkit-daemon19:40:530
179699500,3rtkit-daemon1795-21rtkit-daemon19:13:361
7982212480,4sleep00-21swapper/020:45:100
179699480,3rtkit-daemon1795-21rtkit-daemon23:58:010
8796522460,7sleep126-21ksoftirqd/122:45:171
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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