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2026-07-18 - 04:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sat Jul 18, 2026 00:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31522242263189,58sleep10-21swapper/119:09:111
31519232251190,20sleep00-21swapper/019:05:550
33613682750,4sleep0161rcuc/000:31:370
106799690,21rtkit-daemon1066-21rtkit-daemon00:22:260
33064592670,4sleep13306458-21awk23:20:221
106799580,4rtkit-daemon1066-21rtkit-daemon19:15:090
33140052550,4sleep13314004-21ntp_states23:30:221
106799550,4rtkit-daemon1066-21rtkit-daemon20:04:161
106799510,4rtkit-daemon1066-21rtkit-daemon21:20:291
106799500,3rtkit-daemon1066-21rtkit-daemon19:33:180
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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