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2026-07-01 - 13:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Wed Jul 01, 2026 00:44:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15674622295260,19sleep10-21swapper/119:05:201
15688042259186,59sleep00-21swapper/019:08:130
173227221530,4sleep1251rcuc/123:48:351
179699630,5rtkit-daemon1795-21rtkit-daemon21:40:211
179699530,4rtkit-daemon1795-21rtkit-daemon23:21:071
179699520,4rtkit-daemon1795-21rtkit-daemon19:49:091
179699500,3rtkit-daemon0-21swapper/021:05:220
179699480,4rtkit-daemon1795-21rtkit-daemon19:32:031
179699480,3rtkit-daemon0-21swapper/021:25:190
179699480,3rtkit-daemon0-21swapper/020:25:150
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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