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2026-06-28 - 18:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sun Jun 28, 2026 12:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17206382318275,27sleep00-21swapper/007:07:550
17205892313272,27sleep10-21swapper/107:07:231
172287521100,4sleep11722860-21perf07:15:001
18445822650,4sleep10-21swapper/110:53:281
18877772530,9sleep013-21ksoftirqd/011:52:360
179699490,5rtkit-daemon1834888-21apt-get10:40:121
179699450,3rtkit-daemon0-21swapper/012:10:070
172097699457,7cyclictest13-21ksoftirqd/007:20:010
179699430,3rtkit-daemon0-21swapper/007:22:000
1720979994311,3cyclictest141rcu_preempt12:25:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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