You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-05-27 - 00:02
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Tue May 26, 2026 12:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
23297102277233,29sleep10-21swapper/107:07:001
23298222260178,28sleep00-21swapper/007:08:120
179699610,3rtkit-daemon1795-21rtkit-daemon11:37:480
179699560,4rtkit-daemon1795-21rtkit-daemon12:26:530
179699540,4rtkit-daemon1795-21rtkit-daemon09:58:361
179699530,4rtkit-daemon1795-21rtkit-daemon11:08:091
179699510,4rtkit-daemon1795-21rtkit-daemon12:36:301
179699480,4rtkit-daemon1795-21rtkit-daemon11:49:460
179699480,4rtkit-daemon1795-21rtkit-daemon08:52:460
179699470,4rtkit-daemon1795-21rtkit-daemon09:37:091
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional