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2026-06-28 - 12:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sun Jun 28, 2026 00:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
883862270212,43sleep10-21swapper/119:08:571
881762263191,27sleep00-21swapper/019:06:410
179699670,4rtkit-daemon1795-21rtkit-daemon21:17:270
179699620,3rtkit-daemon1795-21rtkit-daemon20:05:251
179699610,4rtkit-daemon1795-21rtkit-daemon23:45:571
179699590,3rtkit-daemon0-21swapper/021:24:391
1730442580,3sleep0161rcuc/021:58:390
88642995613,26cyclictest233521-21sh23:21:390
8864299553,9cyclictest217189-21apt-get23:00:150
8864299542,9cyclictest267025-21apt-get00:10:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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