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2026-08-19 - 05:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Wed Aug 19, 2026 00:44:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14343322269185,19sleep00-21swapper/019:05:270
14348692256188,52sleep10-21swapper/119:05:441
14353859910495,7cyclictest1560115-21fwupd22:56:250
1435390997672,3cyclictest1536870-21kworker/u8:022:56:251
136599630,19rtkit-daemon1585926-21python323:35:051
16242572620,4sleep10-21swapper/100:30:011
136599560,3rtkit-daemon1364-21rtkit-daemon22:40:550
136599520,4rtkit-daemon1364-21rtkit-daemon00:14:211
136599510,4rtkit-daemon1364-21rtkit-daemon21:19:530
136599500,4rtkit-daemon1364-21rtkit-daemon00:18:051
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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