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2026-07-25 - 20:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sat Jul 25, 2026 12:44:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
28922972267183,20sleep00-21swapper/007:08:000
28923192254183,55sleep10-21swapper/107:08:141
2892597998475,7cyclictest2937397-21fwupd08:55:531
106799580,3rtkit-daemon0-21swapper/011:01:131
106799580,3rtkit-daemon0-21swapper/007:32:511
106799550,4rtkit-daemon1066-21rtkit-daemon07:11:540
106799540,4rtkit-daemon1066-21rtkit-daemon07:55:130
29516752530,3sleep10-21swapper/109:20:251
106799530,4rtkit-daemon1066-21rtkit-daemon11:27:521
106799510,22rtkit-daemon1572373-21urbackupserver:09:15:241
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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