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2026-08-04 - 11:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Tue Aug 04, 2026 00:44:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7384442266186,28sleep10-21swapper/119:09:091
7383972261220,26sleep00-21swapper/019:08:400
84511621460,4sleep0161rcuc/022:25:160
86858921210,4sleep10-21swapper/122:55:231
93071521090,4sleep1251rcuc/100:20:141
86313021080,4sleep00-21swapper/022:48:560
738638999688,6cyclictest822018-21kworker/u8:122:00:120
106799750,4rtkit-daemon0-21swapper/121:50:051
106799650,3rtkit-daemon0-21swapper/100:16:421
9017232580,4sleep00-21swapper/023:40:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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