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2026-08-22 - 09:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sat Aug 22, 2026 00:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
28366662276215,46sleep00-21swapper/019:09:340
28365352265211,39sleep10-21swapper/119:08:091
283681099200194,4cyclictest2894502-21kworker/u8:221:42:561
284728221080,4sleep02847257-21munin-run19:35:000
28680342660,7sleep00-21swapper/020:25:170
136599630,3rtkit-daemon1364-21rtkit-daemon20:40:261
29343012570,4sleep00-21swapper/022:19:420
136599510,4rtkit-daemon1364-21rtkit-daemon23:17:491
136599510,4rtkit-daemon1364-21rtkit-daemon20:50:210
136599510,4rtkit-daemon1364-21rtkit-daemon20:50:200
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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