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2026-07-23 - 22:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Thu Jul 23, 2026 12:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4687672259186,19sleep00-21swapper/007:07:340
4686622250184,51sleep10-21swapper/107:06:281
46915199227221,4cyclictest536335-21kworker/u8:209:54:071
106799650,3rtkit-daemon1066-21rtkit-daemon07:45:580
46914699592,37cyclictest603895-21apt-get11:00:130
46914699562,35cyclictest664101-21apt-get12:20:140
46914699552,33cyclictest630114-21apt-get11:35:130
46914699551,37cyclictest626367-21apt-get11:30:120
46914699551,34cyclictest649050-21apt-get12:00:140
106799550,3rtkit-daemon1066-21rtkit-daemon08:04:460
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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