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2026-08-01 - 12:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sat Aug 01, 2026 00:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
34101012260197,48sleep00-21swapper/019:08:180
34101802257194,48sleep10-21swapper/119:09:091
3410371999287,4cyclictest3491139-21kworker/u8:122:16:001
34636952700,12sleep126-21ksoftirqd/121:15:191
35669752600,5sleep10-21swapper/123:34:161
106799480,3rtkit-daemon0-21swapper/121:02:171
35461352470,4sleep10-21swapper/123:05:211
3410371994514,6cyclictest26-21ksoftirqd/122:30:001
34474332440,1chrt3447335-21/usr/sbin/munin20:40:141
3410371994313,5cyclictest26-21ksoftirqd/120:05:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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