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2026-07-30 - 16:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Thu Jul 30, 2026 12:44:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26374142262187,59sleep00-21swapper/007:09:530
26372262262186,60sleep10-21swapper/107:07:511
2637525998479,4cyclictest2695513-21kworker/u8:109:39:550
26450282830,4sleep12645027-21awk07:25:211
28282172610,6sleep013-21ksoftirqd/012:11:530
106799590,4rtkit-daemon1066-21rtkit-daemon08:32:291
106799540,5rtkit-daemon1066-21rtkit-daemon11:45:101
106799480,4rtkit-daemon1066-21rtkit-daemon08:29:311
28163272460,4sleep00-21swapper/011:55:310
28192502440,1chrt2818725-21/usr/sbin/munin12:00:191
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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