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2026-08-09 - 08:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sun Aug 09, 2026 00:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
38545172265191,20sleep00-21swapper/019:06:490
38544492260186,20sleep10-21swapper/119:06:041
385497399109104,4cyclictest3887540-21kworker/u8:120:48:050
3854976999281,9cyclictest3895035-21fwupd20:48:061
108999640,11rtkit-daemon1088-21rtkit-daemon22:14:090
39800642480,4sleep0161rcuc/022:50:170
39115722450,2sleep00-21swapper/021:20:110
108999430,8rtkit-daemon0-21swapper/123:19:331
40124202420,2sleep04012422-21sh23:32:510
3854976994213,5cyclictest26-21ksoftirqd/100:15:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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