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2026-05-31 - 15:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sun May 31, 2026 12:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19016692261187,59sleep10-21swapper/107:09:081
19013432261188,28sleep00-21swapper/007:05:360
19735512560,2sleep01973553-21rm09:39:510
19115052510,4sleep11911508-21needreboot07:30:191
179699510,3rtkit-daemon1795-21rtkit-daemon10:37:561
179699430,4rtkit-daemon1795-21rtkit-daemon08:54:261
20653472410,4sleep10-21swapper/111:45:141
190187199411,7cyclictest13-21ksoftirqd/010:55:010
190187199410,8cyclictest13-21ksoftirqd/008:25:000
179699410,6rtkit-daemon1982529-21users09:50:241
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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