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2026-08-05 - 14:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Wed Aug 05, 2026 00:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
40231642286220,51sleep10-21swapper/119:09:341
40229132264223,27sleep00-21swapper/019:06:510
40687162980,1chrt4068715-21/usr/sbin/munin21:00:241
40713912790,5chrt4071358-21PipeFile:09:34:540
106799530,3rtkit-daemon1066-21rtkit-daemon23:07:010
106799490,4rtkit-daemon1066-21rtkit-daemon23:44:021
106799490,4rtkit-daemon1066-21rtkit-daemon21:39:231
106799490,3rtkit-daemon1066-21rtkit-daemon20:03:100
106799470,3rtkit-daemon1066-21rtkit-daemon20:44:210
106799470,3rtkit-daemon1066-21rtkit-daemon20:21:130
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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