You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-09-04 - 07:16
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Fri Sep 04, 2026 00:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
34194512271211,45sleep00-21swapper/019:09:540
34191042264188,60sleep10-21swapper/119:06:101
341959199183177,4cyclictest3589182-21kworker/u8:200:12:311
136599590,4rtkit-daemon1364-21rtkit-daemon00:04:571
136599520,5rtkit-daemon1364-21rtkit-daemon23:38:171
136599520,3rtkit-daemon0-21swapper/021:47:061
136599500,4rtkit-daemon1364-21rtkit-daemon22:56:080
136599500,4rtkit-daemon1364-21rtkit-daemon20:14:500
341958499499,8cyclictest13-21ksoftirqd/021:15:010
136599490,4rtkit-daemon1364-21rtkit-daemon22:27:491
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional