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2026-04-26 - 06:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sun Apr 26, 2026 00:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26287442325284,27sleep00-21swapper/019:06:540
26287002309267,28sleep10-21swapper/119:06:271
179699670,7rtkit-daemon1795-21rtkit-daemon22:20:151
179699610,5rtkit-daemon1795-21rtkit-daemon23:25:091
262917899602,38cyclictest2805780-21apt-get23:55:131
262917899592,38cyclictest2760243-21apt-get22:55:131
262917899592,36cyclictest2756453-21apt-get22:50:141
262917499582,9cyclictest2801934-21apt-get23:50:140
28139682570,4sleep10-21swapper/100:05:191
179699570,4rtkit-daemon1795-21rtkit-daemon22:00:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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