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2026-08-27 - 03:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Thu Aug 27, 2026 00:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
23719502274215,45sleep10-21swapper/119:05:311
23724042271231,25sleep00-21swapper/019:09:370
237256399230224,4cyclictest2441412-21kworker/u8:421:39:111
136599730,4rtkit-daemon1364-21rtkit-daemon22:45:350
136599610,7rtkit-daemon1364-21rtkit-daemon00:25:141
136599570,4rtkit-daemon1364-21rtkit-daemon23:15:370
25049792560,5sleep12504980-21grep23:05:201
24862262520,1sleep12486225-21sendmail22:40:001
136599510,4rtkit-daemon1364-21rtkit-daemon21:42:531
136599500,4rtkit-daemon1364-21rtkit-daemon22:51:300
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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