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2025-12-17 - 17:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Wed Dec 17, 2025 12:44:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
29952592319277,26sleep00-21swapper/007:07:370
29952302297178,84sleep10-21swapper/107:07:181
179699520,3rtkit-daemon1795-21rtkit-daemon10:30:400
179699510,4rtkit-daemon1795-21rtkit-daemon07:44:470
179699510,4rtkit-daemon1795-21rtkit-daemon07:15:410
179699510,3rtkit-daemon1795-21rtkit-daemon10:57:461
179699500,4rtkit-daemon1795-21rtkit-daemon11:51:541
179699490,4rtkit-daemon1795-21rtkit-daemon08:39:320
179699480,4rtkit-daemon1795-21rtkit-daemon08:12:151
179699480,3rtkit-daemon1795-21rtkit-daemon12:13:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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