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2026-08-13 - 12:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Thu Aug 13, 2026 00:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
28525152272182,27sleep10-21swapper/119:08:141
28523052255187,52sleep00-21swapper/019:05:560
136599780,3rtkit-daemon1364-21rtkit-daemon23:49:551
136599780,3rtkit-daemon1364-21rtkit-daemon00:33:411
28859852640,4chrt0-21swapper/120:30:221
29889312550,5sleep00-21swapper/023:10:130
136599540,4rtkit-daemon1364-21rtkit-daemon00:19:570
136599500,4rtkit-daemon1364-21rtkit-daemon00:22:130
136599490,3rtkit-daemon1364-21rtkit-daemon20:32:510
136599480,3rtkit-daemon1364-21rtkit-daemon22:31:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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