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2026-06-22 - 11:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Mon Jun 22, 2026 00:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13411762264185,29sleep00-21swapper/019:09:460
13411182264188,27sleep10-21swapper/119:09:091
179699680,16rtkit-daemon1795-21rtkit-daemon22:39:260
15201192670,5sleep10-21swapper/100:09:101
179699560,4rtkit-daemon1795-21rtkit-daemon22:05:100
14687452560,4sleep10-21swapper/122:56:411
179699540,4rtkit-daemon1795-21rtkit-daemon21:45:481
179699540,3rtkit-daemon1795-21rtkit-daemon00:15:090
13491702540,3sleep11347915-21/usr/sbin/munin19:25:241
14457512530,4sleep11444792-21/usr/sbin/munin22:25:221
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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