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2026-06-20 - 14:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sat Jun 20, 2026 00:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31613292297262,19sleep00-21swapper/019:05:310
31619462260188,57sleep10-21swapper/119:08:591
179699600,4rtkit-daemon1795-21rtkit-daemon20:15:241
179699520,3rtkit-daemon1795-21rtkit-daemon22:37:371
179699510,4rtkit-daemon1795-21rtkit-daemon19:54:301
179699510,4rtkit-daemon1795-21rtkit-daemon00:21:411
179699500,4rtkit-daemon1795-21rtkit-daemon21:09:550
179699490,4rtkit-daemon1795-21rtkit-daemon21:06:591
179699490,3rtkit-daemon1795-21rtkit-daemon23:27:311
179699480,4rtkit-daemon1795-21rtkit-daemon21:38:201
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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