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2026-09-03 - 23:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Thu Sep 03, 2026 12:44:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17916972308273,19sleep00-21swapper/007:05:570
17918642272214,43sleep10-21swapper/107:07:461
185440521080,3sleep10-21swapper/109:25:241
19751132600,2sleep10-21swapper/112:14:191
1792229995813,33cyclictest1907666-21sh10:38:171
1792229995813,25cyclictest1951052-21sh11:39:191
179222999580,28cyclictest1841826-21unin-run09:10:001
179222999572,35cyclictest1927071-21apt-get11:05:111
179222999571,40cyclictest1879563-21apt-get10:00:121
179222999571,37cyclictest1965314-21apt-get12:00:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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