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2026-06-27 - 15:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sat Jun 27, 2026 12:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26406562309267,27sleep00-21swapper/007:06:230
26406902291189,87sleep10-21swapper/107:06:431
27123022630,1sleep00-21swapper/009:40:150
179699550,4rtkit-daemon1795-21rtkit-daemon07:36:220
27171862540,3chrt0-21swapper/109:45:271
179699540,4rtkit-daemon1795-21rtkit-daemon10:31:100
179699530,4rtkit-daemon1795-21rtkit-daemon11:06:190
179699530,4rtkit-daemon1795-21rtkit-daemon09:45:480
179699500,3rtkit-daemon1795-21rtkit-daemon09:13:070
179699500,3rtkit-daemon1795-21rtkit-daemon08:09:501
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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