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2026-07-10 - 00:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Thu Jul 09, 2026 12:44:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2389512293251,28sleep10-21swapper/107:09:361
2372382273231,28sleep00-21swapper/007:05:110
179699750,3rtkit-daemon0-21swapper/010:55:240
179699680,4rtkit-daemon1795-21rtkit-daemon10:16:510
23911599631,42cyclictest409157-21apt-get11:40:120
23911599622,40cyclictest417037-21apt-get11:50:140
23911599620,25cyclictest397062-21cut11:25:010
179699620,3rtkit-daemon0-21swapper/012:16:040
23911599611,36cyclictest287537-21diskmemload09:26:160
23911599610,26cyclictest389128-21latency_hist11:15:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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