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2026-06-12 - 16:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Fri Jun 12, 2026 12:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
36521322318277,27sleep10-21swapper/107:07:471
36521492264190,59sleep00-21swapper/007:07:580
37404942620,4sleep00-21swapper/010:01:450
37784682560,4sleep03778459-21apt-get10:55:130
36808522560,4sleep00-21swapper/008:20:160
36659672540,3sleep1251rcuc/107:40:251
179699530,4rtkit-daemon1795-21rtkit-daemon07:15:531
179699520,4rtkit-daemon1795-21rtkit-daemon09:42:231
179699520,4rtkit-daemon1795-21rtkit-daemon09:03:361
179699510,4rtkit-daemon1795-21rtkit-daemon08:12:361
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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