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2026-05-27 - 13:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Wed May 27, 2026 00:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
39730432264183,28sleep00-21swapper/019:09:010
39727982262193,54sleep10-21swapper/119:06:231
404079821100,4sleep04040797-21cron21:35:000
40448972580,1sleep04044896-21fschecks_time21:40:160
179699520,4rtkit-daemon1795-21rtkit-daemon22:07:470
179699510,3rtkit-daemon1795-21rtkit-daemon23:15:200
179699500,4rtkit-daemon1795-21rtkit-daemon22:17:560
179699500,3rtkit-daemon1795-21rtkit-daemon21:09:480
179699470,4rtkit-daemon1795-21rtkit-daemon21:12:530
179699450,4rtkit-daemon1795-21rtkit-daemon21:16:511
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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