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2026-06-06 - 04:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sat Jun 06, 2026 00:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
32418222317276,27sleep00-21swapper/019:07:540
32418082316275,27sleep10-21swapper/119:07:441
338698521530,4sleep10-21swapper/123:16:201
33035982820,3sleep03303602-21latency_hist21:25:000
32912252610,4sleep03291228-21pmu-power21:05:220
33550532600,4sleep10-21swapper/122:34:181
324216599563,9cyclictest3439308-40unattended-upgr00:29:480
179699550,14rtkit-daemon3427137-21ssh00:12:581
324216599533,9cyclictest3251097-21apt-get19:30:130
324216599492,9cyclictest3318675-21apt-get21:45:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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