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2025-12-02 - 07:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Tue Dec 02, 2025 00:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
34935972271186,28sleep00-21swapper/019:06:390
34938742255182,58sleep10-21swapper/119:09:371
125899590,6rtkit-daemon251rcuc/120:25:171
35804192570,5sleep00-21swapper/022:00:230
35604242510,4sleep10-21swapper/121:32:541
3494014994610,6cyclictest26-21ksoftirqd/122:45:001
35849102450,5sleep10-21swapper/122:06:551
3494014994515,7cyclictest26-21ksoftirqd/119:25:011
3494014994514,7cyclictest26-21ksoftirqd/119:20:001
3494014994514,5cyclictest26-21ksoftirqd/122:10:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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