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2026-05-19 - 06:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Tue May 19, 2026 00:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
28547732268186,29sleep00-21swapper/019:05:480
28550552255180,27sleep10-21swapper/119:08:491
28719282700,7sleep02871925-21cat19:50:010
30400442650,4sleep03040042-21seq00:10:220
28585862650,4sleep00-21swapper/019:15:210
179699580,4rtkit-daemon1795-21rtkit-daemon20:29:481
179699580,4rtkit-daemon1795-21rtkit-daemon19:33:291
179699560,3rtkit-daemon1795-21rtkit-daemon22:55:071
179699550,4rtkit-daemon1795-21rtkit-daemon00:31:411
179699550,3rtkit-daemon1795-21rtkit-daemon21:44:351
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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