You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-06-15 - 10:28
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Mon Jun 15, 2026 00:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
34876922310276,19sleep00-21swapper/019:08:390
34876132305263,28sleep10-21swapper/119:07:481
179699590,6rtkit-daemon1795-21rtkit-daemon21:10:161
179699570,4rtkit-daemon1795-21rtkit-daemon19:40:111
179699560,3rtkit-daemon1795-21rtkit-daemon22:52:460
36857742530,4chrt0-21swapper/100:35:111
179699510,3rtkit-daemon1795-21rtkit-daemon19:24:131
179699500,4rtkit-daemon1795-21rtkit-daemon22:43:510
179699500,4rtkit-daemon1795-21rtkit-daemon21:09:431
179699500,4rtkit-daemon1795-21rtkit-daemon19:31:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional