You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-11-18 - 10:56
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Tue Nov 18, 2025 00:44:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
6011002269187,28sleep00-21swapper/019:06:320
6011002269187,28sleep00-21swapper/019:06:320
6011922260186,59sleep10-21swapper/119:07:311
6011922260186,59sleep10-21swapper/119:07:311
7851362590,4sleep00-21swapper/000:15:200
125899550,4rtkit-daemon1257-21rtkit-daemon22:52:320
125899540,4rtkit-daemon1257-21rtkit-daemon19:14:040
125899540,4rtkit-daemon1257-21rtkit-daemon00:00:360
125899520,5rtkit-daemon650281-21diskmemload22:22:211
7098152500,1chrt708797-21/usr/sbin/munin22:30:240
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional