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2026-07-19 - 22:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sun Jul 19, 2026 12:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
39468102264190,28sleep10-21swapper/107:06:241
39468442262223,25sleep00-21swapper/007:06:450
40544062590,4sleep1251rcuc/110:21:461
39526262570,4sleep13952629-21needreboot07:20:201
106799510,4rtkit-daemon1066-21rtkit-daemon07:29:130
41492312500,5sleep00-21swapper/012:22:550
40217402500,4sleep04020488-21/usr/sbin/munin09:40:240
106799490,4rtkit-daemon1066-21rtkit-daemon11:12:491
106799480,4rtkit-daemon1066-21rtkit-daemon12:26:311
106799450,4rtkit-daemon1066-21rtkit-daemon10:48:440
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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