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2026-06-29 - 22:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Mon Jun 29, 2026 12:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
8278902294254,26sleep10-21swapper/107:08:531
8279462256182,59sleep00-21swapper/007:09:320
86361521620,1sleep00-21swapper/008:35:000
179699800,3rtkit-daemon1795-21rtkit-daemon10:52:540
179699610,4rtkit-daemon1795-21rtkit-daemon07:33:480
179699590,3rtkit-daemon0-21swapper/109:50:100
8380052550,4sleep1838008-21kernelversion07:30:211
179699520,4rtkit-daemon1795-21rtkit-daemon07:12:170
179699490,3rtkit-daemon1795-21rtkit-daemon11:28:480
179699470,3rtkit-daemon1795-21rtkit-daemon08:36:400
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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