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2026-08-28 - 12:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Fri Aug 28, 2026 00:44:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14221092272215,42sleep10-21swapper/119:07:411
14208272259191,52sleep00-21swapper/019:05:350
15732522880,5sleep10-21swapper/123:33:181
136599600,6rtkit-daemon1364-21rtkit-daemon23:10:120
15818872580,12sleep126-21ksoftirqd/123:45:221
142245799571,34cyclictest1429088-21apt-get19:25:120
142245799562,36cyclictest1532157-21apt-get22:35:140
136599560,3rtkit-daemon1364-21rtkit-daemon21:56:351
142245799552,34cyclictest1553729-21apt-get23:05:140
142245799552,34cyclictest1497106-21apt-get21:45:150
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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