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2026-07-11 - 11:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sat Jul 11, 2026 00:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
10220322262189,27sleep00-21swapper/019:08:330
10219302262185,27sleep10-21swapper/119:07:291
179699710,4rtkit-daemon1795-21rtkit-daemon23:41:221
179699690,3rtkit-daemon1795-21rtkit-daemon19:38:191
179699630,4rtkit-daemon1795-21rtkit-daemon00:32:000
179699620,3rtkit-daemon1795-21rtkit-daemon20:40:550
179699620,3rtkit-daemon1795-21rtkit-daemon19:25:400
179699620,3rtkit-daemon1795-21rtkit-daemon19:17:370
179699610,4rtkit-daemon1795-21rtkit-daemon20:15:040
179699610,4rtkit-daemon1795-21rtkit-daemon00:04:430
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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