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2025-06-29 - 00:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sat Jun 28, 2025 12:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15692222264206,44sleep10-21swapper/107:07:351
15692002258186,58sleep00-21swapper/007:07:220
1569599997772,4cyclictest1586583-21kworker/u8:208:45:381
125899600,4rtkit-daemon1257-21rtkit-daemon12:33:380
16742272540,3sleep00-21swapper/010:23:180
17157562530,3sleep00-21swapper/011:18:070
125899530,4rtkit-daemon1257-21rtkit-daemon11:56:210
125899530,4rtkit-daemon1257-21rtkit-daemon09:28:521
125899530,4rtkit-daemon1257-21rtkit-daemon08:50:451
125899510,4rtkit-daemon1257-21rtkit-daemon11:39:070
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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