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2026-06-16 - 04:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Tue Jun 16, 2026 00:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
25731872321279,27sleep00-21swapper/019:09:380
25732062263187,61sleep10-21swapper/119:09:511
27681452540,4sleep10-21swapper/100:30:131
179699530,4rtkit-daemon1795-21rtkit-daemon20:45:341
179699460,4rtkit-daemon1795-21rtkit-daemon19:53:211
179699460,4rtkit-daemon1795-21rtkit-daemon19:53:211
179699460,3rtkit-daemon1795-21rtkit-daemon22:18:211
179699450,3rtkit-daemon1795-21rtkit-daemon20:59:230
179699440,6rtkit-daemon2578509-21irqstats19:20:170
27254562420,3chrt0-21swapper/023:30:180
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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