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2026-07-19 - 07:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sun Jul 19, 2026 00:44:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
22734802265224,26sleep00-21swapper/019:09:460
22732052263189,59sleep10-21swapper/119:06:501
22911712530,6sleep12290944-21/usr/sbin/munin19:50:161
106799510,4rtkit-daemon1066-21rtkit-daemon23:37:440
106799510,4rtkit-daemon1066-21rtkit-daemon21:46:040
106799510,3rtkit-daemon1066-21rtkit-daemon20:15:061
106799490,4rtkit-daemon1066-21rtkit-daemon21:57:400
106799470,4rtkit-daemon1066-21rtkit-daemon20:54:401
106799460,4rtkit-daemon1066-21rtkit-daemon00:01:361
106799440,3rtkit-daemon1066-21rtkit-daemon20:29:410
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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