You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-04-26 - 19:10
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sun Apr 26, 2026 12:44:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
912112262192,26sleep10-21swapper/107:07:481
911452260183,27sleep00-21swapper/007:07:060
2334512620,2sleep0233452-21sensors11:10:230
179699560,4rtkit-daemon1795-21rtkit-daemon11:35:140
179699530,4rtkit-daemon1795-21rtkit-daemon10:08:580
179699530,4rtkit-daemon1795-21rtkit-daemon10:08:580
179699530,4rtkit-daemon1795-21rtkit-daemon09:20:061
2767952520,4sleep10-21swapper/112:08:221
179699520,3rtkit-daemon1795-21rtkit-daemon12:15:220
179699510,4rtkit-daemon1795-21rtkit-daemon12:13:500
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional