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2025-12-01 - 17:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Mon Dec 01, 2025 12:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
18663682255185,54sleep00-21swapper/007:07:580
18662742238196,27sleep10-21swapper/107:06:581
18666649920011,175cyclictest1956678-21ls10:05:020
1866668991838,160cyclictest1956703-21dpkg10:05:021
1866664991657,143cyclictest1956999-21apt-key10:05:030
1866668991479,126cyclictest1956855-21apt-key10:05:021
125899660,5rtkit-daemon1257-21rtkit-daemon11:30:180
125899490,8rtkit-daemon0-21swapper/109:00:441
20258742450,2sleep12025862-21switchtime11:35:221
19445242440,4sleep00-21swapper/009:48:310
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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