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2025-12-15 - 09:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot4.osadl.org (updated Mon Dec 15, 2025 00:44:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
35662112264187,27sleep10-21swapper/119:07:181
35661242257184,58sleep00-21swapper/019:06:230
36359582500,1chrt3635959-21/usr/sbin/munin22:00:211
179699450,3rtkit-daemon0-21swapper/100:36:441
179699450,3rtkit-daemon0-21swapper/021:00:490
36165792430,3sleep03615708-21/usr/sbin/munin21:10:210
179699430,3rtkit-daemon0-21swapper/100:16:131
179699420,3rtkit-daemon0-21swapper/100:04:581
179699410,3rtkit-daemon0-21swapper/123:45:131
179699410,3rtkit-daemon0-21swapper/122:34:131
179699390,3rtkit-daemon0-21swapper/021:57:400
179699390,3rtkit-daemon0-21swapper/020:27:120
179699350,6rtkit-daemon3665865-21memory23:15:210
179699350,6rtkit-daemon3649863-21load22:35:190
356659999349,7cyclictest26-21ksoftirqd/119:40:101
179699340,5rtkit-daemon3566589-21cyclictest22:58:450
3566599993213,5cyclictest26-21ksoftirqd/123:15:011
3566599993210,5cyclictest26-21ksoftirqd/100:20:241
3566596993211,6cyclictest13-21ksoftirqd/022:30:250
3566596993210,6cyclictest13-21ksoftirqd/021:00:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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