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2025-12-30 - 12:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot4.osadl.org (updated Tue Dec 30, 2025 00:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
74395823700,9sleep00-21swapper/019:05:040
7457392257185,27sleep10-21swapper/119:08:511
8108972530,7sleep00-21swapper/021:30:240
7586142520,4sleep00-21swapper/019:40:140
179699520,4rtkit-daemon161rcuc/000:29:340
9189122510,3sleep1918915-21needreboot23:50:211
745957994517,8cyclictest26-21ksoftirqd/122:05:001
74595499456,3cyclictest141rcu_preempt21:50:010
179699450,4rtkit-daemon1795-21rtkit-daemon00:27:201
179699450,3rtkit-daemon0-21swapper/023:34:470
74595499416,3cyclictest141rcu_preempt22:09:590
179699410,3rtkit-daemon0-21swapper/021:39:370
74595499406,3cyclictest141rcu_preempt21:20:010
74595499405,3cyclictest141rcu_preempt21:45:010
74595499396,3cyclictest141rcu_preempt22:40:010
74595499396,3cyclictest141rcu_preempt22:40:000
179699390,3rtkit-daemon0-21swapper/019:23:240
74595799380,9cyclictest837887-21apt-get22:05:151
74595499384,3cyclictest141rcu_preempt00:20:240
74595499383,2cyclictest141rcu_preempt22:20:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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