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2026-07-18 - 20:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot4.osadl.org (updated Sat Jul 18, 2026 12:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
6112272271229,26sleep00-21swapper/007:05:510
6115692256189,51sleep10-21swapper/107:09:331
8133082880,3sleep00-21swapper/012:20:180
611715996858,8cyclictest674589-21fwupd09:27:110
6666792590,1sleep10-21swapper/109:17:081
6917682500,3sleep00-21swapper/009:48:270
611715995016,7cyclictest13-21ksoftirqd/012:15:010
611715995014,5cyclictest13-21ksoftirqd/010:25:000
7544972480,3sleep0754500-21timerwakeupswit11:05:250
611715994614,5cyclictest13-21ksoftirqd/009:45:000
611715994514,6cyclictest13-21ksoftirqd/011:20:010
611715994513,5cyclictest13-21ksoftirqd/011:30:000
611715994416,6cyclictest13-21ksoftirqd/010:15:000
611715994413,7cyclictest13-21ksoftirqd/008:25:010
611715994412,6cyclictest13-21ksoftirqd/011:40:010
611715994412,5cyclictest13-21ksoftirqd/012:35:010
611715994412,5cyclictest13-21ksoftirqd/008:00:010
106799440,3rtkit-daemon0-21swapper/010:30:230
611715994313,5cyclictest13-21ksoftirqd/012:05:000
611715994312,5cyclictest13-21ksoftirqd/011:05:010
106799430,3rtkit-daemon0-21swapper/011:41:580
7843322420,2sleep10-21swapper/111:44:551
611720994213,9cyclictest26-21ksoftirqd/110:30:231
611715994212,6cyclictest13-21ksoftirqd/012:10:010
611715994212,5cyclictest13-21ksoftirqd/008:05:000
611715994211,5cyclictest13-21ksoftirqd/008:20:000
611715994211,5cyclictest13-21ksoftirqd/007:25:000
61171599418,5cyclictest13-21ksoftirqd/008:55:010
61171599417,5cyclictest13-21ksoftirqd/011:00:000
61171599417,5cyclictest13-21ksoftirqd/008:35:000
611715994111,5cyclictest13-21ksoftirqd/010:20:000
611715994111,5cyclictest13-21ksoftirqd/007:15:010
611715994110,5cyclictest13-21ksoftirqd/007:40:010
611715994110,4cyclictest13-21ksoftirqd/012:35:260
611715994110,4cyclictest13-21ksoftirqd/010:00:010
106799410,3rtkit-daemon0-21swapper/012:17:000
61171599409,5cyclictest13-21ksoftirqd/011:50:010
61171599409,5cyclictest13-21ksoftirqd/011:35:000
61171599408,5cyclictest13-21ksoftirqd/009:55:010
61171599404,3cyclictest141rcu_preempt10:30:000
611715994011,5cyclictest13-21ksoftirqd/012:00:000
106799400,3rtkit-daemon0-21swapper/010:41:030
106799400,3rtkit-daemon0-21swapper/010:35:380
611715993922,5cyclictest668134-21ssh09:19:520
611715993912,5cyclictest13-21ksoftirqd/012:30:000
611715993910,5cyclictest13-21ksoftirqd/008:50:000
106799390,5rtkit-daemon659977-21diskmemload12:08:571
61171599388,4cyclictest13-21ksoftirqd/010:55:000
61171599387,5cyclictest13-21ksoftirqd/010:10:020
61171599387,5cyclictest13-21ksoftirqd/009:10:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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