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2026-08-09 - 06:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot4.osadl.org (updated Sun Aug 09, 2026 00:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
38545172265191,20sleep00-21swapper/019:06:490
38544492260186,20sleep10-21swapper/119:06:041
385497399109104,4cyclictest3887540-21kworker/u8:120:48:050
3854976999281,9cyclictest3895035-21fwupd20:48:061
108999640,11rtkit-daemon1088-21rtkit-daemon22:14:090
39800642480,4sleep0161rcuc/022:50:170
39115722450,2sleep00-21swapper/021:20:110
108999430,8rtkit-daemon0-21swapper/123:19:331
40124202420,2sleep04012422-21sh23:32:510
3854976994213,5cyclictest26-21ksoftirqd/100:15:011
385497699406,2cyclictest141rcu_preempt20:00:011
385497699405,3cyclictest141rcu_preempt21:35:001
108999400,3rtkit-daemon0-21swapper/123:06:181
385497699397,3cyclictest141rcu_preempt20:20:011
3854973993914,5cyclictest13-21ksoftirqd/020:35:000
385497699385,3cyclictest141rcu_preempt21:10:011
3854973993813,5cyclictest13-21ksoftirqd/019:50:010
108999380,4rtkit-daemon820-21snmpd22:55:501
385497699376,3cyclictest141rcu_preempt23:50:221
385497699376,3cyclictest141rcu_preempt19:55:001
385497699376,2cyclictest141rcu_preempt21:55:011
385497699376,2cyclictest141rcu_preempt19:40:001
385497699375,3cyclictest141rcu_preempt00:25:181
108999370,4rtkit-daemon1088-21rtkit-daemon20:11:220
385497699368,3cyclictest141rcu_preempt23:55:181
385497699366,3cyclictest141rcu_preempt00:15:251
385497699365,3cyclictest141rcu_preempt20:30:001
3854976993612,3cyclictest141rcu_preempt22:25:141
3854976993610,9cyclictest26-21ksoftirqd/123:45:001
385497399369,5cyclictest141rcu_preempt21:15:370
385497399369,5cyclictest13-21ksoftirqd/019:45:000
3854973993613,4cyclictest13-21ksoftirqd/019:29:590
385497699358,2cyclictest141rcu_preempt22:45:231
385497699357,3cyclictest141rcu_preempt23:30:021
385497699357,3cyclictest141rcu_preempt22:40:221
385497699356,3cyclictest141rcu_preempt21:40:241
385497399357,2cyclictest141rcu_preempt00:20:210
385497699347,3cyclictest141rcu_preempt22:05:221
385497699346,2cyclictest141rcu_preempt20:10:241
385497699343,3cyclictest141rcu_preempt20:35:021
3854976993410,3cyclictest141rcu_preempt19:15:081
385497399349,2cyclictest141rcu_preempt23:20:230
385497399348,2cyclictest141rcu_preempt22:57:580
385497399348,2cyclictest141rcu_preempt21:41:010
385497699337,8cyclictest26-21ksoftirqd/121:20:241
385497699336,3cyclictest141rcu_preempt22:15:011
385497699336,3cyclictest141rcu_preempt19:20:221
385497699336,10cyclictest26-21ksoftirqd/123:22:041
385497699335,3cyclictest141rcu_preempt22:15:221
385497699335,3cyclictest141rcu_preempt21:45:211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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