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2026-08-20 - 16:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Thu Aug 20, 2026 12:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
214664023420,8sleep10-21swapper/107:05:281
21471832272201,26sleep00-21swapper/007:08:420
23060622800,5sleep02306064-21latency11:45:200
21936232720,4sleep00-21swapper/009:00:230
22407332560,3sleep00-21swapper/010:12:080
136599550,4rtkit-daemon1364-21rtkit-daemon11:52:351
23217322530,4sleep00-21swapper/012:08:020
136599510,3rtkit-daemon1364-21rtkit-daemon07:21:541
136599500,4rtkit-daemon1364-21rtkit-daemon07:41:280
136599480,4rtkit-daemon1364-21rtkit-daemon08:09:511
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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