You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-01 - 08:56
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Thu Jan 01, 2026 00:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31882712266189,27sleep00-21swapper/019:06:450
31868512255180,27sleep10-21swapper/119:05:161
32749072580,4sleep10-21swapper/121:57:321
179699580,4rtkit-daemon1795-21rtkit-daemon20:33:040
179699580,3rtkit-daemon1795-21rtkit-daemon22:03:431
179699560,4rtkit-daemon1795-21rtkit-daemon00:17:440
32961842550,4sleep00-21swapper/022:25:130
179699540,4rtkit-daemon1795-21rtkit-daemon23:58:541
179699540,4rtkit-daemon1795-21rtkit-daemon23:58:541
179699540,3rtkit-daemon1795-21rtkit-daemon20:35:371
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional