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2026-08-17 - 15:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Mon Aug 17, 2026 12:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
8434672262192,55sleep00-21swapper/007:06:440
8435952253190,47sleep10-21swapper/107:08:071
84394499235230,3cyclictest937829-21kworker/u8:310:13:001
843939998776,8cyclictest937867-21fwupd10:13:000
136599610,7rtkit-daemon0-21swapper/012:36:350
136599600,4rtkit-daemon1364-21rtkit-daemon09:23:381
136599600,4rtkit-daemon1364-21rtkit-daemon09:23:381
8478332590,3sleep1847836-21grep07:15:251
136599580,3rtkit-daemon1364-21rtkit-daemon10:30:190
136599570,3rtkit-daemon0-21swapper/012:29:340
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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