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2026-05-23 - 11:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sat May 23, 2026 00:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
33920212267225,28sleep00-21swapper/019:07:020
33922652259187,28sleep10-21swapper/119:09:401
349489321490,2sleep00-21swapper/022:16:190
179699700,4rtkit-daemon1795-21rtkit-daemon21:29:000
179699680,3rtkit-daemon1795-21rtkit-daemon20:00:170
179699550,4rtkit-daemon1795-21rtkit-daemon22:24:330
179699550,4rtkit-daemon1795-21rtkit-daemon22:24:330
34635962530,3chrt0-21swapper/021:39:310
179699530,4rtkit-daemon1795-21rtkit-daemon00:26:121
179699500,4rtkit-daemon1795-21rtkit-daemon23:59:220
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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