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2026-03-26 - 10:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Thu Mar 26, 2026 00:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19041192261188,28sleep00-21swapper/019:08:570
19040452248181,52sleep10-21swapper/119:08:091
20089082690,4chrt0-21swapper/122:24:021
179699590,5rtkit-daemon1795-21rtkit-daemon20:19:240
179699550,4rtkit-daemon1795-21rtkit-daemon20:27:551
20296602540,6sleep10-21swapper/122:53:171
179699520,4rtkit-daemon1795-21rtkit-daemon22:02:000
179699520,4rtkit-daemon1795-21rtkit-daemon21:43:050
179699500,3rtkit-daemon1795-21rtkit-daemon00:01:511
179699490,4rtkit-daemon1795-21rtkit-daemon23:19:571
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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