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2026-07-27 - 17:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Mon Jul 27, 2026 12:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11149132271214,43sleep10-21swapper/107:05:421
11152722267183,19sleep00-21swapper/007:09:330
111547799163158,4cyclictest1150613-21kworker/u8:311:23:480
106799620,2rtkit-daemon1066-21rtkit-daemon12:29:220
13055182590,12sleep126-21ksoftirqd/112:10:351
106799580,4rtkit-daemon1066-21rtkit-daemon07:52:480
11891442540,5sleep00-21swapper/009:41:190
106799540,4rtkit-daemon1066-21rtkit-daemon10:46:051
106799530,22rtkit-daemon1572373-21urbackupserver:11:10:271
106799530,22rtkit-daemon1572373-21urbackupserver:07:25:111
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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