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2026-03-14 - 10:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sat Mar 14, 2026 00:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7679192259183,26sleep00-21swapper/019:09:310
7677392259183,28sleep10-21swapper/119:07:341
179699590,4rtkit-daemon1795-21rtkit-daemon22:03:241
179699590,4rtkit-daemon1795-21rtkit-daemon22:03:241
179699570,3rtkit-daemon0-21swapper/121:29:171
179699570,3rtkit-daemon0-21swapper/119:20:241
8835552560,2sleep00-21swapper/022:40:490
179699560,5rtkit-daemon833690-21chrt21:32:461
179699560,3rtkit-daemon0-21swapper/123:33:491
179699560,3rtkit-daemon0-21swapper/121:39:181
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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