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2025-12-24 - 11:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Wed Dec 24, 2025 00:44:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
22334272263183,27sleep10-21swapper/119:07:311
22335442261184,27sleep00-21swapper/019:08:470
22725542730,5sleep00-21swapper/020:45:180
23576822650,3sleep00-21swapper/000:15:200
22601582590,2sleep12260159-21idleruntime-cro20:15:001
179699580,4rtkit-daemon1795-21rtkit-daemon00:36:140
179699540,4rtkit-daemon1795-21rtkit-daemon23:12:291
179699530,4rtkit-daemon1795-21rtkit-daemon19:21:520
179699520,4rtkit-daemon1795-21rtkit-daemon21:07:110
179699520,4rtkit-daemon1795-21rtkit-daemon20:17:370
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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