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2026-07-21 - 11:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Tue Jul 21, 2026 00:44:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
5209912268186,19sleep00-21swapper/019:08:170
5211502267194,28sleep10-21swapper/119:10:001
5810222730,4sleep013-21ksoftirqd/021:21:570
5594912710,7sleep00-21swapper/020:40:210
106799570,3rtkit-daemon1066-21rtkit-daemon22:14:590
106799550,3rtkit-daemon1066-21rtkit-daemon22:45:370
106799540,4rtkit-daemon1066-21rtkit-daemon23:07:581
106799530,4rtkit-daemon1066-21rtkit-daemon00:38:391
7168712490,4sleep10-21swapper/100:15:131
106799490,4rtkit-daemon1066-21rtkit-daemon20:17:571
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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