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2025-12-11 - 22:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Thu Dec 11, 2025 12:44:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
61163723510,9sleep0611501-21/usr/sbin/munin07:05:160
6130932262191,55sleep10-21swapper/107:08:211
8100682680,4sleep1809288-21/usr/sbin/munin12:25:231
125899630,4rtkit-daemon1257-21rtkit-daemon10:30:390
125899620,4rtkit-daemon1257-21rtkit-daemon09:38:101
125899560,4rtkit-daemon1257-21rtkit-daemon11:36:391
7476462540,3sleep10-21swapper/111:03:481
8160942520,6sleep1816087-21turbostat12:35:011
125899520,4rtkit-daemon1257-21rtkit-daemon12:19:341
125899510,4rtkit-daemon1257-21rtkit-daemon07:49:200
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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