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2026-03-19 - 20:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Thu Mar 19, 2026 12:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15240662265187,28sleep00-21swapper/007:09:210
15239802262187,27sleep10-21swapper/107:08:271
179699840,4rtkit-daemon1795-21rtkit-daemon11:24:470
179699740,4rtkit-daemon1795-21rtkit-daemon07:39:161
179699540,3rtkit-daemon1795-21rtkit-daemon10:54:561
179699530,3rtkit-daemon1795-21rtkit-daemon09:19:311
179699520,4rtkit-daemon1795-21rtkit-daemon09:30:230
179699500,4rtkit-daemon1795-21rtkit-daemon11:03:550
179699500,3rtkit-daemon1795-21rtkit-daemon09:57:570
179699490,4rtkit-daemon1795-21rtkit-daemon07:24:431
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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