You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-05-07 - 23:44
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Thu May 07, 2026 12:44:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
27929332266191,26sleep00-21swapper/007:05:340
27929332266191,26sleep00-21swapper/007:05:330
27929652259184,27sleep10-21swapper/107:05:551
27929652259184,27sleep10-21swapper/107:05:541
286387621340,4sleep10-21swapper/109:35:231
179699610,3rtkit-daemon1795-21rtkit-daemon12:09:491
29962682590,4sleep10-21swapper/112:34:231
179699570,4rtkit-daemon1795-21rtkit-daemon10:15:160
179699570,4rtkit-daemon1795-21rtkit-daemon10:15:160
179699560,4rtkit-daemon1795-21rtkit-daemon07:27:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional