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2025-11-25 - 14:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Tue Nov 25, 2025 00:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19688692284216,52sleep00-21swapper/019:05:250
19698802267189,28sleep10-21swapper/119:08:241
19724682710,1chrt1972469-21munin-node19:15:031
125899650,3rtkit-daemon1257-21rtkit-daemon20:01:141
125899580,4rtkit-daemon1257-21rtkit-daemon21:42:070
21033842550,5chrt0-21swapper/023:05:240
125899550,4rtkit-daemon1257-21rtkit-daemon21:55:261
125899540,4rtkit-daemon1257-21rtkit-daemon23:58:350
125899470,7rtkit-daemon0-21swapper/023:39:420
21001872450,5sleep10-21swapper/123:01:081
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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