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2025-09-18 - 04:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Thu Sep 18, 2025 00:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
36486082257185,57sleep00-21swapper/019:05:520
36488722243202,26sleep10-21swapper/119:08:411
36491129914156,73cyclictest3814125-21/usr/sbin/munin00:00:211
36491099912839,77cyclictest3814110-21which00:00:210
366136821150,4sleep0161rcuc/019:40:000
36778472550,4sleep03677821-21cron20:20:000
36857582540,4sleep1251rcuc/120:39:591
37843412530,2sleep13784342-21ssh23:17:381
125899480,3rtkit-daemon0-21swapper/021:15:480
125899470,3rtkit-daemon0-21swapper/021:55:360
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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