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2026-03-15 - 20:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sun Mar 15, 2026 12:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14570252269188,28sleep00-21swapper/007:09:140
14570022245205,27sleep10-21swapper/107:09:001
179699690,6rtkit-daemon1795-21rtkit-daemon12:05:130
179699570,3rtkit-daemon1795-21rtkit-daemon09:12:030
15279132570,3sleep01527915-21sendmail09:40:000
179699560,3rtkit-daemon0-21swapper/112:33:101
179699560,3rtkit-daemon0-21swapper/107:20:091
179699550,3rtkit-daemon0-21swapper/112:35:151
179699550,3rtkit-daemon0-21swapper/108:23:581
179699540,3rtkit-daemon1795-21rtkit-daemon07:55:281
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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