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2026-05-18 - 02:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sun May 17, 2026 12:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
21212362273214,45sleep00-21swapper/007:08:140
21213302253187,51sleep10-21swapper/107:09:151
179699580,4rtkit-daemon1795-21rtkit-daemon12:33:470
179699550,3rtkit-daemon1795-21rtkit-daemon10:19:010
179699540,4rtkit-daemon1795-21rtkit-daemon10:23:331
212153799532,33cyclictest2193112-21apt-get09:40:141
179699530,4rtkit-daemon1795-21rtkit-daemon12:17:571
179699510,4rtkit-daemon1795-21rtkit-daemon07:12:431
212153799502,6cyclictest2304143-21apt-get12:10:131
212153799502,4cyclictest2274377-21apt-get11:30:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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