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2026-05-27 - 18:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Wed May 27, 2026 12:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14148982263202,46sleep10-21swapper/107:09:191
14147022239197,27sleep00-21swapper/007:07:140
179699700,4rtkit-daemon1795-21rtkit-daemon07:27:580
14559022640,7sleep00-21swapper/008:50:190
179699620,4rtkit-daemon1795-21rtkit-daemon07:27:121
179699590,4rtkit-daemon1795-21rtkit-daemon11:42:290
15346412560,14sleep126-21ksoftirqd/110:45:171
179699520,4rtkit-daemon1795-21rtkit-daemon09:47:090
179699510,4rtkit-daemon1795-21rtkit-daemon08:15:220
179699500,4rtkit-daemon1795-21rtkit-daemon11:26:130
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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