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2025-11-01 - 09:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sat Nov 01, 2025 00:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
5331242270193,28sleep10-21swapper/119:07:111
5333792260186,59sleep00-21swapper/019:09:550
6797062590,2sleep00-21swapper/023:21:390
6843042490,4sleep00-21swapper/023:28:480
125899490,3rtkit-daemon0-21swapper/022:24:000
125899460,3rtkit-daemon0-21swapper/021:46:280
125899440,3rtkit-daemon0-21swapper/021:15:040
6596372430,5sleep10-21swapper/122:54:531
125899430,4rtkit-daemon596694-21ssh21:27:530
7005082400,1sleep1700507-21ntp_offset23:50:241
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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