You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-11-15 - 12:38
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sat Nov 15, 2025 00:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
39629162271195,59sleep00-21swapper/019:08:080
39630092266191,25sleep10-21swapper/119:09:071
125899700,10rtkit-daemon1257-21rtkit-daemon23:24:400
41537812660,5sleep10-21swapper/100:25:511
40288742490,3sleep10-21swapper/121:31:571
40595982450,1sleep14059597-21cpuspeed_turbos22:15:181
3963222994414,5cyclictest13-21ksoftirqd/023:05:010
39843942430,5sleep00-21swapper/020:00:230
3963222994214,6cyclictest13-21ksoftirqd/023:30:010
3963222994213,6cyclictest13-21ksoftirqd/022:25:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional