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2025-12-30 - 21:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Tue Dec 30, 2025 12:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
23965532271212,45sleep10-21swapper/107:07:531
23966372264190,28sleep00-21swapper/007:08:460
25102882570,5chrt0-21swapper/010:32:550
239688799562,6cyclictest2500194-21apt-get10:20:140
239688799562,6cyclictest2500194-21apt-get10:20:130
239688799561,7cyclictest2445722-21diskmemload09:15:230
25726772550,5sleep00-21swapper/011:51:300
239688799542,6cyclictest2516445-21apt-get10:40:150
179699530,4rtkit-daemon1795-21rtkit-daemon10:06:130
179699530,4rtkit-daemon1795-21rtkit-daemon09:46:420
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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