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2025-12-29 - 08:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Mon Dec 29, 2025 00:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
16320322254186,53sleep10-21swapper/119:07:071
16322682251181,55sleep00-21swapper/019:09:370
16486572610,7sleep01648660-21unixbench_singl19:45:270
179699570,4rtkit-daemon1795-21rtkit-daemon20:01:241
179699560,4rtkit-daemon1795-21rtkit-daemon19:15:501
179699540,6rtkit-daemon0-21swapper/023:12:250
17603962540,2sleep01760398-21rm22:51:120
179699530,4rtkit-daemon1795-21rtkit-daemon23:48:011
179699510,4rtkit-daemon1795-21rtkit-daemon21:35:410
179699500,7rtkit-daemon0-21swapper/122:35:401
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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