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2026-01-09 - 10:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Fri Jan 09, 2026 00:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
5156112265186,62sleep00-21swapper/019:09:470
5155852261188,24sleep10-21swapper/119:09:291
179699720,6rtkit-daemon1795-21rtkit-daemon00:12:000
6034612610,3sleep10-21swapper/122:00:161
179699580,4rtkit-daemon1795-21rtkit-daemon21:20:071
6017872520,5sleep00-21swapper/021:57:350
6812422500,1chrt680837-21/usr/sbin/munin23:40:181
179699500,4rtkit-daemon1795-21rtkit-daemon00:26:560
179699490,3rtkit-daemon1795-21rtkit-daemon22:23:481
6727082460,5sleep10-21swapper/123:29:361
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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