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2026-01-07 - 14:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Wed Jan 07, 2026 00:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
224567723750,9sleep10-21swapper/119:05:161
22471922276193,28sleep00-21swapper/019:09:400
232236521490,3sleep1251rcuc/121:43:291
242455621100,3sleep00-21swapper/023:55:030
179699600,4rtkit-daemon1795-21rtkit-daemon23:40:121
179699580,5rtkit-daemon1795-21rtkit-daemon23:17:061
179699540,3rtkit-daemon1795-21rtkit-daemon23:38:251
179699530,4rtkit-daemon1795-21rtkit-daemon20:48:261
179699520,4rtkit-daemon1795-21rtkit-daemon20:06:191
23695412510,4sleep00-21swapper/022:44:260
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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