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2026-04-08 - 22:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Wed Apr 08, 2026 12:44:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
39754082316275,27sleep10-21swapper/107:08:281
39752232270207,47sleep00-21swapper/007:06:290
179699700,4rtkit-daemon1795-21rtkit-daemon09:48:471
179699700,4rtkit-daemon1795-21rtkit-daemon09:22:411
40024582600,1sleep00-21swapper/008:15:140
179699600,4rtkit-daemon1795-21rtkit-daemon09:18:500
179699560,4rtkit-daemon4034084-21ssh09:20:350
179699560,3rtkit-daemon0-21swapper/110:26:320
179699540,4rtkit-daemon1795-21rtkit-daemon12:19:570
179699530,3rtkit-daemon0-21swapper/107:56:310
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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