You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-05-06 - 08:54
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Wed May 06, 2026 00:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20544532325281,28sleep00-21swapper/019:05:110
20558352269210,44sleep10-21swapper/119:06:041
225140021510,4sleep10-21swapper/100:25:151
22298552800,4sleep00-21swapper/023:54:180
179699620,4rtkit-daemon1795-21rtkit-daemon19:32:151
22149962610,5sleep12214997-21ssh23:35:011
21316132600,4chrt2131595-21python321:45:000
179699550,4rtkit-daemon1795-21rtkit-daemon22:53:540
22397832530,4sleep10-21swapper/100:06:271
179699530,4rtkit-daemon1795-21rtkit-daemon22:25:520
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional