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2025-12-09 - 21:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Tue Dec 09, 2025 12:44:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
25326742269206,48sleep00-21swapper/007:05:280
25333732259186,58sleep10-21swapper/107:07:181
2533755991936,173cyclictest2616010-21expr09:55:151
2533751991867,165cyclictest2616320-21if_enp2s009:55:200
2533751991276,107cyclictest2612878-21cut09:50:180
25337519912536,74cyclictest2605542-21needreboot09:40:200
253375599914,73cyclictest2612878-21needreboot09:50:191
27167722670,7sleep1251rcuc/112:09:071
125899610,4rtkit-daemon1257-21rtkit-daemon10:19:191
26479302590,8sleep0161rcuc/010:36:080
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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