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2025-11-28 - 20:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Fri Nov 28, 2025 12:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
6645592275214,46sleep10-21swapper/107:06:291
6646452243200,28sleep00-21swapper/007:07:260
125899600,6rtkit-daemon1257-21rtkit-daemon08:55:141
8510942590,4sleep10-21swapper/112:10:431
8080352560,3sleep00-21swapper/011:14:090
125899530,4rtkit-daemon1257-21rtkit-daemon11:43:280
125899530,4rtkit-daemon1257-21rtkit-daemon10:45:351
8058342520,2chrt804903-21/usr/sbin/munin11:10:211
125899510,4rtkit-daemon1257-21rtkit-daemon09:01:160
125899500,3rtkit-daemon1257-21rtkit-daemon12:32:180
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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