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2026-09-14 - 03:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Mon Sep 14, 2026 00:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26118672322280,27sleep10-21swapper/119:07:101
26119412318276,27sleep00-21swapper/019:07:580
261227499153147,4cyclictest2620380-21kworker/u8:019:56:091
136599670,4rtkit-daemon1364-21rtkit-daemon19:18:091
136599670,4rtkit-daemon1364-21rtkit-daemon19:18:091
136599650,4rtkit-daemon1364-21rtkit-daemon20:53:571
136599640,4rtkit-daemon1364-21rtkit-daemon19:24:271
136599640,3rtkit-daemon1364-21rtkit-daemon21:06:241
136599540,5rtkit-daemon1364-21rtkit-daemon20:55:251
136599510,3rtkit-daemon1364-21rtkit-daemon23:18:111
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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