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2025-12-06 - 18:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sat Dec 06, 2025 12:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
12438152238194,29sleep00-21swapper/007:05:260
12438242236193,28sleep10-21swapper/107:05:271
13021682610,6sleep10-21swapper/109:20:181
124534999612,41cyclictest1363403-21apt-get10:40:161
124534999591,40cyclictest1317002-21apt-get09:40:061
124534999591,39cyclictest1242923-21apt-get07:10:351
124534999581,39cyclictest1261647-21apt-get07:50:071
124534999580,28cyclictest1288703-21grep08:55:241
124534999579,27cyclictest1326456-21grep09:50:241
124534999571,37cyclictest1393388-21apt-get11:20:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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