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2026-04-01 - 15:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Wed Apr 01, 2026 12:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20205642271186,28sleep00-21swapper/007:05:020
20221262260187,58sleep10-21swapper/107:06:471
213856221560,1sleep10-21swapper/110:41:561
179699560,4rtkit-daemon1795-21rtkit-daemon11:31:340
179699560,3rtkit-daemon1795-21rtkit-daemon09:40:221
21205512550,4sleep10-21swapper/110:16:311
179699550,5rtkit-daemon1795-21rtkit-daemon10:19:160
179699540,4rtkit-daemon1795-21rtkit-daemon12:31:410
179699530,4rtkit-daemon1795-21rtkit-daemon10:03:380
179699520,4rtkit-daemon1795-21rtkit-daemon09:56:340
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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