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2026-04-18 - 20:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sat Apr 18, 2026 12:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31330852259217,28sleep00-21swapper/007:09:450
31313462255180,59sleep10-21swapper/107:05:021
179699610,4rtkit-daemon1795-21rtkit-daemon07:15:410
179699530,4rtkit-daemon1795-21rtkit-daemon12:25:190
179699520,4rtkit-daemon1795-21rtkit-daemon09:16:040
179699520,4rtkit-daemon1795-21rtkit-daemon08:45:210
31494212510,1chrt3149420-21/usr/sbin/munin07:45:200
179699510,4rtkit-daemon1795-21rtkit-daemon11:37:520
179699510,4rtkit-daemon1795-21rtkit-daemon10:34:170
179699510,4rtkit-daemon1795-21rtkit-daemon10:29:480
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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