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2026-09-17 - 10:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Thu Sep 17, 2026 00:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
40243932274200,28sleep00-21swapper/019:09:210
40241012263189,59sleep10-21swapper/119:06:131
402458399158151,5cyclictest4127026-21kworker/u8:122:29:241
136599750,4rtkit-daemon1364-21rtkit-daemon21:52:570
136599560,4rtkit-daemon1364-21rtkit-daemon22:53:360
40361762540,4sleep00-21swapper/019:35:230
40836472530,3sleep10-21swapper/121:24:531
136599530,4rtkit-daemon1364-21rtkit-daemon19:18:281
136599520,4rtkit-daemon1364-21rtkit-daemon21:04:090
136599520,4rtkit-daemon1364-21rtkit-daemon20:53:070
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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