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2025-12-12 - 13:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Fri Dec 12, 2025 00:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
207532523500,11sleep00-21swapper/019:05:220
20762712266192,57sleep10-21swapper/119:06:311
21822532480,3sleep00-21swapper/022:28:310
22293822470,4sleep00-21swapper/023:35:200
207670799460,43cyclictest243-21jbd2/mmcblk0p2-00:00:041
125899450,3rtkit-daemon0-21swapper/120:33:101
21314602440,2sleep10-21swapper/121:16:441
125899440,3rtkit-daemon0-21swapper/120:35:461
207670799411,38cyclictest2253887-1kworker/1:1H00:20:331
125899400,3rtkit-daemon0-21swapper/121:49:411
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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