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2026-01-12 - 14:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Mon Jan 12, 2026 00:44:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20516562264190,59sleep00-21swapper/019:07:520
20517502263224,25sleep10-21swapper/119:08:531
21263682740,4sleep10-21swapper/121:44:581
21132382680,2sleep00-21swapper/021:25:320
22411442580,4chrt2240262-21/usr/sbin/munin00:20:220
22261442510,3sleep12226139-21sort00:00:141
179699510,4rtkit-daemon1795-21rtkit-daemon21:20:190
179699510,4rtkit-daemon1795-21rtkit-daemon19:34:390
179699500,4rtkit-daemon1795-21rtkit-daemon23:22:120
179699500,3rtkit-daemon1795-21rtkit-daemon20:02:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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