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2025-12-18 - 14:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Thu Dec 18, 2025 00:44:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3499202254187,53sleep00-21swapper/019:09:230
3497482254212,28sleep10-21swapper/119:07:301
4604752760,5chrt0-21swapper/123:45:171
3841222540,4sleep10-21swapper/120:35:021
179699520,4rtkit-daemon1795-21rtkit-daemon20:44:211
4517032510,4sleep10-21swapper/123:25:011
179699510,4rtkit-daemon1795-21rtkit-daemon23:58:461
179699500,4rtkit-daemon1795-21rtkit-daemon22:21:401
179699500,4rtkit-daemon1795-21rtkit-daemon22:02:390
179699500,4rtkit-daemon1795-21rtkit-daemon20:59:271
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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