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2025-11-27 - 05:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Thu Nov 27, 2025 00:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
339502257184,57sleep00-21swapper/019:07:590
335572257183,20sleep10-21swapper/119:05:301
125899570,5rtkit-daemon1257-21rtkit-daemon21:35:090
125899540,5rtkit-daemon1257-21rtkit-daemon23:30:121
125899540,4rtkit-daemon1257-21rtkit-daemon19:15:120
2095972530,4sleep10-21swapper/100:07:451
125899530,4rtkit-daemon1257-21rtkit-daemon23:00:260
125899530,3rtkit-daemon1257-21rtkit-daemon00:18:041
2216182510,1chrt221617-21/usr/sbin/munin00:25:270
125899500,3rtkit-daemon1257-21rtkit-daemon21:12:501
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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