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2026-05-25 - 16:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Mon May 25, 2026 12:44:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
32360792302182,89sleep00-21swapper/007:06:340
32357652252184,52sleep10-21swapper/107:05:301
33683092620,4sleep03368307-21readlink11:00:010
179699600,4rtkit-daemon1795-21rtkit-daemon09:19:561
33774172540,1chrt3377416-21/usr/sbin/munin11:10:241
32611692540,3sleep00-21swapper/008:10:110
179699540,3rtkit-daemon1795-21rtkit-daemon12:15:211
179699520,5rtkit-daemon1795-21rtkit-daemon10:41:000
179699500,4rtkit-daemon1795-21rtkit-daemon08:27:071
179699490,3rtkit-daemon1795-21rtkit-daemon08:14:301
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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