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2025-12-13 - 20:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Sat Dec 13, 2025 12:44:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30015102264188,27sleep10-21swapper/107:06:421
30017512252188,48sleep00-21swapper/007:09:190
30892872500,1chrt3089286-21/usr/sbin/munin10:45:190
179699440,3rtkit-daemon0-21swapper/110:22:361
179699440,3rtkit-daemon0-21swapper/107:26:451
179699430,3rtkit-daemon0-21swapper/108:01:551
300194599419,3cyclictest141rcu_preempt10:30:000
300194899408,9cyclictest26-21ksoftirqd/107:50:011
300194899407,8cyclictest26-21ksoftirqd/107:40:011
300194599402,11cyclictest3010696-40apt-check07:30:100
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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