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2026-05-22 - 22:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Fri May 22, 2026 12:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17787162265223,28sleep10-21swapper/107:05:481
17789562262220,28sleep00-21swapper/007:08:200
179699730,4rtkit-daemon1795-21rtkit-daemon10:15:121
19093902570,2sleep01909391-21sh10:57:160
179699570,4rtkit-daemon1795-21rtkit-daemon09:56:371
179699550,4rtkit-daemon1795-21rtkit-daemon09:29:001
179699520,4rtkit-daemon1795-21rtkit-daemon10:34:261
179699510,4rtkit-daemon1795-21rtkit-daemon12:22:211
19727322500,6sleep00-21swapper/012:24:300
19279362490,3sleep10-21swapper/111:22:331
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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