You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-12-05 - 15:28
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Fri Dec 05, 2025 12:44:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
22161152268184,19sleep00-21swapper/007:09:150
22157592263180,68sleep10-21swapper/107:05:271
24008112800,1chrt2400812-21/usr/sbin/munin12:35:161
23364402450,4sleep12336438-21grep11:10:181
125899450,3rtkit-daemon0-21swapper/109:40:421
22713992440,5sleep02271128-21/usr/sbin/munin09:45:160
125899440,3rtkit-daemon0-21swapper/111:00:111
22824942430,1sleep00-21swapper/009:59:370
125899430,3rtkit-daemon0-21swapper/107:23:451
125899400,3rtkit-daemon0-21swapper/107:43:531
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional