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2025-12-04 - 18:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot4.osadl.org (updated Thu Dec 04, 2025 12:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
32160392262186,61sleep00-21swapper/007:06:390
32161892260188,27sleep10-21swapper/107:08:151
32407002790,4chrt141rcu_preempt08:10:010
33903392470,2sleep00-21swapper/011:52:240
125899450,3rtkit-daemon0-21swapper/108:53:591
125899450,3rtkit-daemon0-21swapper/108:06:081
3216466994413,20cyclictest26-21ksoftirqd/111:25:001
125899440,3rtkit-daemon0-21swapper/108:44:181
125899440,3rtkit-daemon0-21swapper/108:19:151
125899430,3rtkit-daemon0-21swapper/107:57:361
3216466993924,2cyclictest3280953-21rm09:29:461
3216463993816,7cyclictest13-21ksoftirqd/011:45:030
125899380,5rtkit-daemon1257-21rtkit-daemon11:22:000
125899370,4rtkit-daemon1257-21rtkit-daemon11:25:380
125899350,4rtkit-daemon1257-21rtkit-daemon09:58:321
321646699345,19cyclictest26-21ksoftirqd/111:20:001
3216463993430,2cyclictest131ksoftirqd/009:25:000
3216463993413,6cyclictest13-21ksoftirqd/009:50:170
321646399339,2cyclictest141rcu_preempt12:17:360
3216463993310,4cyclictest13-21ksoftirqd/007:50:240
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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