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2026-07-03 - 10:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot4.osadl.org (updated Fri Jul 03, 2026 00:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
39007532273221,37sleep10-21swapper/119:09:191
39005012261191,55sleep00-21swapper/019:06:360
3900941995617,9cyclictest1-21systemd00:20:021
3900941995614,12cyclictest3970434-21wc21:50:001
3900941995613,13cyclictest4071330-21date00:30:001
179699540,4rtkit-daemon1795-21rtkit-daemon23:43:070
3900941995317,9cyclictest1-21systemd00:25:001
3900941995317,13cyclictest3996380-21latency_hist22:40:001
3900941995317,11cyclictest4074789-21/usr/sbin/munin00:35:011
3900941995315,12cyclictest4036014-21/usr/sbin/munin23:40:231
3900941995313,12cyclictest4039864-21expr23:45:271
179699520,4rtkit-daemon1795-21rtkit-daemon21:24:491
3900941995119,9cyclictest4009934-21/usr/sbin/munin23:05:171
3900941995116,8cyclictest3949632-21diskmemload00:05:241
3900941995114,9cyclictest3913651-21sh19:40:001
3900941995114,11cyclictest3916765-21basename19:45:231
3900941995113,9cyclictest4027142-21latency_hist23:30:011
3900941995113,11cyclictest3999097-21latency_hist22:45:011
179699510,4rtkit-daemon1795-21rtkit-daemon22:43:030
3900941995015,14cyclictest4029100-21rm23:31:031
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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