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2025-12-16 - 23:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot4.osadl.org (updated Tue Dec 16, 2025 12:44:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
40652162264183,28sleep10-21swapper/107:06:501
40651582263186,27sleep00-21swapper/007:06:120
179699590,3rtkit-daemon1795-21rtkit-daemon09:14:561
40880572570,5sleep04087827-21/usr/sbin/munin08:05:160
41796112530,4sleep00-21swapper/011:50:270
179699500,4rtkit-daemon1795-21rtkit-daemon09:01:280
41074282490,3sleep00-21swapper/008:55:160
179699490,4rtkit-daemon1795-21rtkit-daemon11:47:341
179699490,4rtkit-daemon1795-21rtkit-daemon11:18:240
406564799488,8cyclictest4170476-21systemd-run11:30:000
179699480,4rtkit-daemon1795-21rtkit-daemon08:47:400
179699470,4rtkit-daemon1795-21rtkit-daemon12:09:541
179699460,3rtkit-daemon1795-21rtkit-daemon11:56:060
406564799446,11cyclictest4148195-21sh10:35:000
406564799445,11cyclictest4073161-21grep07:25:230
406564799437,9cyclictest1-21systemd07:15:020
406564799434,9cyclictest4099490-21latency_hist08:35:010
406564799429,9cyclictest4093902-21/usr/sbin/munin08:20:150
406564799429,11cyclictest4148379-21taskset10:35:130
406564799427,8cyclictest763-21dbus-daemon12:30:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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