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2025-12-06 - 01:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot4.osadl.org (updated Fri Dec 05, 2025 12:44:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
22161152268184,19sleep00-21swapper/007:09:150
22157592263180,68sleep10-21swapper/107:05:271
24008112800,1chrt2400812-21/usr/sbin/munin12:35:161
23364402450,4sleep12336438-21grep11:10:181
125899450,3rtkit-daemon0-21swapper/109:40:421
22713992440,5sleep02271128-21/usr/sbin/munin09:45:160
125899440,3rtkit-daemon0-21swapper/111:00:111
22824942430,1sleep00-21swapper/009:59:370
125899430,3rtkit-daemon0-21swapper/107:23:451
125899400,3rtkit-daemon0-21swapper/107:43:531
2216392993513,5cyclictest13-21ksoftirqd/008:00:010
2216392993510,7cyclictest13-21ksoftirqd/007:10:110
221639799348,6cyclictest26-21ksoftirqd/112:30:131
221639799340,2cyclictest0-21swapper/111:55:561
2216392993412,5cyclictest13-21ksoftirqd/011:20:000
2216392993315,5cyclictest13-21ksoftirqd/009:40:000
2216392993311,7cyclictest13-21ksoftirqd/009:55:000
2216397993224,6cyclictest2390205-21taskset12:22:071
221639299329,3cyclictest2320646-21latency_hist10:50:000
125899320,3rtkit-daemon0-21swapper/010:25:580
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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