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2026-04-12 - 15:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Sun Apr 12, 2026 12:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7902234167,22sleep30-21swapper/307:05:503
9132228164,21sleep10-21swapper/107:07:251
9592204171,22sleep20-21swapper/207:08:022
10142204170,23sleep00-21swapper/007:08:460
1338221370,7sleep3143199cyclictest12:05:013
276162790,8sleep127615-21turbostat.cron10:20:001
1430996125,6cyclictest33-21ksoftirqd/211:55:232
1430995930,6cyclictest33-21ksoftirqd/210:10:002
1430995930,4cyclictest33-21ksoftirqd/209:40:142
1430995823,5cyclictest33-21ksoftirqd/210:50:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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