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2026-05-12 - 01:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Mon May 11, 2026 12:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591235168,22phc2sys0-21swapper/307:09:193
228882206172,23sleep00-21swapper/007:09:540
225742206172,23sleep20-21swapper/207:05:542
228112204170,22sleep10-21swapper/107:08:581
2814821650,6sleep12319299cyclictest10:40:191
2493021480,3sleep00-21swapper/009:25:230
1307221420,2sleep30-21swapper/310:10:153
278192600,2sleep00-21swapper/010:40:170
147792590,2sleep00-21swapper/012:25:280
139291580,1ptp4l401ktimersoftd/307:40:033
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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