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2026-06-15 - 08:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Mon Jun 15, 2026 00:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
318002230168,50sleep10-21swapper/119:09:191
318012208174,22sleep20-21swapper/219:09:192
139591205172,22phc2sys0-21swapper/319:05:093
315132203170,22sleep00-21swapper/019:05:400
271021390,5sleep13214699cyclictest23:45:181
2955121180,2sleep20-21swapper/222:25:202
32148997434,8cyclictest41-21ksoftirqd/319:45:003
32148997429,4cyclictest41-21ksoftirqd/319:20:003
32148997132,5cyclictest41-21ksoftirqd/323:00:003
32148996832,7cyclictest41-21ksoftirqd/322:10:193
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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