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2026-05-18 - 02:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Sun May 17, 2026 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591216171,33phc2sys0-21swapper/307:09:443
218622206172,22sleep10-21swapper/107:08:081
218342205171,23sleep00-21swapper/007:07:470
218632204171,22sleep20-21swapper/207:08:092
755621410,6sleep12230799cyclictest10:00:221
139291720,0ptp4l401ktimersoftd/312:00:143
2230699643,58cyclictest11179-21grep10:10:000
139291640,1ptp4l401ktimersoftd/311:29:203
173782610,2sleep30-21swapper/308:05:213
284322600,5sleep09-21ksoftirqd/010:45:130
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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