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2025-12-17 - 00:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Tue Dec 16, 2025 12:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139522224189,23sleep20-21swapper/207:07:582
139212212178,23sleep30-21swapper/307:07:343
120172211178,21sleep10-21swapper/107:05:311
138532209175,23sleep00-21swapper/007:06:390
986221180,2sleep20-21swapper/211:30:442
1441299600,34cyclictest19119-21taskset09:35:263
279502580,4sleep127954-21unixbench_singl12:05:581
51182520,5sleep35120-21fschecks_count11:20:473
14410995143,5cyclictest15338-21cron08:20:001
44752470,1sleep20-21swapper/212:25:522
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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