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2026-01-05 - 09:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Mon Jan 05, 2026 00:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591238169,23phc2sys0-21swapper/319:06:573
199672206170,24sleep00-21swapper/019:08:070
198262205171,23sleep10-21swapper/119:06:191
198122203170,22sleep20-21swapper/219:06:082
185121870,6sleep22040699cyclictest23:00:162
2286121710,6sleep32040799cyclictest19:15:153
1966021440,4sleep12040599cyclictest21:20:291
1181521440,1sleep30-21swapper/320:00:003
142621320,3sleep12040599cyclictest00:05:251
2011328162,10sleep10-21swapper/119:10:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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