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2026-04-04 - 15:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Sat Apr 04, 2026 12:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
204252229167,50sleep10-21swapper/107:08:361
139591209175,22phc2sys0-21swapper/307:05:503
204982205172,22sleep20-21swapper/207:09:322
204812204171,22sleep00-21swapper/007:09:180
1149821560,4sleep32083899cyclictest12:25:203
1149821560,4sleep32083899cyclictest12:25:203
20838997231,9cyclictest41-21ksoftirqd/308:40:003
20838996833,8cyclictest41-21ksoftirqd/310:50:003
20838996635,9cyclictest41-21ksoftirqd/307:55:003
20838996635,9cyclictest41-21ksoftirqd/307:55:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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