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2026-01-01 - 14:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Wed Dec 31, 2025 12:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591235168,22phc2sys0-21swapper/307:06:423
122172205172,22sleep20-21swapper/207:06:362
122982203170,22sleep00-21swapper/007:07:390
121742203169,23sleep10-21swapper/107:06:031
139591147121,14phc2sys0-21swapper/307:10:013
2739721370,6sleep11277999cyclictest07:40:131
2739721370,6sleep11277999cyclictest07:40:131
2090321310,2sleep11277999cyclictest11:55:151
165592620,4sleep116560-21unixbench_multi09:30:291
282142610,6sleep01277899cyclictest08:50:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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