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2026-01-04 - 02:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Sat Jan 03, 2026 12:45:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
236102231167,21sleep10-21swapper/107:08:221
236022208173,23sleep00-21swapper/007:08:160
236462205171,23sleep20-21swapper/207:08:502
139591205171,22phc2sys0-21swapper/307:05:553
2354721780,6sleep02403499cyclictest08:15:190
681721390,5sleep22403699cyclictest09:55:182
2403599564,50cyclictest0-21swapper/108:55:251
139291540,0ptp4l401ktimersoftd/309:08:133
207682530,2sleep00-21swapper/011:30:190
14182520,4sleep11423-21irqrtprio10:50:211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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