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2026-03-30 - 05:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Mon Mar 30, 2026 00:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
217762235208,18sleep10-21swapper/119:09:581
217612206173,22sleep20-21swapper/219:09:482
214312205171,22sleep30-21swapper/319:05:383
217312203170,22sleep00-21swapper/019:09:260
2704621750,6sleep12207199cyclictest19:20:121
22073996229,3cyclictest41-21ksoftirqd/319:55:193
22073996227,8cyclictest41-21ksoftirqd/300:30:203
22073996224,4cyclictest41-21ksoftirqd/323:46:153
22073996024,4cyclictest41-21ksoftirqd/321:25:293
22073996022,4cyclictest41-21ksoftirqd/321:55:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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