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2026-08-17 - 22:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Mon Aug 17, 2026 12:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
247952245199,35sleep30-21swapper/307:08:593
247952245199,35sleep30-21swapper/307:08:583
245822234168,22sleep20-21swapper/207:06:122
245822234168,22sleep20-21swapper/207:06:122
246422231202,19sleep00-21swapper/007:06:590
246422231202,19sleep00-21swapper/007:06:590
248802229167,50sleep10-21swapper/107:09:571
248802229167,50sleep10-21swapper/107:09:571
2860221390,3sleep02517699cyclictest07:15:210
2440821270,2sleep20-21swapper/210:30:162
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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