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2026-04-25 - 04:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Sat Apr 25, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
312302233168,22sleep00-21swapper/019:08:160
312302233168,22sleep00-21swapper/019:08:160
139591222193,19phc2sys0-21swapper/319:08:593
139591222193,19phc2sys0-21swapper/319:08:593
310442205172,21sleep10-21swapper/119:05:571
310442205172,21sleep10-21swapper/119:05:561
312592204170,23sleep20-21swapper/219:08:382
312592204170,23sleep20-21swapper/219:08:382
859421600,6sleep33166099cyclictest22:50:153
31660997131,5cyclictest41-21ksoftirqd/321:10:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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