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2026-04-18 - 02:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Fri Apr 17, 2026 12:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7622208175,22sleep10-21swapper/107:07:061
7952206172,23sleep20-21swapper/207:07:302
139591206172,22phc2sys0-21swapper/307:06:033
6432204170,23sleep00-21swapper/007:05:350
1395918363,11phc2sys0-21swapper/307:10:013
1288996831,10cyclictest25-21ksoftirqd/109:35:001
19982630,3sleep10-21swapper/107:10:181
1288995920,4cyclictest25-21ksoftirqd/111:20:131
1288995422,4cyclictest25-21ksoftirqd/110:40:151
171692530,2sleep217170-21ptp4l07:40:232
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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