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2026-05-15 - 01:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Thu May 14, 2026 12:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
289742212169,31sleep10-21swapper/107:05:051
139591205170,23phc2sys0-21swapper/307:08:493
309772204170,22sleep20-21swapper/207:08:182
308202203170,22sleep00-21swapper/007:06:150
1261121370,3sleep33157499cyclictest08:45:153
77452670,6sleep23157399cyclictest07:25:242
31573996322,10cyclictest33-21ksoftirqd/212:30:162
31572996128,8cyclictest25-21ksoftirqd/110:15:151
31572996028,7cyclictest25-21ksoftirqd/108:35:001
31572996027,8cyclictest25-21ksoftirqd/110:10:171
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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