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2026-03-11 - 18:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Wed Mar 11, 2026 12:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591234168,22phc2sys0-21swapper/307:07:093
112562229165,23sleep10-21swapper/107:09:281
110832207174,22sleep20-21swapper/207:07:202
111352201168,22sleep00-21swapper/007:07:550
2252921600,5sleep31159199cyclictest07:30:233
139291540,1ptp4l401ktimersoftd/312:15:193
193512530,2sleep00-21swapper/007:25:190
139291470,1ptp4l401ktimersoftd/307:35:593
139291420,1ptp4l401ktimersoftd/311:15:543
139291420,0ptp4l401ktimersoftd/310:33:353
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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