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2026-11-03 - 10:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Tue Nov 03, 2026 00:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1198622480,4sleep3391rcuc/319:05:193
130122206172,22sleep00-21swapper/019:07:170
129382206173,21sleep10-21swapper/119:06:261
128912203170,22sleep20-21swapper/219:05:502
13516996327,11cyclictest41-21ksoftirqd/321:05:273
278482610,6sleep21351599cyclictest19:40:132
13516996027,5cyclictest41-21ksoftirqd/321:55:293
245342560,2sleep20-21swapper/219:30:252
13516995528,9cyclictest41-21ksoftirqd/319:40:133
13516995426,9cyclictest41-21ksoftirqd/323:40:133
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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