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2026-05-08 - 19:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Fri May 08, 2026 12:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591243175,22phc2sys0-21swapper/307:07:553
154172233169,53sleep20-21swapper/207:07:572
154882208175,22sleep10-21swapper/107:08:521
134552202168,22sleep00-21swapper/007:05:090
404321760,7sleep11587699cyclictest07:50:231
1587799660,32cyclictest28377-21latency_hist11:00:002
15875996230,4cyclictest9-21ksoftirqd/007:55:130
15875995928,4cyclictest9-21ksoftirqd/010:00:250
227972570,3sleep122790-21latency_hist07:25:001
1587799576,19cyclictest6526-21taskset10:11:412
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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