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2025-11-19 - 08:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Wed Nov 19, 2025 00:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3135222890,54sleep20-21swapper/219:07:072
1158622250,3sleep011588-21grep19:07:500
1168822100,12sleep30-21swapper/319:08:523
3013722070,8sleep10-21swapper/119:08:061
852121130,4sleep18540-21sh19:10:321
1642499697,60cyclictest8087-21kworker/1:021:53:051
16424996915,52cyclictest10041-21kworker/1:220:55:251
216632580,4sleep021664-21sh19:10:070
147302520,2sleep10-21swapper/123:05:161
129752520,1sleep00-21swapper/020:45:250
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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