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2025-12-13 - 18:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Sat Dec 13, 2025 12:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
256042235174,49sleep20-21swapper/207:07:092
139591233171,51phc2sys0-21swapper/307:07:503
258062218185,22sleep00-21swapper/007:09:040
258122212180,21sleep10-21swapper/107:09:091
2858121610,6sleep32618299cyclictest07:15:123
396921520,6sleep12618099cyclictest12:00:001
1038221480,5sleep22618199cyclictest08:50:222
2749421280,2sleep00-21swapper/008:20:160
130672660,3sleep22618199cyclictest10:03:122
17942580,4sleep31799-21irqrtprio07:25:233
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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