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2026-08-10 - 21:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Mon Aug 10, 2026 12:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591232170,21phc2sys0-21swapper/307:06:013
139591232170,21phc2sys0-21swapper/307:06:013
114652207173,22sleep00-21swapper/007:06:550
114652207173,22sleep00-21swapper/007:06:550
113582206173,22sleep10-21swapper/107:05:301
113582206173,22sleep10-21swapper/107:05:301
113792203168,23sleep20-21swapper/207:05:482
113792203168,23sleep20-21swapper/207:05:482
1171127255,7sleep10-21swapper/107:10:001
1200499679,16cyclictest15625-21/usr/sbin/munin07:15:221
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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