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2025-12-22 - 02:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Sun Dec 21, 2025 12:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
36112229163,23sleep10-21swapper/107:08:061
139591229163,22phc2sys0-21swapper/307:06:503
34242204170,22sleep00-21swapper/007:05:400
37252202169,22sleep20-21swapper/207:09:322
1709521690,7sleep3406199cyclictest07:35:203
142632570,2sleep00-21swapper/009:45:180
406099504,6cyclictest33-21ksoftirqd/209:40:242
406099495,6cyclictest33-21ksoftirqd/207:20:182
406099485,6cyclictest33-21ksoftirqd/212:15:252
406099483,5cyclictest33-21ksoftirqd/212:10:222
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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