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2026-04-10 - 00:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Thu Apr 09, 2026 12:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
226522220171,37sleep30-21swapper/307:08:593
225322207172,23sleep20-21swapper/207:07:242
227062206171,23sleep00-21swapper/007:09:390
224902203171,21sleep10-21swapper/107:06:521
1868921620,7sleep22318399cyclictest09:15:132
860421410,6sleep22318399cyclictest12:15:212
224052660,4sleep222404-21grep09:20:272
139291650,1ptp4l401ktimersoftd/308:39:333
139291620,1ptp4l401ktimersoftd/312:08:233
162172600,2sleep30-21swapper/310:15:253
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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