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2026-04-24 - 16:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Fri Apr 24, 2026 12:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1311823170,5sleep213116-21grep07:05:152
139591207174,22phc2sys0-21swapper/307:07:163
146852206171,23sleep10-21swapper/107:08:501
144342202169,22sleep00-21swapper/007:05:340
2801921340,7sleep11507599cyclictest08:45:001
1507699720,3cyclictest12590-21sed11:35:012
77582600,2sleep00-21swapper/008:00:220
279902580,2sleep00-21swapper/012:05:220
90512550,2sleep00-21swapper/009:10:230
1507699490,3cyclictest31524-21taskset07:44:552
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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