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2026-06-08 - 06:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Mon Jun 08, 2026 00:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591232165,22phc2sys0-21swapper/319:05:413
139591232165,22phc2sys0-21swapper/319:05:413
229332207174,22sleep20-21swapper/219:05:302
229332207174,22sleep20-21swapper/219:05:302
230272205171,22sleep00-21swapper/019:06:370
230272205171,22sleep00-21swapper/019:06:370
232782204170,23sleep10-21swapper/119:09:501
232782204170,23sleep10-21swapper/119:09:501
262332560,4sleep226237-21phc2sys20:20:232
139291550,1ptp4l401ktimersoftd/319:17:583
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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