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2026-04-14 - 21:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Tue Apr 14, 2026 12:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591238171,23phc2sys0-21swapper/307:09:273
69432205171,22sleep10-21swapper/107:06:061
70262204170,23sleep00-21swapper/007:07:100
51272203170,22sleep20-21swapper/207:05:112
7544996713,19cyclictest12143-21date09:34:593
272812580,7sleep2754399cyclictest07:50:162
29702550,2sleep20-21swapper/208:05:242
7543995333,17cyclictest33-21ksoftirqd/211:20:002
7543994611,21cyclictest23483-21smartctl08:50:162
754399451,3cyclictest217-21systemd-journal07:49:222
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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