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2026-07-06 - 18:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Mon Jul 06, 2026 12:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
172902234168,22sleep10-21swapper/107:07:111
139591214169,33phc2sys0-21swapper/307:08:383
172892206174,21sleep00-21swapper/007:07:090
171832204171,22sleep20-21swapper/207:05:462
139591173123,41phc2sys0-21swapper/307:10:013
1077421610,6sleep21781499cyclictest10:15:172
139291900,1ptp4l31268-21ls07:35:263
139291900,1ptp4l31268-21ls07:35:263
197342740,1sleep20-21swapper/210:35:152
17812996925,5cyclictest9-21ksoftirqd/010:55:190
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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