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2026-03-22 - 20:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Sun Mar 22, 2026 12:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
323462237182,46sleep00-21swapper/007:09:110
139591214170,32phc2sys0-21swapper/307:07:553
321692207179,18sleep10-21swapper/107:06:581
320652205170,23sleep20-21swapper/207:05:392
2652121280,1sleep30-21swapper/309:10:203
241432610,1sleep20-21swapper/212:30:012
80252590,2sleep20-21swapper/211:55:142
259202590,5sleep225923-21fschecks_count09:10:152
38042450,1sleep20-21swapper/209:30:202
32706994526,16cyclictest41-21ksoftirqd/308:57:373
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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