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2026-04-30 - 19:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Thu Apr 30, 2026 12:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591206173,22phc2sys0-21swapper/307:06:473
177212205170,23sleep20-21swapper/207:05:482
176772203169,23sleep00-21swapper/007:05:140
177502202168,22sleep10-21swapper/107:06:131
1395918362,11phc2sys0-21swapper/307:10:013
1834699752,8cyclictest33-21ksoftirqd/210:08:192
18346996934,5cyclictest33-21ksoftirqd/209:55:002
18346996930,7cyclictest33-21ksoftirqd/209:05:012
139291670,1ptp4l401ktimersoftd/310:45:233
18346996630,6cyclictest33-21ksoftirqd/211:10:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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