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2026-05-11 - 01:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Sun May 10, 2026 12:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591228199,19phc2sys0-21swapper/307:05:593
234952207173,22sleep10-21swapper/107:07:011
233932203167,25sleep20-21swapper/207:05:422
237092202169,22sleep00-21swapper/007:09:420
45682700,2sleep20-21swapper/207:35:182
24025996929,4cyclictest9-21ksoftirqd/008:45:010
24025996432,5cyclictest9-21ksoftirqd/010:35:000
24025996430,4cyclictest9-21ksoftirqd/011:20:210
24025996232,4cyclictest9-21ksoftirqd/007:25:000
24025996227,4cyclictest9-21ksoftirqd/011:50:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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