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2026-04-17 - 01:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Thu Apr 16, 2026 12:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
238272208174,23sleep20-21swapper/207:09:502
139591208174,22phc2sys0-21swapper/307:06:343
235482207174,22sleep10-21swapper/107:06:161
236022203172,20sleep00-21swapper/007:06:580
669321540,2sleep20-21swapper/209:55:142
231432640,1sleep10-21swapper/108:15:111
215542590,4sleep30-21swapper/309:20:003
295482500,4sleep329549-21fschecks_time09:35:173
295482500,4sleep329549-21fschecks_time09:35:173
2413899472,42cyclictest27573-21apt10:40:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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