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2026-01-10 - 04:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Sat Jan 10, 2026 00:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
190312237171,22sleep10-21swapper/119:05:511
139591237169,22phc2sys0-21swapper/319:05:573
190682206172,22sleep00-21swapper/019:06:180
193212205170,23sleep20-21swapper/219:09:382
356121590,6sleep31964799cyclictest00:10:213
820921540,7sleep31964799cyclictest00:20:193
2994121380,6sleep21964699cyclictest20:35:252
1935329070,11sleep10-21swapper/119:10:011
19644997119,4cyclictest9-21ksoftirqd/000:30:000
19646996630,8cyclictest33-21ksoftirqd/219:40:172
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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