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2026-05-09 - 23:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Sat May 09, 2026 12:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591209175,22phc2sys0-21swapper/307:09:463
306012206173,22sleep20-21swapper/207:06:292
305332205172,21sleep10-21swapper/107:05:361
306042202167,23sleep00-21swapper/007:06:310
883821370,5sleep33117499cyclictest10:50:183
3117399709,58cyclictest13980-21kworker/2:008:00:252
3117399664,59cyclictest13980-21kworker/2:009:10:252
3117199656,56cyclictest16180-21cut10:00:110
3117399618,9cyclictest18007-21wc12:15:252
3117399587,14cyclictest7493-21if_enp4s011:55:172
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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