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2025-12-23 - 10:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Tue Dec 23, 2025 00:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591209175,23phc2sys0-21swapper/319:05:103
259482208175,22sleep20-21swapper/219:05:332
262312204171,22sleep00-21swapper/019:09:090
261052202170,21sleep10-21swapper/119:07:291
139291670,1ptp4l401ktimersoftd/321:40:273
139291660,1ptp4l401ktimersoftd/300:07:333
176612640,2sleep017662-21ps23:20:210
139291560,1ptp4l401ktimersoftd/319:38:043
139291510,0ptp4l401ktimersoftd/321:57:213
139291500,0ptp4l401ktimersoftd/322:00:183
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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