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2025-11-09 - 05:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Sun Nov 09, 2025 00:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
136691233169,52phc2sys0-21swapper/319:09:463
174502229167,50sleep00-21swapper/019:08:200
175092208174,23sleep20-21swapper/219:09:072
173862204170,23sleep10-21swapper/119:07:331
2920321600,4sleep31787499cyclictest21:45:283
1730921500,4sleep11787299cyclictest20:15:191
73432630,4sleep10-21swapper/123:15:231
296042590,4sleep1226-21systemd-journal19:35:011
99732580,3sleep00-21swapper/022:15:170
17874995232,17cyclictest41-21ksoftirqd/300:10:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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