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2026-03-19 - 07:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Thu Mar 19, 2026 00:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
38512237170,23sleep20-21swapper/219:07:012
40582229168,49sleep10-21swapper/119:09:421
139591206172,22phc2sys0-21swapper/319:09:133
37622204171,22sleep00-21swapper/019:05:510
2782421670,5sleep1438499cyclictest00:25:251
408528262,11sleep00-21swapper/019:10:010
438599790,77cyclictest17361-21kworker/2:221:35:252
4384996233,3cyclictest25-21ksoftirqd/100:20:211
4384996129,7cyclictest25-21ksoftirqd/120:20:001
4384996033,7cyclictest25-21ksoftirqd/123:25:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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