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2026-07-20 - 20:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Mon Jul 20, 2026 12:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591237170,22phc2sys0-21swapper/307:09:513
110262232168,52sleep20-21swapper/207:09:402
107072204170,22sleep10-21swapper/107:05:331
107412203170,22sleep00-21swapper/007:06:000
1537221430,2sleep11135099cyclictest07:15:291
92192740,1sleep1231rcuc/108:10:281
1134999670,3cyclictest24390-21/usr/sbin/munin07:35:210
139291550,1ptp4l401ktimersoftd/310:48:253
11349995512,18cyclictest19809-21needreboot09:40:230
248212540,1sleep00-21swapper/011:00:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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