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2026-04-08 - 21:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Wed Apr 08, 2026 12:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
247832207172,23sleep20-21swapper/207:08:012
249242206171,23sleep30-21swapper/307:09:513
246632205172,22sleep00-21swapper/007:06:350
227992202169,21sleep10-21swapper/107:05:031
139591160117,33phc2sys0-21swapper/307:10:013
1815621360,6sleep02522899cyclictest10:15:250
25230997427,5cyclictest33-21ksoftirqd/207:15:242
25230997332,11cyclictest33-21ksoftirqd/209:00:012
25230997031,9cyclictest33-21ksoftirqd/210:39:592
25230996931,7cyclictest33-21ksoftirqd/208:00:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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