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2026-03-15 - 02:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Sat Mar 14, 2026 12:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591229168,50phc2sys0-21swapper/307:09:303
293812206173,22sleep20-21swapper/207:06:422
293802204172,22sleep10-21swapper/107:06:421
295192203169,23sleep00-21swapper/007:08:290
46321630,7sleep22993199cyclictest07:15:182
1392911020,1ptp4l29121-21gdbus08:15:013
29929997036,8cyclictest9-21ksoftirqd/007:55:140
29929996832,6cyclictest9-21ksoftirqd/008:40:140
29929996830,4cyclictest9-21ksoftirqd/012:00:000
29929996728,6cyclictest9-21ksoftirqd/008:40:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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