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2026-04-11 - 14:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Sat Apr 11, 2026 00:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591234167,22phc2sys0-21swapper/319:07:453
309552209177,22sleep20-21swapper/219:06:422
310012208174,23sleep00-21swapper/019:07:130
309022205172,22sleep10-21swapper/119:06:021
139291540,1ptp4l401ktimersoftd/321:33:413
139291540,0ptp4l401ktimersoftd/323:31:313
244842520,1sleep20-21swapper/222:15:252
229462520,2sleep20-21swapper/223:20:202
31509994539,4cyclictest14391-21sh20:50:003
139291430,0ptp4l401ktimersoftd/321:57:263
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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