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2026-09-15 - 00:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Mon Sep 14, 2026 12:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
106222236169,23sleep10-21swapper/107:07:221
139591208174,22phc2sys0-21swapper/307:06:263
86932205171,22sleep20-21swapper/207:05:032
86982204170,22sleep00-21swapper/007:05:050
42321510,6sleep11112399cyclictest11:15:171
176712700,2sleep10-21swapper/108:30:141
11125996728,10cyclictest41-21ksoftirqd/308:40:133
11125996533,8cyclictest41-21ksoftirqd/311:00:013
11125996526,7cyclictest41-21ksoftirqd/308:40:013
11125996332,3cyclictest41-21ksoftirqd/311:55:253
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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