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2026-05-25 - 04:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Mon May 25, 2026 00:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591244198,35phc2sys0-21swapper/319:09:593
306482234169,21sleep20-21swapper/219:08:372
304422231167,21sleep00-21swapper/019:06:020
286302207172,23sleep10-21swapper/119:05:101
1556221630,7sleep03104899cyclictest19:45:010
3105099770,75cyclictest16807-21kworker/2:119:45:252
100342640,2sleep30-21swapper/322:55:153
31049996324,7cyclictest25-21ksoftirqd/123:50:161
31049996324,7cyclictest25-21ksoftirqd/123:50:151
31049996222,4cyclictest25-21ksoftirqd/123:55:191
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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