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2026-04-26 - 17:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Sun Apr 26, 2026 12:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
174082243198,34sleep10-21swapper/107:07:591
172542227197,20sleep20-21swapper/207:06:002
139591209175,22phc2sys0-21swapper/307:08:053
174752204170,23sleep00-21swapper/007:08:500
139591163122,14phc2sys0-21swapper/307:10:003
17866996720,4cyclictest25-21ksoftirqd/109:00:001
17868996030,9cyclictest41-21ksoftirqd/308:55:143
17866996015,7cyclictest25-21ksoftirqd/111:15:011
17868995928,8cyclictest41-21ksoftirqd/309:05:013
1786899543,6cyclictest27321-21sed09:45:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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