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2026-03-26 - 01:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Wed Mar 25, 2026 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
280232235168,22sleep00-21swapper/007:05:450
283112223164,47sleep10-21swapper/107:09:241
281712206172,23sleep30-21swapper/307:07:413
281282205172,22sleep20-21swapper/207:07:082
1397821390,5sleep32865399cyclictest07:45:203
283592133109,13sleep10-21swapper/107:10:001
1395918762,16phc2sys0-21swapper/307:10:003
139291760,1ptp4l391rcuc/308:30:223
28653997031,9cyclictest41-21ksoftirqd/309:10:003
28653996925,4cyclictest41-21ksoftirqd/312:15:253
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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