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2025-12-26 - 19:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Fri Dec 26, 2025 12:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
303142207174,22sleep30-21swapper/307:08:003
302502207174,22sleep10-21swapper/107:07:091
303502206171,23sleep20-21swapper/207:08:272
301872203170,22sleep00-21swapper/007:06:200
569721450,7sleep33077099cyclictest08:30:233
3076799771,26cyclictest15112-21basename07:45:000
3076799670,24cyclictest14818-21cut11:05:160
3076799661,23cyclictest18992-21cat10:05:260
3076799660,23cyclictest20042-21sed12:25:010
3076799660,23cyclictest16603-21processes07:45:220
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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