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2026-04-13 - 16:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Mon Apr 13, 2026 12:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591220177,35phc2sys0-21swapper/307:07:043
82492203170,22sleep20-21swapper/207:09:322
80042203170,22sleep00-21swapper/007:06:210
79432203170,22sleep10-21swapper/107:05:331
858699654,16cyclictest21641-21irqrtprio12:05:162
858699613,11cyclictest6270-21missed_timers08:10:212
829326139,14sleep20-21swapper/207:10:012
858699585,18cyclictest26082-21df_abs12:15:142
858699585,10cyclictest30145-21latency_hist07:55:002
858699563,17cyclictest15936-21egrep09:40:122
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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