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2026-08-03 - 21:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Mon Aug 03, 2026 12:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
75092234168,22sleep30-21swapper/307:09:383
73052209174,23sleep00-21swapper/007:06:580
74752204169,23sleep10-21swapper/107:09:111
72452203170,22sleep20-21swapper/207:06:122
139291790,1ptp4l391rcuc/307:55:163
7895997039,2cyclictest33-21ksoftirqd/209:40:272
139291660,1ptp4l401ktimersoftd/310:16:443
7895996528,5cyclictest33-21ksoftirqd/210:30:002
7895996434,7cyclictest33-21ksoftirqd/208:00:012
202302630,2sleep20-21swapper/208:40:192
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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