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2026-04-24 - 03:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Fri Apr 24, 2026 00:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
142272230200,20sleep00-21swapper/019:05:580
139591208175,22phc2sys0-21swapper/319:05:043
143712205172,22sleep20-21swapper/219:07:452
144822204171,23sleep10-21swapper/119:09:141
1395916842,18phc2sys0-21swapper/319:10:013
14837996532,4cyclictest25-21ksoftirqd/123:35:001
14837996530,4cyclictest25-21ksoftirqd/120:55:141
14837996430,8cyclictest25-21ksoftirqd/120:45:001
14837996331,4cyclictest25-21ksoftirqd/100:10:281
14837996330,5cyclictest25-21ksoftirqd/121:15:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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