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2025-09-16 - 14:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Tue Sep 16, 2025 00:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
137391235168,23phc2sys0-21swapper/319:05:333
45722208174,23sleep00-21swapper/019:07:430
46192206172,22sleep10-21swapper/119:08:161
46052204173,19sleep20-21swapper/219:08:052
2098821680,5sleep1521499cyclictest23:05:011
2774121610,5sleep1521499cyclictest00:25:161
502121570,1sleep10-21swapper/120:15:191
1373918262,11phc2sys0-21swapper/319:10:013
521799647,11cyclictest6341-21ls20:20:003
521799627,17cyclictest26055-21expr23:15:153
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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