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2025-11-29 - 09:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Sat Nov 29, 2025 00:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
50722210169,22sleep20-21swapper/219:07:532
51462208175,22sleep30-21swapper/319:08:503
51742204170,23sleep10-21swapper/119:09:121
49522203169,23sleep00-21swapper/019:06:260
52382168129,13sleep10-21swapper/119:10:021
553199643,59cyclictest31459-21kworker/2:220:10:252
136591610,1ptp4l401ktimersoftd/323:40:143
5529995926,7cyclictest9-21ksoftirqd/023:45:150
5529995826,6cyclictest9-21ksoftirqd/019:40:130
5529995820,6cyclictest9-21ksoftirqd/022:50:220
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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