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2025-11-16 - 06:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Sun Nov 16, 2025 00:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
136691220162,47phc2sys0-21swapper/319:05:473
15112206172,22sleep20-21swapper/219:06:422
14612204171,22sleep00-21swapper/019:06:040
15572203169,23sleep10-21swapper/119:07:131
43321840,8sleep1208199cyclictest20:10:261
3147221640,7sleep1208199cyclictest21:15:261
208099580,21cyclictest27422-21irqstats22:15:200
208099570,27cyclictest10072-21tr22:45:250
136591530,36ptp4l0-21swapper/319:10:013
51032520,2sleep20-21swapper/221:30:162
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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