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2026-04-16 - 01:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Wed Apr 15, 2026 12:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
289802233168,22sleep30-21swapper/307:08:583
288252228164,22sleep00-21swapper/007:07:010
288392205172,22sleep20-21swapper/207:07:112
287342204171,22sleep10-21swapper/107:05:511
2260321750,6sleep02935299cyclictest09:10:170
890321560,6sleep12935399cyclictest07:35:111
2349421500,6sleep12935399cyclictest11:25:251
1790821280,4sleep22935499cyclictest10:08:042
139291650,1ptp4l401ktimersoftd/310:40:153
139291640,1ptp4l401ktimersoftd/310:30:163
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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