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2026-06-29 - 15:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Mon Jun 29, 2026 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
263382232166,23sleep00-21swapper/007:09:190
139591207174,22phc2sys0-21swapper/307:05:013
261282206172,23sleep20-21swapper/207:06:362
242672206172,22sleep10-21swapper/107:05:061
1048221550,6sleep32669399cyclictest11:05:183
26692997231,6cyclictest33-21ksoftirqd/211:20:002
26692996834,5cyclictest33-21ksoftirqd/208:20:162
26692996531,6cyclictest33-21ksoftirqd/210:05:002
26692996530,4cyclictest33-21ksoftirqd/210:40:002
26692996433,4cyclictest33-21ksoftirqd/209:00:232
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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