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2026-04-10 - 18:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Fri Apr 10, 2026 12:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
154332204170,22sleep00-21swapper/007:07:360
152722204170,22sleep10-21swapper/107:05:311
152732203170,22sleep20-21swapper/207:05:322
139591203169,22phc2sys0-21swapper/307:05:043
634521470,4sleep01592099cyclictest11:20:010
1395918662,15phc2sys0-21swapper/307:10:013
139291730,10ptp4l401ktimersoftd/307:20:203
15920997129,3cyclictest9-21ksoftirqd/008:00:170
15920997129,3cyclictest9-21ksoftirqd/008:00:170
15921996833,4cyclictest25-21ksoftirqd/110:55:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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