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2026-09-07 - 23:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Mon Sep 07, 2026 12:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
190082230168,50sleep10-21swapper/107:07:261
189002226163,22sleep20-21swapper/207:06:022
188862205172,22sleep30-21swapper/307:05:513
191092202168,22sleep00-21swapper/007:08:450
2782521730,6sleep31950499cyclictest08:35:013
1920928362,11sleep30-21swapper/307:10:013
1950299692,22cyclictest16961-21date10:25:221
19504996831,8cyclictest41-21ksoftirqd/310:15:003
19503996832,8cyclictest33-21ksoftirqd/209:40:142
19504996734,8cyclictest41-21ksoftirqd/307:45:273
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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