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2025-05-09 - 05:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Fri May 09, 2025 00:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
275242222165,46sleep10-21swapper/119:09:231
272002205171,23sleep30-21swapper/319:05:273
254532204170,23sleep20-21swapper/219:05:112
273342203170,22sleep00-21swapper/019:06:540
275732145120,14sleep20-21swapper/219:10:012
119421230,2sleep02786499cyclictest22:45:000
137291610,1ptp4l401ktimersoftd/320:05:003
265752570,5sleep02786499cyclictest22:30:000
35582530,2sleep20-21swapper/221:40:192
2786599481,9cyclictest29071-21cpu22:35:151
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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