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2025-12-03 - 09:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Wed Dec 03, 2025 00:45:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
283892232167,23sleep10-21swapper/119:08:151
136691210175,24phc2sys0-21swapper/319:07:573
283452206173,22sleep20-21swapper/219:07:392
282392202170,22sleep00-21swapper/019:06:200
1765521600,7sleep22881999cyclictest21:00:162
1959421490,6sleep32882099cyclictest00:25:213
2881999685,61cyclictest24569-21kworker/2:122:50:252
2882099649,16cyclictest18747-21/usr/sbin/munin19:55:203
2881999640,24cyclictest18298-21cat22:10:002
2881999631,24cyclictest29983-21sed20:15:292
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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