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2026-09-23 - 02:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Tue Sep 22, 2026 12:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591209164,33phc2sys0-21swapper/307:08:343
67082207174,22sleep20-21swapper/207:08:012
67072206173,22sleep10-21swapper/107:07:591
67262203170,22sleep00-21swapper/007:08:140
1395918363,11phc2sys0-21swapper/307:10:003
139291730,1ptp4l30486-21latency_hist09:05:003
7161996722,4cyclictest9-21ksoftirqd/008:40:000
716399668,16cyclictest0-21swapper/209:10:152
716399649,11cyclictest7503-21sed11:35:262
716399648,10cyclictest29244-21wc09:00:202
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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