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2026-01-08 - 14:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Thu Jan 08, 2026 00:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
231332209175,23sleep00-21swapper/019:07:220
231722208175,22sleep20-21swapper/219:07:522
230862205172,22sleep30-21swapper/319:06:453
212012203169,22sleep10-21swapper/119:05:021
104312700,2sleep20-21swapper/200:15:252
139291640,1ptp4l401ktimersoftd/322:35:003
23637996014,44cyclictest0-21swapper/121:55:451
2363899541,17cyclictest217-21systemd-journal00:21:282
139291540,1ptp4l401ktimersoftd/323:25:253
139291540,1ptp4l401ktimersoftd/319:38:073
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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