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2026-11-10 - 09:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Mon Nov 09, 2026 12:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591235168,22phc2sys0-21swapper/307:08:073
139591235168,22phc2sys0-21swapper/307:08:073
314662231169,50sleep00-21swapper/007:08:370
314662231169,50sleep00-21swapper/007:08:370
314532207173,22sleep20-21swapper/207:08:262
314532207173,22sleep20-21swapper/207:08:262
315462206172,22sleep10-21swapper/107:09:371
315462206172,22sleep10-21swapper/107:09:371
2952121520,1sleep30-21swapper/310:25:203
69592750,5sleep13187599cyclictest10:45:241
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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