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2025-12-29 - 14:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Mon Dec 29, 2025 00:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
48332232170,50sleep20-21swapper/219:08:152
139591209175,22phc2sys0-21swapper/319:07:333
49562206173,22sleep00-21swapper/019:09:490
48072206171,23sleep10-21swapper/119:07:541
139291580,1ptp4l401ktimersoftd/321:45:313
139291560,1ptp4l401ktimersoftd/319:20:243
5262995514,3cyclictest33-21ksoftirqd/223:10:002
132952520,1sleep30-21swapper/320:35:003
5262995120,4cyclictest33-21ksoftirqd/220:25:192
5262995120,4cyclictest33-21ksoftirqd/220:25:182
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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