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2025-12-19 - 10:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Fri Dec 19, 2025 00:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591233168,22phc2sys0-21swapper/319:06:583
147562216154,50sleep10-21swapper/119:07:581
148562207173,23sleep00-21swapper/019:09:140
147942206173,22sleep20-21swapper/219:08:272
149152163124,14sleep30-21swapper/319:10:003
277102720,7sleep31521099cyclictest20:40:263
139291600,1ptp4l401ktimersoftd/323:05:303
277042570,2sleep30-21swapper/321:50:143
109202560,2sleep20-21swapper/200:35:242
139291530,8ptp4l401ktimersoftd/319:51:183
139291510,8ptp4l0-21swapper/320:33:423
139291510,1ptp4l401ktimersoftd/323:35:013
260232500,2sleep30-21swapper/322:55:003
15208994842,3cyclictest10649-21dump-pmu-power21:15:001
139291470,0ptp4l401ktimersoftd/300:25:323
41298440,2rtkit-daemon0-21swapper/120:21:211
24342440,2sleep30-21swapper/322:05:143
139291440,0ptp4l401ktimersoftd/300:35:193
15210994339,3cyclictest41-21ksoftirqd/300:00:003
15209994314,27cyclictest25914-21kworker/2:022:35:352
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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