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2025-12-10 - 17:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Wed Dec 10, 2025 12:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
136691216170,36phc2sys0-21swapper/307:08:583
227672206171,24sleep20-21swapper/207:05:332
228912205171,23sleep10-21swapper/107:07:091
228602204169,23sleep00-21swapper/007:06:430
1177821520,6sleep02341199cyclictest11:15:160
2341499723,34cyclictest22353-21cat08:15:013
168122580,5sleep32341499cyclictest08:00:263
6552550,2sleep30-21swapper/312:00:163
290482530,1sleep20-21swapper/207:20:212
102682500,2sleep10-21swapper/107:50:011
136591440,0ptp4l401ktimersoftd/310:35:253
51698430,9rtkit-daemon0-21swapper/111:16:321
51698430,8rtkit-daemon0-21swapper/109:17:191
136591430,0ptp4l401ktimersoftd/312:07:153
23414994236,4cyclictest13633-21cron09:05:003
136591420,0ptp4l401ktimersoftd/311:35:373
136591420,0ptp4l401ktimersoftd/311:32:363
136591410,0ptp4l401ktimersoftd/308:45:333
136591410,0ptp4l401ktimersoftd/308:20:133
23411994033,4cyclictest4083-21cron08:45:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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