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2026-08-07 - 04:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Fri Aug 07, 2026 00:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591239170,23phc2sys0-21swapper/319:08:163
107702234168,22sleep10-21swapper/119:07:461
105912205171,22sleep20-21swapper/219:05:342
108302204171,21sleep00-21swapper/019:08:330
1094328263,10sleep30-21swapper/319:10:013
139291580,1ptp4l401ktimersoftd/322:21:403
71292490,1sleep10-21swapper/121:15:181
11237994740,4cyclictest26608-21cron20:50:002
139291450,0ptp4l401ktimersoftd/323:40:153
139291430,1ptp4l401ktimersoftd/323:49:273
11236994337,3cyclictest25-21ksoftirqd/121:14:591
11236994337,3cyclictest21160-21fschecks_count19:30:161
11238994235,5cyclictest41-21ksoftirqd/323:35:003
41298410,7rtkit-daemon0-21swapper/120:15:441
139291410,0ptp4l401ktimersoftd/320:20:003
11238994136,3cyclictest41-21ksoftirqd/322:30:013
11238994130,9cyclictest41-21ksoftirqd/300:00:293
11237994027,11cyclictest33-21ksoftirqd/222:35:002
139291390,0ptp4l401ktimersoftd/321:30:193
11238993935,3cyclictest41-21ksoftirqd/322:50:213
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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