You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2025-12-07 - 22:22
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Sun Dec 07, 2025 12:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
136691233167,23phc2sys0-21swapper/307:08:353
147782205172,22sleep10-21swapper/107:07:101
147542204170,23sleep20-21swapper/207:06:492
148662203170,22sleep00-21swapper/007:08:160
131582780,2sleep10-21swapper/110:25:321
1529999598,12cyclictest29283-21sed12:05:272
280002580,2sleep0111rcuc/011:00:010
1529999588,16cyclictest4060-21latency_hist10:10:012
1529999588,12cyclictest12763-21grep11:35:142
1529999588,12cyclictest12763-21grep11:35:142
1529999587,12cyclictest21997-21latency10:45:212
1529999585,11cyclictest20131-21sed11:50:012
1529999579,45cyclictest24607-21grep08:35:202
1529999577,11cyclictest80872sleep211:25:172
1529999576,12cyclictest7397-21fschecks_count08:00:162
1529999576,11cyclictest20561-21if_enp1s009:35:172
1529999566,16cyclictest19344-21unixbench_multi07:15:292
1529999566,11cyclictest20203-21cpuspeed_turbos07:20:152
1529999565,17cyclictest10395-21irqrtprio12:35:192
1529999565,17cyclictest10395-21irqrtprio12:35:192
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional