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2025-12-11 - 06:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Thu Dec 11, 2025 00:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
136691207173,23phc2sys0-21swapper/319:08:163
241222206172,23sleep10-21swapper/119:09:081
240542205171,23sleep20-21swapper/219:08:172
238922203170,22sleep00-21swapper/019:06:100
133291690,9getstats0-21swapper/300:10:503
37812630,4sleep13783-21irqrtprio20:40:181
47832530,2sleep10-21swapper/100:05:231
265552530,1sleep10-21swapper/122:35:191
24486995223,3cyclictest41-21ksoftirqd/323:40:223
24486995123,4cyclictest41-21ksoftirqd/300:25:233
24483995124,4cyclictest9-21ksoftirqd/000:35:290
24483995122,6cyclictest9-21ksoftirqd/023:50:300
24486995021,4cyclictest41-21ksoftirqd/319:50:123
24483995022,4cyclictest9-21ksoftirqd/021:40:280
24483995021,7cyclictest9-21ksoftirqd/000:15:140
24483995015,4cyclictest9-21ksoftirqd/000:20:170
24486994927,2cyclictest41-21ksoftirqd/321:10:143
24486994920,4cyclictest41-21ksoftirqd/319:55:153
24483994922,7cyclictest9-21ksoftirqd/023:55:140
24483994916,4cyclictest9-21ksoftirqd/019:50:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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