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2026-01-02 - 00:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Thu Jan 01, 2026 12:45:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591223160,51phc2sys0-21swapper/307:05:383
152872204171,22sleep20-21swapper/207:08:482
152962203169,23sleep10-21swapper/107:08:561
131752202169,22sleep00-21swapper/007:05:010
153832149124,13sleep10-21swapper/107:10:011
15675996924,4cyclictest25-21ksoftirqd/109:15:001
15675996430,10cyclictest25-21ksoftirqd/107:40:001
15675996022,7cyclictest25-21ksoftirqd/111:05:231
15675996016,9cyclictest25-21ksoftirqd/110:00:151
15675995828,9cyclictest25-21ksoftirqd/109:35:011
1567599575,3cyclictest25-21ksoftirqd/110:45:151
15675995722,6cyclictest25-21ksoftirqd/110:30:141
15675995623,10cyclictest25-21ksoftirqd/108:05:121
15675995620,7cyclictest25-21ksoftirqd/111:25:141
15675995618,8cyclictest25-21ksoftirqd/111:50:241
15675995617,3cyclictest25-21ksoftirqd/110:25:111
15675995610,4cyclictest25-21ksoftirqd/108:15:251
15675995521,10cyclictest25-21ksoftirqd/111:40:271
15675995519,6cyclictest25-21ksoftirqd/110:50:161
15675995516,7cyclictest25-21ksoftirqd/112:35:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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