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2026-03-29 - 12:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Sun Mar 29, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591235168,22phc2sys0-21swapper/319:09:093
244802209174,23sleep00-21swapper/019:06:400
226082205171,23sleep20-21swapper/219:05:052
226062203168,23sleep10-21swapper/119:05:051
2190921540,2sleep30-21swapper/322:25:173
2498621520,5sleep32503999cyclictest22:30:223
1544621280,3sleep32503999cyclictest23:20:003
1544621280,3sleep32503999cyclictest23:20:003
1395918969,11phc2sys0-21swapper/319:10:023
25038997814,62cyclictest28326-21kworker/2:119:11:252
314732630,4sleep02503699cyclictest20:30:170
25039994811,35cyclictest11461-21kworker/3:222:10:253
139291470,1ptp4l401ktimersoftd/321:12:543
25039994610,24cyclictest1308-21runrttasks00:03:193
25037994639,4cyclictest50792irq/128-enp1s0-23:10:461
25037994639,4cyclictest50792irq/128-enp1s0-23:10:461
2503899451,43cyclictest3930-21kworker/2:120:50:252
25039994310,31cyclictest9312-21kworker/3:120:53:253
139291420,0ptp4l401ktimersoftd/300:25:253
2503899412,36cyclictest12967-21cat23:15:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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