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2026-01-07 - 20:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Wed Jan 07, 2026 12:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
260322207174,22sleep00-21swapper/007:07:540
261322206173,22sleep30-21swapper/307:09:063
240602204169,23sleep20-21swapper/207:05:042
240592204170,22sleep10-21swapper/107:05:021
3058021760,2sleep32649799cyclictest10:40:153
1217621750,5sleep02649499cyclictest11:10:000
262032135108,15sleep10-21swapper/107:10:001
1395918662,15phc2sys0-21swapper/307:10:003
26496996535,7cyclictest33-21ksoftirqd/209:25:012
188942640,4sleep10-21swapper/111:20:281
26496996330,7cyclictest33-21ksoftirqd/208:00:002
16572630,7sleep12649599cyclictest08:30:231
26496996222,9cyclictest33-21ksoftirqd/207:25:192
26496996137,13cyclictest33-21ksoftirqd/211:25:252
26496996036,13cyclictest33-21ksoftirqd/209:45:222
26496995928,3cyclictest33-21ksoftirqd/210:00:262
26496995828,4cyclictest33-21ksoftirqd/209:35:002
26496995820,7cyclictest33-21ksoftirqd/210:40:002
26496995729,3cyclictest33-21ksoftirqd/210:40:252
26496995727,4cyclictest33-21ksoftirqd/212:15:132
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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