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2026-07-26 - 03:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Sat Jul 25, 2026 12:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591232169,51phc2sys0-21swapper/307:05:063
314152206171,23sleep10-21swapper/107:09:251
311672206172,22sleep00-21swapper/007:06:110
311642204170,22sleep20-21swapper/207:06:092
139291560,1ptp4l401ktimersoftd/307:19:273
278152520,1sleep327818-21awk12:35:303
3176399507,3cyclictest9244-21turbostat.cron12:04:552
256862490,2sleep20-21swapper/209:10:212
139291440,1ptp4l401ktimersoftd/311:24:343
139291430,0ptp4l401ktimersoftd/312:19:103
139291430,0ptp4l401ktimersoftd/310:05:303
139291430,0ptp4l401ktimersoftd/308:00:153
31764994237,3cyclictest41-21ksoftirqd/308:09:593
139291420,0ptp4l401ktimersoftd/310:28:223
139291420,0ptp4l401ktimersoftd/307:35:253
100352420,1sleep00-21swapper/012:00:160
31762994125,8cyclictest25-21ksoftirqd/111:38:201
139291410,0ptp4l401ktimersoftd/310:00:303
139291410,0ptp4l401ktimersoftd/307:28:053
31764994034,3cyclictest41-21ksoftirqd/307:50:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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