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2025-11-19 - 20:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Wed Nov 19, 2025 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
44782206173,22sleep20-21swapper/207:07:142
136691206172,23phc2sys0-21swapper/307:06:023
46142205173,21sleep10-21swapper/107:08:551
46032205172,22sleep00-21swapper/007:08:450
687821870,6sleep3499699cyclictest11:40:253
43452740,1sleep10-21swapper/109:20:271
217142680,5sleep24992-21cyclictest11:05:232
77142590,2sleep10-21swapper/109:30:011
140552560,6sleep3499699cyclictest07:25:323
77782550,2sleep30-21swapper/307:15:173
136591530,1ptp4l401ktimersoftd/310:33:163
149592500,1sleep20-21swapper/208:35:272
248162470,2sleep00-21swapper/007:50:160
60882460,2sleep30-21swapper/308:20:003
136591430,0ptp4l401ktimersoftd/312:35:013
136591430,0ptp4l401ktimersoftd/311:55:443
136591420,0ptp4l401ktimersoftd/312:38:243
136591420,0ptp4l401ktimersoftd/312:21:153
136591410,0ptp4l401ktimersoftd/311:49:373
499499401,37cyclictest12424-21kworker/1:007:16:551
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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