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2026-07-23 - 01:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Wed Jul 22, 2026 12:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
246022209175,22sleep00-21swapper/007:07:480
246562208173,23sleep30-21swapper/307:08:273
247662207172,23sleep10-21swapper/107:09:541
246652206172,22sleep20-21swapper/207:08:342
3137121430,3sleep12524199cyclictest11:50:261
2477628363,11sleep00-21swapper/007:10:010
174042700,2sleep20-21swapper/211:20:262
2524199669,55cyclictest0-21swapper/108:01:051
25241996525,18cyclictest25-21ksoftirqd/111:15:121
139291650,1ptp4l401ktimersoftd/310:17:073
25243996235,5cyclictest33-21ksoftirqd/212:19:592
25243996229,5cyclictest33-21ksoftirqd/210:25:142
25243996228,5cyclictest33-21ksoftirqd/209:15:222
139291620,1ptp4l401ktimersoftd/307:38:263
25243996131,3cyclictest33-21ksoftirqd/211:50:262
25243996027,4cyclictest33-21ksoftirqd/208:10:192
25243996027,4cyclictest33-21ksoftirqd/207:55:192
25243995930,3cyclictest33-21ksoftirqd/209:05:172
25243995928,6cyclictest33-21ksoftirqd/212:25:162
25243995928,4cyclictest33-21ksoftirqd/210:30:162
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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