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2026-09-09 - 11:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Wed Sep 09, 2026 00:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591231166,52phc2sys0-21swapper/319:07:583
305302206172,22sleep00-21swapper/019:06:010
306582205174,20sleep20-21swapper/219:07:362
305752205171,22sleep10-21swapper/119:06:291
3051521500,3sleep23113699cyclictest22:30:172
31136998331,4cyclictest33-21ksoftirqd/219:20:252
139291830,1ptp4l20231-21ptp4l23:15:243
31136997422,10cyclictest33-21ksoftirqd/223:50:192
31136997224,10cyclictest33-21ksoftirqd/222:25:162
31136997128,5cyclictest33-21ksoftirqd/223:20:282
31135997011,12cyclictest15476-21latency_hist19:44:591
31136996925,4cyclictest33-21ksoftirqd/223:45:262
31136996920,9cyclictest33-21ksoftirqd/223:05:182
31135996914,10cyclictest20237-21/usr/sbin/munin22:10:121
31135996813,12cyclictest18070-21/usr/sbin/munin22:05:131
31136996726,9cyclictest33-21ksoftirqd/221:40:102
31135996712,11cyclictest28262-21wc22:25:201
31134996727,4cyclictest9-21ksoftirqd/020:25:000
31135996611,11cyclictest5769-21cat19:25:011
31135996610,11cyclictest20335-21ptp4l-jitter21:00:251
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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