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2026-06-25 - 14:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Thu Jun 25, 2026 00:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591208175,22phc2sys0-21swapper/319:07:233
62712207173,22sleep10-21swapper/119:07:071
62002206173,22sleep20-21swapper/219:06:122
43672204169,23sleep00-21swapper/019:05:050
679799811,77cyclictest1290-21kworker/2:120:05:252
139291800,5ptp4l679899cyclictest20:00:163
185662620,1sleep00-21swapper/021:50:010
158562610,2sleep10-21swapper/120:35:161
313602600,6sleep0679599cyclictest00:30:150
185772600,5sleep3679899cyclictest19:35:013
256812550,2sleep20-21swapper/219:50:002
212752510,3sleep20-21swapper/219:40:132
6795994842,3cyclictest7878-21awk22:35:000
139291470,1ptp4l401ktimersoftd/320:56:393
139291450,1ptp4l401ktimersoftd/321:45:363
139291440,0ptp4l401ktimersoftd/322:35:203
6798994338,3cyclictest41-21ksoftirqd/319:40:003
6798994337,4cyclictest24534-21cron20:55:003
139291430,0ptp4l401ktimersoftd/322:50:233
139291420,0ptp4l401ktimersoftd/300:23:063
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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