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2026-05-01 - 17:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Fri May 01, 2026 12:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1069822870,4sleep0101ktimersoftd/007:05:140
139591215171,33phc2sys0-21swapper/307:07:143
122432208173,23sleep10-21swapper/107:07:451
124192205172,22sleep20-21swapper/207:09:562
1271899771,74cyclictest0-21swapper/109:00:061
12718997416,56cyclictest0-21swapper/110:06:451
307362620,5sleep230740-21ptp4l-jitter07:45:252
139291610,1ptp4l401ktimersoftd/309:10:163
1271799616,11cyclictest9239-21strings09:15:210
84172600,4sleep20-21swapper/212:35:252
1271799605,11cyclictest4793-21grep09:05:240
1271799605,11cyclictest4793-21grep09:05:240
1271799595,11cyclictest15929-21sed07:15:200
1271799595,11cyclictest15929-21sed07:15:200
1271799594,11cyclictest4624-21sed10:15:010
5212570,2sleep10-21swapper/107:50:211
1271799574,11cyclictest27267-21date12:10:000
1271799574,10cyclictest16571-21latency_hist10:40:000
139291550,1ptp4l401ktimersoftd/309:16:363
1271799554,17cyclictest10565-21grep09:20:110
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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