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2026-07-10 - 20:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Fri Jul 10, 2026 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
255192233204,19sleep20-21swapper/207:07:592
139591230164,22phc2sys0-21swapper/307:09:583
254062207172,23sleep10-21swapper/107:06:291
253582206172,22sleep00-21swapper/007:05:520
2115521510,2sleep00-21swapper/008:05:210
25977996530,4cyclictest33-21ksoftirqd/208:20:202
46472640,2sleep00-21swapper/007:30:270
46472640,2sleep00-21swapper/007:30:270
25976996431,8cyclictest25-21ksoftirqd/109:55:001
304022630,6sleep030403-21irqrtprio10:40:180
139291630,1ptp4l401ktimersoftd/310:15:393
25976996222,10cyclictest25-21ksoftirqd/108:35:241
25976996220,9cyclictest25-21ksoftirqd/107:55:281
25976996219,8cyclictest25-21ksoftirqd/110:25:171
25976996125,7cyclictest25-21ksoftirqd/111:40:141
25976996030,3cyclictest25-21ksoftirqd/110:00:251
25976996027,7cyclictest25-21ksoftirqd/110:45:011
25976996025,4cyclictest25-21ksoftirqd/109:05:271
25976996025,3cyclictest25-21ksoftirqd/110:20:141
25976996022,8cyclictest25-21ksoftirqd/109:30:271
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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