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2026-08-19 - 08:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Wed Aug 19, 2026 00:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
178622247194,18sleep10-21swapper/119:07:331
180632205172,22sleep20-21swapper/219:09:102
139591205172,22phc2sys0-21swapper/319:06:513
177282202170,21sleep00-21swapper/019:06:030
156021610,7sleep01849199cyclictest19:14:050
810221480,6sleep11849299cyclictest21:09:591
784721360,5sleep31849499cyclictest00:30:193
2861221260,6sleep01849199cyclictest21:50:220
139291690,1ptp4l401ktimersoftd/320:42:293
139291690,1ptp4l401ktimersoftd/320:42:293
139291690,0ptp4l401ktimersoftd/319:13:583
133852670,6sleep213360-21sh19:19:212
133852670,6sleep213360-21sh19:19:212
66732650,6sleep06639-21sh19:19:150
66732650,6sleep06639-21sh19:19:140
71412630,5sleep120758-21spawn19:13:061
77302590,3sleep07728-21rm19:21:150
70222580,2sleep36900-21multi.sh19:21:143
201222580,1sleep00-21swapper/022:40:210
18492995614,4cyclictest25-21ksoftirqd/123:34:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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