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2025-12-30 - 18:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Tue Dec 30, 2025 12:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
137952236169,23sleep00-21swapper/007:06:350
137952236169,23sleep00-21swapper/007:06:350
139032223195,19sleep10-21swapper/107:08:021
139032223195,19sleep10-21swapper/107:08:021
137292205172,22sleep20-21swapper/207:05:452
137292205172,22sleep20-21swapper/207:05:452
137912203170,22sleep30-21swapper/307:06:353
137912203170,22sleep30-21swapper/307:06:343
1662921580,6sleep21436099cyclictest08:20:182
185762590,2sleep00-21swapper/008:25:130
22882580,3sleep32292-21irqrtprio12:20:213
22882580,3sleep32292-21irqrtprio12:20:213
301822540,2sleep00-21swapper/008:50:010
159422500,2sleep20-21swapper/209:25:252
139291490,1ptp4l401ktimersoftd/308:17:423
313462480,2sleep21436099cyclictest07:45:012
139291470,1ptp4l401ktimersoftd/309:26:553
14358994539,3cyclictest26356-21anacron12:03:000
139291440,0ptp4l401ktimersoftd/308:59:563
14359994337,4cyclictest7162-21cron09:10:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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