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2025-12-08 - 22:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Mon Dec 08, 2025 12:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
39882235168,23sleep30-21swapper/307:08:233
38732227164,22sleep10-21swapper/107:06:521
39092206172,23sleep20-21swapper/207:07:212
38102201167,22sleep00-21swapper/007:06:020
2725321410,6sleep1441299cyclictest10:10:211
1365911070,1ptp4l18222-21sed11:00:203
136591670,1ptp4l401ktimersoftd/312:38:593
136591610,1ptp4l401ktimersoftd/311:52:523
4411995955,2cyclictest111rcuc/008:25:160
4411995955,2cyclictest111rcuc/008:25:150
101412590,7sleep210145-21irqrtprio09:35:202
4411995425,6cyclictest9-21ksoftirqd/010:00:000
4411995425,6cyclictest9-21ksoftirqd/010:00:000
441199536,7cyclictest9-21ksoftirqd/009:00:280
4411995322,6cyclictest9-21ksoftirqd/012:10:010
169322530,1sleep20-21swapper/210:55:272
263052520,2sleep00-21swapper/007:55:160
263052520,2sleep00-21swapper/007:55:160
27892500,2sleep30-21swapper/311:35:203
441199496,9cyclictest9-21ksoftirqd/011:55:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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