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2025-11-28 - 04:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Fri Nov 28, 2025 00:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
136691208175,22phc2sys0-21swapper/319:06:493
80802206173,22sleep20-21swapper/219:08:402
78432206171,24sleep10-21swapper/119:05:421
78422204171,22sleep00-21swapper/019:05:400
249412700,2sleep10-21swapper/120:50:201
136592590,3sleep00-21swapper/020:25:230
862299580,55cyclictest6285-21kworker/1:223:15:251
122992570,2sleep30-21swapper/321:30:213
122802550,2sleep30-21swapper/322:35:293
862299510,2cyclictest2352-21kworker/1:122:15:251
136591480,1ptp4l391rcuc/323:58:073
51698450,8rtkit-daemon0-21swapper/220:59:522
51698450,10rtkit-daemon0-21swapper/220:47:282
136591440,0ptp4l401ktimersoftd/320:35:203
136591420,0ptp4l401ktimersoftd/300:11:503
51698400,7rtkit-daemon0-21swapper/320:23:483
8623993832,4cyclictest24687-21cron23:05:002
862399380,3cyclictest121rcu_preempt22:35:152
51698370,7rtkit-daemon0-21swapper/321:13:413
8623993626,9cyclictest33-21ksoftirqd/222:40:272
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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