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2026-06-01 - 02:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Sun May 31, 2026 12:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
57302233168,22sleep10-21swapper/107:06:341
139591208174,22phc2sys0-21swapper/307:09:533
56912205172,22sleep20-21swapper/207:06:042
57862204170,23sleep00-21swapper/007:07:190
3117821010,1sleep10-21swapper/108:00:231
3117821010,1sleep10-21swapper/108:00:221
139291650,1ptp4l401ktimersoftd/310:48:223
139291640,1ptp4l401ktimersoftd/309:00:213
6297996231,4cyclictest25-21ksoftirqd/108:05:161
6297996226,4cyclictest25-21ksoftirqd/112:05:201
6297996225,4cyclictest25-21ksoftirqd/109:20:291
6297996129,8cyclictest25-21ksoftirqd/109:30:211
6297996124,4cyclictest25-21ksoftirqd/110:15:241
6297996028,4cyclictest25-21ksoftirqd/111:35:001
6297996026,4cyclictest25-21ksoftirqd/111:05:181
6297996026,4cyclictest25-21ksoftirqd/111:00:261
6297996025,7cyclictest25-21ksoftirqd/112:25:191
6297996025,7cyclictest25-21ksoftirqd/108:15:161
6297996025,3cyclictest25-21ksoftirqd/110:30:281
6297996023,3cyclictest25-21ksoftirqd/108:55:251
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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