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2025-12-09 - 13:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Tue Dec 09, 2025 00:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
66432235169,23sleep10-21swapper/119:06:351
136691211172,28phc2sys0-21swapper/319:07:423
66862204170,23sleep20-21swapper/219:07:042
47862201168,22sleep00-21swapper/019:05:090
1708521700,8sleep2735899cyclictest19:30:142
58422650,2sleep00-21swapper/023:35:160
31402590,3sleep30-21swapper/300:35:253
31402590,3sleep30-21swapper/300:35:253
7358995722,4cyclictest33-21ksoftirqd/220:15:002
7358995720,9cyclictest33-21ksoftirqd/223:50:012
7358995619,4cyclictest33-21ksoftirqd/200:05:282
7358995618,8cyclictest33-21ksoftirqd/219:25:162
281702560,2sleep20-21swapper/221:00:012
7358995524,8cyclictest33-21ksoftirqd/220:45:002
7358995524,8cyclictest33-21ksoftirqd/220:45:002
7358995521,3cyclictest33-21ksoftirqd/221:35:222
7358995423,9cyclictest33-21ksoftirqd/222:15:002
7358995423,9cyclictest33-21ksoftirqd/222:15:002
7358995421,4cyclictest33-21ksoftirqd/200:35:182
7358995421,4cyclictest33-21ksoftirqd/200:35:172
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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