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2026-08-31 - 10:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Mon Aug 31, 2026 00:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
40312237170,22sleep00-21swapper/019:07:530
139591208174,22phc2sys0-21swapper/319:07:513
20082207172,23sleep10-21swapper/119:05:031
40962206171,23sleep20-21swapper/219:08:432
684621670,4sleep0448899cyclictest22:35:250
684621670,4sleep0448899cyclictest22:35:250
3013121590,6sleep3449199cyclictest22:15:303
2320121430,5sleep3449199cyclictest00:15:283
1392911150,1ptp4l29622-21memory00:30:243
419628562,13sleep30-21swapper/319:10:013
139291610,1ptp4l401ktimersoftd/323:27:003
185482570,4sleep118554-21latency20:45:211
185482570,4sleep118554-21latency20:45:211
4491995639,14cyclictest23035-21sh22:05:013
4489995448,3cyclictest11117-21awk21:39:591
139291540,1ptp4l401ktimersoftd/319:53:483
264742520,1sleep30-21swapper/323:15:273
4491994613,19cyclictest7714-21needreboot21:30:233
4489994639,4cyclictest1308-21runrttasks21:49:561
4489994639,4cyclictest1308-21runrttasks21:49:551
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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