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2025-11-25 - 23:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Tue Nov 25, 2025 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
136691238170,23phc2sys0-21swapper/307:08:303
191752207141,22sleep10-21swapper/107:08:141
190422204171,22sleep20-21swapper/207:06:302
189772204171,22sleep00-21swapper/007:05:390
1932128363,11sleep30-21swapper/307:10:003
136591730,10ptp4l401ktimersoftd/312:17:413
19614995728,4cyclictest9-21ksoftirqd/008:55:140
19614995728,4cyclictest9-21ksoftirqd/008:55:140
19614995725,4cyclictest9-21ksoftirqd/011:15:200
19615995623,8cyclictest25-21ksoftirqd/111:40:001
19614995629,4cyclictest9-21ksoftirqd/010:50:230
19615995526,4cyclictest25-21ksoftirqd/110:10:121
19614995529,3cyclictest9-21ksoftirqd/010:10:200
19614995527,4cyclictest9-21ksoftirqd/011:35:210
19614995527,3cyclictest9-21ksoftirqd/009:45:260
19614995525,4cyclictest9-21ksoftirqd/009:40:270
19614995524,3cyclictest9-21ksoftirqd/011:40:200
19614995522,3cyclictest9-21ksoftirqd/009:15:200
320412540,1sleep30-21swapper/310:55:263
19615995428,4cyclictest25-21ksoftirqd/108:25:241
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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