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2026-08-16 - 07:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Sun Aug 16, 2026 00:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
127412208174,23sleep30-21swapper/319:06:573
127452205171,22sleep20-21swapper/219:07:002
126792205171,22sleep10-21swapper/119:06:151
127482204170,22sleep00-21swapper/019:07:030
200221600,6sleep01327099cyclictest00:20:250
2505121590,3sleep11327199cyclictest20:40:221
129782146121,14sleep10-21swapper/119:10:001
201922690,5sleep120194-21latency_hist19:25:001
45432540,6sleep31327399cyclictest20:00:003
139291520,1ptp4l391rcuc/322:55:153
139291440,0ptp4l401ktimersoftd/320:18:143
139291420,1ptp4l401ktimersoftd/300:09:253
139291420,0ptp4l401ktimersoftd/323:17:103
139291420,0ptp4l401ktimersoftd/320:34:233
139291420,0ptp4l401ktimersoftd/320:34:233
139291420,0ptp4l401ktimersoftd/319:36:023
1327399420,40cyclictest9248-21latency_hist20:10:003
13272994230,10cyclictest33-21ksoftirqd/220:30:162
13272994230,10cyclictest33-21ksoftirqd/220:30:162
13272994222,17cyclictest25957-21cron20:45:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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