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2025-12-14 - 03:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Sun Dec 14, 2025 00:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
194612224191,23sleep00-21swapper/019:05:020
213762219185,23sleep10-21swapper/119:07:121
215862215180,24sleep20-21swapper/219:09:502
215052212179,22sleep30-21swapper/319:08:463
1627921580,2sleep00-21swapper/020:05:240
173042730,5sleep317309-21missed_timers00:35:313
253112610,2sleep00-21swapper/021:30:280
139291560,1ptp4l401ktimersoftd/319:40:563
79362530,2sleep3401ktimersoftd/320:55:253
139291530,0ptp4l401ktimersoftd/320:40:303
139291530,0ptp4l401ktimersoftd/320:40:303
232402510,2sleep20-21swapper/222:35:242
139291460,0ptp4l401ktimersoftd/322:04:563
139291440,0ptp4l401ktimersoftd/319:54:193
2189299437,3cyclictest25-21ksoftirqd/123:00:001
139291430,35ptp4l0-21swapper/319:10:003
139291430,0ptp4l401ktimersoftd/322:59:533
139291420,0ptp4l401ktimersoftd/323:45:263
139291420,0ptp4l401ktimersoftd/319:47:233
139291410,1ptp4l401ktimersoftd/322:50:203
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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