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2025-11-18 - 05:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Tue Nov 18, 2025 00:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139202233165,22sleep20-21swapper/219:07:132
136691214170,33phc2sys0-21swapper/319:07:543
138172204171,22sleep10-21swapper/119:05:521
120132202169,22sleep00-21swapper/019:05:060
1366918563,15phc2sys0-21swapper/319:10:003
136591810,1ptp4l391rcuc/321:45:113
136591730,1ptp4l391rcuc/323:40:263
282532570,2sleep20-21swapper/223:00:212
136591560,0ptp4l391rcuc/300:25:053
17372550,3sleep1231rcuc/119:50:211
247792530,2sleep20-21swapper/219:30:192
1443999507,10cyclictest6609-21sed23:25:003
136591490,0ptp4l391rcuc/321:44:573
133391490,2getstats0-21swapper/322:10:173
14439994819,3cyclictest41-21ksoftirqd/319:58:483
14439994618,8cyclictest41-21ksoftirqd/300:18:563
14439994618,7cyclictest41-21ksoftirqd/323:01:133
14439994617,7cyclictest41-21ksoftirqd/319:26:173
1443999456,7cyclictest6961-21awk22:15:273
14439994517,7cyclictest41-21ksoftirqd/322:05:333
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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