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2026-05-25 - 23:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Mon May 25, 2026 12:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591237169,22phc2sys0-21swapper/307:09:193
123372208175,22sleep20-21swapper/207:08:222
124382205170,23sleep10-21swapper/107:09:381
122262201167,22sleep00-21swapper/007:06:560
1247228763,15sleep00-21swapper/007:10:010
139291840,1ptp4l22516-21df12:00:143
29162620,2sleep30-21swapper/309:05:003
12764995927,7cyclictest25-21ksoftirqd/108:10:001
12764995823,7cyclictest25-21ksoftirqd/110:00:101
12764995822,8cyclictest25-21ksoftirqd/110:05:181
139291560,1ptp4l401ktimersoftd/308:34:163
12764995653,2cyclictest231rcuc/109:59:551
12764995621,4cyclictest25-21ksoftirqd/110:38:081
1276499556,9cyclictest25-21ksoftirqd/108:20:121
1276499556,7cyclictest25-21ksoftirqd/108:00:161
1276499555,6cyclictest25-21ksoftirqd/110:25:221
12764995528,8cyclictest25-21ksoftirqd/112:25:171
12764995520,7cyclictest25-21ksoftirqd/109:06:161
1276499546,9cyclictest25-21ksoftirqd/111:45:241
1276499546,8cyclictest25-21ksoftirqd/110:55:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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