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2026-06-19 - 10:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Fri Jun 19, 2026 00:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
266062236170,21sleep30-21swapper/319:08:003
266952231167,21sleep00-21swapper/019:09:100
267192208175,22sleep20-21swapper/219:09:282
265842204171,21sleep10-21swapper/119:07:421
1637521700,5sleep22705699cyclictest23:15:182
2155021440,5sleep32705799cyclictest20:05:123
2166421430,6sleep02705499cyclictest20:05:130
27057997326,10cyclictest41-21ksoftirqd/322:30:193
27057997030,5cyclictest41-21ksoftirqd/300:40:003
27057996734,4cyclictest41-21ksoftirqd/323:40:293
27057996534,4cyclictest41-21ksoftirqd/322:45:013
27057996533,4cyclictest41-21ksoftirqd/321:35:193
27057996532,4cyclictest41-21ksoftirqd/319:35:003
274542640,6sleep22705699cyclictest23:40:142
27057996433,4cyclictest41-21ksoftirqd/320:40:173
27057996433,4cyclictest41-21ksoftirqd/320:40:173
2676226441,12sleep30-21swapper/319:10:013
27057996332,8cyclictest41-21ksoftirqd/300:00:263
27057996332,4cyclictest41-21ksoftirqd/320:00:253
27057996332,4cyclictest41-21ksoftirqd/319:50:143
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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