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2026-04-02 - 17:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Thu Apr 02, 2026 12:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
132122840,4sleep00-21swapper/007:09:550
192222770,9sleep11915-21sh07:09:551
1191222660,3sleep30-21swapper/307:09:153
909622490,5sleep20-21swapper/207:09:102
2263721430,6sleep222640-21irqrtprio12:15:152
1934621320,2sleep30-21swapper/307:10:233
704221300,4sleep2384799cyclictest10:35:192
140782690,2sleep10-21swapper/110:50:181
269322600,2sleep30-21swapper/307:50:003
139291590,1ptp4l401ktimersoftd/312:30:143
220742580,2sleep00-21swapper/010:00:140
139291560,1ptp4l401ktimersoftd/310:03:473
139291540,1ptp4l401ktimersoftd/308:30:153
139291530,1ptp4l391rcuc/308:13:343
295732500,4sleep029579-21irqrtprio10:15:190
384799461,42cyclictest1312-21snmpd09:05:062
384899452,40cyclictest27037-21tr10:10:193
139291420,0ptp4l401ktimersoftd/311:36:143
139291420,0ptp4l401ktimersoftd/307:16:563
139291410,0ptp4l401ktimersoftd/307:55:353
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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