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2026-03-26 - 10:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Thu Mar 26, 2026 00:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
169432208174,22sleep30-21swapper/319:07:333
168372204171,22sleep20-21swapper/219:06:122
167952204170,22sleep00-21swapper/019:05:370
168362203169,22sleep10-21swapper/119:06:111
171372148123,14sleep10-21swapper/119:10:001
139591148122,15phc2sys0-21swapper/319:10:003
59002580,3sleep21743199cyclictest21:00:172
59002580,3sleep21743199cyclictest21:00:172
153282550,2sleep20-21swapper/223:35:172
139291550,1ptp4l401ktimersoftd/322:05:463
202172530,1sleep30-21swapper/320:20:263
263342470,2sleep10-21swapper/120:35:151
139291470,0ptp4l401ktimersoftd/300:35:183
17430994337,3cyclictest25-21ksoftirqd/119:20:001
139291430,1ptp4l401ktimersoftd/300:23:553
139291430,0ptp4l401ktimersoftd/323:14:463
139291420,0ptp4l401ktimersoftd/321:53:373
139291420,0ptp4l401ktimersoftd/321:35:013
139291420,0ptp4l401ktimersoftd/320:28:133
139291410,1ptp4l401ktimersoftd/323:34:533
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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