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2026-05-15 - 19:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Fri May 15, 2026 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11152240176,53sleep30-21swapper/307:05:433
13692214154,48sleep10-21swapper/107:08:461
14722205172,23sleep00-21swapper/007:09:590
11562205170,23sleep20-21swapper/207:06:142
1400621720,5sleep0177199cyclictest08:40:190
139291620,7ptp4l401ktimersoftd/310:45:563
139291620,7ptp4l401ktimersoftd/310:45:563
202502600,7sleep1177299cyclictest08:55:001
202502600,7sleep1177299cyclictest08:55:001
194992570,7sleep1177299cyclictest10:00:151
120972550,2sleep30-21swapper/308:35:263
1771995220,4cyclictest9-21ksoftirqd/009:00:190
1771995117,5cyclictest9-21ksoftirqd/010:35:000
139291510,1ptp4l401ktimersoftd/308:40:093
1771994944,2cyclictest9-21ksoftirqd/007:30:000
1771994815,7cyclictest9-21ksoftirqd/009:25:220
157552480,1sleep00-21swapper/009:50:230
1771994718,3cyclictest9-21ksoftirqd/012:05:240
1771994715,5cyclictest9-21ksoftirqd/012:20:160
1771994713,6cyclictest9-21ksoftirqd/008:10:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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