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2026-08-01 - 03:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Fri Jul 31, 2026 12:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
180262236168,23sleep30-21swapper/307:09:413
177122205171,23sleep20-21swapper/207:05:422
177272204171,22sleep10-21swapper/107:05:531
177412202169,22sleep00-21swapper/007:06:040
199621400,1sleep20-21swapper/208:50:002
139291790,1ptp4l391rcuc/309:15:133
18347996913,10cyclictest17172-21latency_hist08:15:003
18347996611,10cyclictest3022-21cut08:50:193
18347996611,10cyclictest22486-21latency_hist10:40:013
18347996611,10cyclictest10143-21unixbench_singl10:10:273
1834799659,16cyclictest0-21swapper/312:05:143
1834799659,11cyclictest0-21swapper/309:30:293
1834799659,11cyclictest0-21swapper/309:25:143
18347996515,10cyclictest21881-21latency_hist08:25:003
18347996514,10cyclictest4714-21expr08:55:143
18347996512,18cyclictest23242-21cpuspeed07:20:133
18347996511,12cyclictest24374-21sed11:50:183
18347996511,10cyclictest6473-21irqrtprio12:20:163
18347996511,10cyclictest15112-21latency_hist12:40:003
1834799649,16cyclictest0-21swapper/307:45:213
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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