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2025-12-29 - 20:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Mon Dec 29, 2025 12:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591221193,19phc2sys0-21swapper/307:07:383
301962208174,22sleep10-21swapper/107:07:461
302822205172,22sleep00-21swapper/007:08:530
303002203170,22sleep20-21swapper/207:09:062
140721330,4sleep23067099cyclictest08:20:272
139291650,1ptp4l401ktimersoftd/307:50:273
139291600,1ptp4l401ktimersoftd/312:17:243
43612550,2sleep10-21swapper/107:20:241
139291550,1ptp4l401ktimersoftd/311:57:013
139291540,1ptp4l401ktimersoftd/307:57:453
139291530,1ptp4l401ktimersoftd/312:25:163
216482520,3sleep021651-21switchtime07:55:260
139291520,1ptp4l401ktimersoftd/310:43:203
139291510,43ptp4l0-21swapper/307:10:013
139291510,1ptp4l401ktimersoftd/309:03:003
82562490,1sleep20-21swapper/207:30:172
30669994540,3cyclictest19932-21cron07:55:001
139291440,0ptp4l401ktimersoftd/307:19:553
139291430,1ptp4l401ktimersoftd/309:15:493
139291430,0ptp4l401ktimersoftd/309:35:303
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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