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2026-08-22 - 08:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Sat Aug 22, 2026 00:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
234902229166,51sleep20-21swapper/219:07:142
234902229166,51sleep20-21swapper/219:07:132
139591211178,22phc2sys0-21swapper/319:08:523
139591211178,22phc2sys0-21swapper/319:08:513
235242205171,22sleep10-21swapper/119:07:411
235242205171,22sleep10-21swapper/119:07:401
234782205171,22sleep00-21swapper/019:07:040
234782205171,22sleep00-21swapper/019:07:040
205921630,5sleep32399999cyclictest21:45:163
2370528765,12sleep00-21swapper/019:10:000
1395918662,16phc2sys0-21swapper/319:10:013
139291700,1ptp4l391rcuc/321:55:223
23996996710,16cyclictest20975-21systemctl21:15:240
23999996434,9cyclictest41-21ksoftirqd/319:55:003
2399699629,17cyclictest1370-21awk19:30:130
296232610,5sleep32399999cyclictest21:35:183
2399699618,12cyclictest29326-21date22:40:250
23996996112,11cyclictest9902-21awk00:15:200
23996996111,10cyclictest9942-21grep22:00:220
139291610,1ptp4l391rcuc/322:25:203
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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