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2025-12-29 - 00:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Sun Dec 28, 2025 12:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591232164,23phc2sys0-21swapper/307:08:593
183172227197,20sleep00-21swapper/007:09:590
181802206173,22sleep10-21swapper/107:08:191
179682204172,22sleep20-21swapper/207:05:352
1710821740,4sleep31861499cyclictest10:25:263
68202580,6sleep31861499cyclictest10:05:203
112052570,2sleep10-21swapper/111:20:271
139291510,1ptp4l401ktimersoftd/310:39:203
139291510,1ptp4l401ktimersoftd/309:05:523
1861399505,8cyclictest33-21ksoftirqd/207:20:002
18612995015,4cyclictest25-21ksoftirqd/109:15:001
139291500,39ptp4l0-21swapper/307:10:013
18612994716,4cyclictest25-21ksoftirqd/108:50:001
18613994640,3cyclictest24623-21uname11:50:182
139291460,0ptp4l401ktimersoftd/307:55:293
135291460,1getstats0-21swapper/307:52:183
18613994438,3cyclictest17548-21cron10:30:002
1861399441,3cyclictest33-21ksoftirqd/210:09:592
139291440,0ptp4l401ktimersoftd/310:10:193
139291440,0ptp4l401ktimersoftd/308:25:263
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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