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2026-04-21 - 22:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Tue Apr 21, 2026 12:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
118662206173,22sleep20-21swapper/207:08:292
117232204170,22sleep30-21swapper/307:06:383
98602203170,22sleep00-21swapper/007:05:090
117782202169,22sleep10-21swapper/107:07:201
139291690,1ptp4l401ktimersoftd/308:54:123
12283996723,4cyclictest25-21ksoftirqd/108:25:271
12283996723,4cyclictest25-21ksoftirqd/108:25:271
1395915948,6phc2sys0-21swapper/307:10:013
71022570,2sleep20-21swapper/212:35:162
12283995731,8cyclictest25-21ksoftirqd/109:50:001
139291550,1ptp4l401ktimersoftd/307:15:153
139291540,1ptp4l401ktimersoftd/310:10:183
139291540,1ptp4l401ktimersoftd/308:48:173
227762530,2sleep0111rcuc/008:40:140
12283995218,4cyclictest25-21ksoftirqd/111:50:251
12283995217,3cyclictest25-21ksoftirqd/112:15:181
12283995216,9cyclictest25-21ksoftirqd/111:40:171
12283995115,7cyclictest25-21ksoftirqd/107:45:131
12283995019,9cyclictest25-21ksoftirqd/110:25:251
12283995017,4cyclictest25-21ksoftirqd/112:20:181
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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