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2026-01-02 - 15:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Fri Jan 02, 2026 00:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
168422229162,22sleep00-21swapper/019:06:050
139591221161,48phc2sys0-21swapper/319:09:213
169192207173,23sleep10-21swapper/119:07:031
170662205172,22sleep20-21swapper/219:08:532
3094121380,2sleep01744599cyclictest23:00:130
3094121380,2sleep01744599cyclictest23:00:130
139291650,1ptp4l401ktimersoftd/322:44:073
139291550,1ptp4l401ktimersoftd/300:00:273
139291530,1ptp4l401ktimersoftd/320:40:173
41298520,12rtkit-daemon411-21rtkit-daemon20:33:411
139291430,0ptp4l401ktimersoftd/321:40:203
17448994239,2cyclictest41-21ksoftirqd/321:00:013
17448994239,2cyclictest41-21ksoftirqd/321:00:003
17446994236,3cyclictest28018-21dpkg20:40:001
139291420,0ptp4l401ktimersoftd/323:24:033
139291420,0ptp4l401ktimersoftd/300:05:393
17446994136,3cyclictest25-21ksoftirqd/121:40:001
139291410,0ptp4l401ktimersoftd/323:44:583
139291410,0ptp4l401ktimersoftd/320:50:113
17448994023,6cyclictest41-21ksoftirqd/319:50:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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