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2026-04-28 - 23:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Tue Apr 28, 2026 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2029722770,12sleep220316-21grep07:05:202
1478922690,5sleep014778-21sh07:07:130
251772236168,23sleep10-21swapper/107:08:301
252492234168,22sleep30-21swapper/307:09:203
3078621760,7sleep32559899cyclictest10:40:253
2436021430,3sleep0111rcuc/009:20:180
25597997011,18cyclictest0-21swapper/209:15:132
150302700,3sleep00-21swapper/012:25:000
37112660,7sleep02559599cyclictest12:00:170
25597996612,17cyclictest2801-21sshd09:44:032
25597996510,16cyclictest1327-21sshd08:36:472
2559799649,19cyclictest0-21swapper/209:10:012
25597996410,17cyclictest0-21swapper/212:05:152
25597996410,16cyclictest24868-21cpu08:15:132
25597996312,16cyclictest32454-21cat11:50:252
25597996310,16cyclictest0-21swapper/207:40:172
25598996210,18cyclictest9576-21cat12:10:253
25595996229,4cyclictest9-21ksoftirqd/009:10:010
25597996112,15cyclictest2695-21irqrtprio10:50:202
25597996112,13cyclictest6003-21smartctl09:50:162
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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