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2025-09-15 - 22:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Mon Sep 15, 2025 12:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
137391210177,22phc2sys0-21swapper/307:06:433
223422206173,22sleep20-21swapper/207:08:182
203412204171,22sleep10-21swapper/107:05:091
221732203170,22sleep00-21swapper/007:06:070
137291620,1ptp4l401ktimersoftd/310:50:223
306312590,3sleep030635-21irqrtprio11:55:200
194032520,2sleep10-21swapper/110:25:141
22768994943,4cyclictest23805-21latency_hist08:19:592
139812490,2sleep20-21swapper/211:20:202
1373914533,6phc2sys0-21swapper/307:10:013
137291430,0ptp4l401ktimersoftd/312:39:333
137291420,0ptp4l401ktimersoftd/312:34:073
137291420,0ptp4l401ktimersoftd/308:35:313
137291420,0ptp4l401ktimersoftd/307:55:393
137291410,0ptp4l401ktimersoftd/312:25:183
137291410,0ptp4l401ktimersoftd/308:10:223
22769994035,3cyclictest41-21ksoftirqd/310:15:013
22767994033,5cyclictest25-21ksoftirqd/109:35:001
22766994035,3cyclictest9-21ksoftirqd/009:29:590
22766994034,3cyclictest9-21ksoftirqd/012:30:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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