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2026-04-01 - 15:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Wed Apr 01, 2026 12:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591235169,22phc2sys0-21swapper/307:09:513
183122229168,49sleep10-21swapper/107:07:261
182082205171,22sleep20-21swapper/207:06:072
181892202168,22sleep00-21swapper/007:05:530
1971321510,6sleep01896799cyclictest10:33:040
139291590,1ptp4l401ktimersoftd/312:35:013
237742580,6sleep01896799cyclictest09:34:590
272932540,2sleep327299-21missed_timers07:25:223
139291540,1ptp4l401ktimersoftd/309:40:523
18967994942,4cyclictest217-21systemd-journal11:30:010
135291490,1getstats0-21swapper/311:20:053
1896999481,44cyclictest0-21swapper/212:25:002
135291480,1getstats0-21swapper/311:15:053
18967994642,2cyclictest23617-21sh11:49:590
139291430,1ptp4l401ktimersoftd/308:31:393
18970994237,3cyclictest41-21ksoftirqd/311:00:013
139291420,1ptp4l401ktimersoftd/310:01:363
18970994137,2cyclictest41-21ksoftirqd/311:40:003
1896799414,6cyclictest9-21ksoftirqd/009:09:590
18967994135,3cyclictest22238-21cron10:39:590
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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