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2026-04-25 - 23:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Sat Apr 25, 2026 12:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
176852208174,22sleep00-21swapper/007:07:370
175812207174,22sleep30-21swapper/307:06:153
177032203171,21sleep10-21swapper/107:07:511
175332202168,23sleep20-21swapper/207:05:382
178712134109,14sleep30-21swapper/307:10:013
41298590,2rtkit-daemon0-21swapper/008:45:150
18168995512,41cyclictest461-21kworker/3:112:25:453
18168995512,41cyclictest461-21kworker/3:112:25:443
313052520,1sleep00-21swapper/008:45:020
41298470,2rtkit-daemon0-21swapper/009:00:540
139291430,0ptp4l401ktimersoftd/311:25:183
18168994214,27cyclictest461-21kworker/3:111:01:153
139291420,0ptp4l401ktimersoftd/310:25:273
18168994129,10cyclictest41-21ksoftirqd/309:33:583
18167994126,3cyclictest33-21ksoftirqd/209:05:132
18165994137,3cyclictest9-21ksoftirqd/010:20:010
18165994033,4cyclictest20562-21irqrtprio10:35:180
18168993933,4cyclictest41-21ksoftirqd/310:10:153
18168993926,4cyclictest41-21ksoftirqd/310:20:013
18167993910,27cyclictest0-21swapper/210:50:252
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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