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2026-03-23 - 08:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Mon Mar 23, 2026 00:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
286402234168,23sleep00-21swapper/019:08:540
284702233169,21sleep10-21swapper/119:06:421
139591208173,23phc2sys0-21swapper/319:05:393
285852204170,22sleep20-21swapper/219:08:112
29018996928,3cyclictest25-21ksoftirqd/120:10:161
29018996430,4cyclictest25-21ksoftirqd/100:25:001
29018996430,4cyclictest25-21ksoftirqd/100:25:001
29018996429,7cyclictest25-21ksoftirqd/122:20:011
29017996434,4cyclictest9-21ksoftirqd/000:35:190
29018996332,4cyclictest25-21ksoftirqd/121:15:011
29018996331,4cyclictest25-21ksoftirqd/123:00:001
29017996332,4cyclictest9-21ksoftirqd/019:55:190
29018996231,4cyclictest25-21ksoftirqd/100:25:181
29017996234,3cyclictest9-21ksoftirqd/021:00:280
29017996233,4cyclictest9-21ksoftirqd/022:55:110
29017996233,4cyclictest9-21ksoftirqd/021:20:280
139291620,5ptp4l401ktimersoftd/319:12:333
29018996131,4cyclictest25-21ksoftirqd/121:25:251
29018996130,4cyclictest25-21ksoftirqd/119:25:001
29018996130,3cyclictest25-21ksoftirqd/123:55:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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