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2025-12-06 - 07:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Sat Dec 06, 2025 00:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3065123280,56sleep30-21swapper/319:07:483
2290222260,3sleep122936-21sh19:08:371
1792522030,11sleep00-21swapper/019:05:160
224022201167,23sleep20-21swapper/219:08:362
176342590,3sleep017629-21sort19:10:230
176342590,3sleep017629-21sort19:10:230
133291590,10getstats7401-21ls00:00:223
18632540,2sleep00-21swapper/022:40:280
136591540,1ptp4l401ktimersoftd/322:12:413
103352490,3sleep10-21swapper/119:35:241
2702994619,3cyclictest33-21ksoftirqd/219:10:402
2702994619,3cyclictest33-21ksoftirqd/219:10:402
270099450,2cyclictest1307-21runrttasks00:06:340
2700994412,18cyclictest7257-21seq20:39:140
136591440,0ptp4l401ktimersoftd/300:09:413
270099436,21cyclictest11073-21seq19:39:190
270099426,20cyclictest0-21swapper/019:15:200
136591420,0ptp4l401ktimersoftd/322:08:283
136591420,0ptp4l401ktimersoftd/319:50:073
136591410,0ptp4l401ktimersoftd/322:48:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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