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2026-10-22 - 03:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Thu Oct 22, 2026 00:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591233171,50phc2sys0-21swapper/319:08:103
222152207172,23sleep00-21swapper/019:08:560
221102207173,22sleep20-21swapper/219:07:332
220052204172,21sleep10-21swapper/119:06:111
139291670,1ptp4l401ktimersoftd/320:59:433
139291580,2ptp4l401ktimersoftd/322:41:363
81802540,5sleep32259299cyclictest23:10:133
286072540,1sleep10-21swapper/123:50:271
139291540,1ptp4l401ktimersoftd/320:37:553
139291510,8ptp4l401ktimersoftd/323:37:143
139291510,1ptp4l401ktimersoftd/300:24:313
11412510,2sleep00-21swapper/020:40:140
139291500,1ptp4l401ktimersoftd/321:14:133
22589994336,4cyclictest9021-21ls22:05:000
139291430,0ptp4l401ktimersoftd/321:01:203
139291430,0ptp4l401ktimersoftd/320:42:463
22589994235,4cyclictest29188-21cron23:55:000
139291420,0ptp4l401ktimersoftd/319:39:563
22589994135,3cyclictest1585-21cron00:05:000
139291410,1ptp4l22756-21ls20:15:263
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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