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2026-04-03 - 10:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Fri Apr 03, 2026 00:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
53122233167,21sleep20-21swapper/219:08:442
53122233167,21sleep20-21swapper/219:08:442
139591224195,19phc2sys0-21swapper/319:09:583
139591224195,19phc2sys0-21swapper/319:09:583
53032204170,22sleep00-21swapper/019:08:380
53032204170,22sleep00-21swapper/019:08:380
52342204172,21sleep10-21swapper/119:07:421
52342204172,21sleep10-21swapper/119:07:421
964121430,2sleep0574299cyclictest23:45:250
1777921380,6sleep2574499cyclictest00:05:142
904821190,4sleep0574299cyclictest20:24:550
139291740,1ptp4l401ktimersoftd/300:27:243
139291700,1ptp4l401ktimersoftd/323:53:463
574499685,61cyclictest25758-21kworker/2:119:15:262
139291650,1ptp4l401ktimersoftd/323:12:193
139291650,1ptp4l401ktimersoftd/323:12:193
139291610,1ptp4l401ktimersoftd/322:53:423
574499574,7cyclictest23539-21idleruntime-cro20:55:012
139291570,1ptp4l401ktimersoftd/319:35:193
139291570,1ptp4l401ktimersoftd/319:35:193
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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