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2026-05-18 - 21:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Mon May 18, 2026 12:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
190652234170,53sleep20-21swapper/207:08:462
139591205171,23phc2sys0-21swapper/307:05:333
189142204170,23sleep00-21swapper/007:06:470
188602203170,22sleep10-21swapper/107:06:041
3027021470,5sleep01946299cyclictest09:45:210
1395918763,16phc2sys0-21swapper/307:10:013
139291770,1ptp4l391rcuc/309:00:263
139291690,1ptp4l11255-21needreboot09:05:233
139291680,1ptp4l401ktimersoftd/311:25:183
1946499667,16cyclictest13165-21/usr/sbin/munin09:10:192
27812650,5sleep32770-21turbostat08:50:003
1946499658,11cyclictest25428-21cut11:50:182
1946499658,11cyclictest25428-21cut11:50:182
1946499657,17cyclictest21147-21awk07:10:282
1946499647,17cyclictest0-21swapper/210:50:112
1946499647,16cyclictest1312-21snmpd09:27:572
1946499646,16cyclictest217-21systemd-journal10:18:042
1946499646,16cyclictest1312-21snmpd10:33:092
1946499633,18cyclictest0-21swapper/208:35:002
139291630,1ptp4l401ktimersoftd/310:48:053
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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