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2026-04-28 - 15:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Tue Apr 28, 2026 00:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591208174,22phc2sys0-21swapper/319:08:173
277722207173,22sleep00-21swapper/019:09:040
276762205173,21sleep10-21swapper/119:07:481
277022204170,23sleep20-21swapper/219:08:102
2123521800,4sleep22813899cyclictest23:25:152
2232821270,2sleep00-21swapper/023:25:250
301912600,2sleep20-21swapper/222:35:162
173102590,3sleep2311rcuc/200:25:002
139291580,50ptp4l0-21swapper/319:10:013
139291520,1ptp4l391rcuc/322:33:443
28138994931,16cyclictest33-21ksoftirqd/220:19:102
230652470,3sleep10-21swapper/122:20:191
28136994427,8cyclictest9-21ksoftirqd/019:43:360
139291440,0ptp4l401ktimersoftd/320:20:233
139291440,0ptp4l401ktimersoftd/319:20:283
139291440,0ptp4l401ktimersoftd/319:19:103
139291440,0ptp4l401ktimersoftd/300:25:223
28136994327,3cyclictest9-21ksoftirqd/019:51:590
139291430,0ptp4l401ktimersoftd/323:40:183
139291430,0ptp4l401ktimersoftd/323:40:173
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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