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2026-03-22 - 05:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Sun Mar 22, 2026 00:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1250822370,8sleep00-21swapper/019:05:200
135132213166,36sleep20-21swapper/219:06:592
139591209175,23phc2sys0-21swapper/319:08:083
135172207174,22sleep10-21swapper/119:07:011
106662800,2sleep30-21swapper/300:40:003
278272640,2sleep10-21swapper/123:00:131
139291560,48ptp4l0-21swapper/319:10:013
139291560,48ptp4l0-21swapper/319:10:003
135191490,2getstats0-21swapper/322:00:173
135191480,2getstats0-21swapper/320:35:183
155642460,1sleep30-21swapper/321:25:233
14047994637,6cyclictest18570-21cron19:20:011
135191460,2getstats0-21swapper/322:50:183
41298430,8rtkit-daemon0-21swapper/322:15:083
1404799432,22cyclictest0-21swapper/119:40:001
139291430,0ptp4l401ktimersoftd/323:05:003
1404999421,39cyclictest10240-21ls20:10:003
139291420,0ptp4l401ktimersoftd/320:25:443
139291420,0ptp4l401ktimersoftd/319:21:333
139291400,0ptp4l401ktimersoftd/321:45:143
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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