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2026-05-05 - 13:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Tue May 05, 2026 00:45:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591236169,22phc2sys0-21swapper/319:08:563
108902235169,23sleep20-21swapper/219:08:462
109822206171,23sleep10-21swapper/119:09:581
107002204171,22sleep00-21swapper/019:06:230
1078121510,5sleep01142499cyclictest23:35:240
11424996529,6cyclictest9-21ksoftirqd/019:30:010
11426996216,10cyclictest1991-21kworker/2:219:15:252
11424995824,8cyclictest9-21ksoftirqd/022:00:200
11424995824,5cyclictest9-21ksoftirqd/021:45:250
11424995823,6cyclictest9-21ksoftirqd/023:50:260
11424995822,5cyclictest9-21ksoftirqd/022:15:210
139291570,1ptp4l401ktimersoftd/321:25:293
11424995720,6cyclictest9-21ksoftirqd/000:35:230
11424995622,9cyclictest9-21ksoftirqd/020:15:130
11424995621,5cyclictest9-21ksoftirqd/020:05:110
137362550,1sleep00-21swapper/020:20:200
11424995525,5cyclictest9-21ksoftirqd/023:00:000
139291540,1ptp4l401ktimersoftd/322:31:073
139291540,1ptp4l401ktimersoftd/322:26:093
139291540,1ptp4l401ktimersoftd/300:07:203
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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