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2026-05-28 - 01:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Wed May 27, 2026 12:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
122792235168,22sleep30-21swapper/307:07:443
121332230168,51sleep20-21swapper/207:05:492
123122206172,22sleep00-21swapper/007:08:080
122502205171,22sleep10-21swapper/107:07:221
12759997134,10cyclictest41-21ksoftirqd/310:39:593
12759996831,8cyclictest41-21ksoftirqd/312:30:003
12759996729,9cyclictest41-21ksoftirqd/308:55:003
12759996630,9cyclictest41-21ksoftirqd/312:00:013
12759996629,7cyclictest41-21ksoftirqd/312:35:133
135191650,7getstats1275999cyclictest10:54:203
12759996433,4cyclictest41-21ksoftirqd/311:05:003
12759996432,4cyclictest41-21ksoftirqd/308:45:183
12759996430,9cyclictest41-21ksoftirqd/309:35:003
12759996422,4cyclictest41-21ksoftirqd/308:07:403
12758996415,12cyclictest15807-21kworker/2:210:50:252
1395916333,5phc2sys0-21swapper/307:10:023
12759996325,4cyclictest41-21ksoftirqd/309:50:153
298712620,5sleep09-21ksoftirqd/007:45:150
12759996230,7cyclictest41-21ksoftirqd/310:20:283
12759996230,4cyclictest41-21ksoftirqd/308:20:133
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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