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2026-08-28 - 09:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Fri Aug 28, 2026 00:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591235168,22phc2sys0-21swapper/319:07:453
85732230163,22sleep20-21swapper/219:07:082
87322206173,22sleep00-21swapper/019:09:110
86142206172,22sleep10-21swapper/119:07:391
1167821800,5sleep2908899cyclictest21:30:142
455321700,2sleep0908699cyclictest21:15:150
911621430,4sleep1908799cyclictest22:30:271
268842620,6sleep3908999cyclictest23:10:123
9088995911,10cyclictest33-21ksoftirqd/219:20:002
908799571,10cyclictest14545-21idleruntime-cro22:45:001
311932560,5sleep2908899cyclictest19:55:182
139291550,1ptp4l401ktimersoftd/323:00:173
125822550,3sleep00-21swapper/020:25:010
125822550,3sleep00-21swapper/020:25:010
139291530,1ptp4l391rcuc/321:39:203
139291520,1ptp4l401ktimersoftd/319:10:013
139291520,1ptp4l401ktimersoftd/300:38:123
139291520,1ptp4l401ktimersoftd/300:38:123
908799514,7cyclictest2329-21grep21:10:161
288422500,1sleep30-21swapper/319:50:163
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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