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2026-07-29 - 02:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Tue Jul 28, 2026 12:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
326292208175,23sleep30-21swapper/307:06:223
327522206172,23sleep20-21swapper/207:07:582
327292205172,22sleep10-21swapper/107:07:411
3032203169,22sleep00-21swapper/007:08:130
786995044,3cyclictest11304-21turbostat08:40:000
1395914834,7phc2sys0-21swapper/307:10:013
1395914834,7phc2sys0-21swapper/307:10:013
788994338,3cyclictest7792-21cat07:25:012
139291430,0ptp4l401ktimersoftd/310:30:133
139291430,0ptp4l401ktimersoftd/307:33:323
786994235,4cyclictest9871-21cron09:45:000
789994122,16cyclictest41-21ksoftirqd/309:23:593
788994132,5cyclictest33-21ksoftirqd/209:20:122
139291410,0ptp4l401ktimersoftd/308:22:013
789994022,16cyclictest41-21ksoftirqd/307:19:583
789993934,3cyclictest41-21ksoftirqd/311:53:073
787993930,5cyclictest25-21ksoftirqd/112:25:141
786993933,3cyclictest9-21ksoftirqd/012:34:590
789993832,4cyclictest41-21ksoftirqd/311:07:253
789993821,15cyclictest41-21ksoftirqd/309:25:583
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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