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2025-12-21 - 08:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Sun Dec 21, 2025 00:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
182162230169,50sleep10-21swapper/119:05:461
139591206171,23phc2sys0-21swapper/319:06:343
182822204171,22sleep00-21swapper/019:06:380
182172204170,23sleep20-21swapper/219:05:482
41298900,69rtkit-daemon0-21swapper/019:10:010
183182660,7sleep01884299cyclictest23:35:270
183182660,7sleep01884299cyclictest23:35:270
139291640,8ptp4l401ktimersoftd/321:01:313
301972570,3sleep30-21swapper/321:45:263
299942530,2sleep10-21swapper/121:45:241
151862490,2sleep00-21swapper/023:30:170
139291490,8ptp4l401ktimersoftd/321:43:013
139291490,1ptp4l401ktimersoftd/319:19:053
139291430,0ptp4l401ktimersoftd/323:47:113
139291430,0ptp4l401ktimersoftd/323:21:433
139291430,0ptp4l401ktimersoftd/323:17:373
139291430,0ptp4l401ktimersoftd/322:20:193
139291420,0ptp4l401ktimersoftd/321:50:303
139291420,0ptp4l401ktimersoftd/320:50:433
139291420,0ptp4l401ktimersoftd/319:28:203
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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