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2026-04-21 - 10:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Tue Apr 21, 2026 00:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
236642224166,46sleep10-21swapper/119:07:271
235902213168,32sleep20-21swapper/219:06:362
139591213168,33phc2sys0-21swapper/319:08:083
235252203170,22sleep00-21swapper/019:05:460
650721600,3sleep02415399cyclictest00:07:020
139591148122,14phc2sys0-21swapper/319:10:013
1907121380,1sleep00-21swapper/020:05:190
24155997511,62cyclictest1454-21kworker/2:020:45:242
41298700,2rtkit-daemon411-21rtkit-daemon00:00:141
259202620,6sleep22415599cyclictest23:40:232
2415699584,15cyclictest12998-21cstates23:15:153
139291550,0ptp4l391rcuc/300:25:273
139291510,0ptp4l391rcuc/300:23:493
2415699498,5cyclictest41-21ksoftirqd/319:50:283
2415699450,6cyclictest41-21ksoftirqd/323:05:273
2415599450,43cyclictest0-21swapper/219:50:252
139291440,0ptp4l401ktimersoftd/319:34:303
139291440,0ptp4l401ktimersoftd/319:34:303
2415699436,4cyclictest41-21ksoftirqd/319:23:573
139291430,0ptp4l401ktimersoftd/321:57:403
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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