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2026-04-20 - 07:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Mon Apr 20, 2026 00:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
118702236168,23sleep00-21swapper/019:07:380
99142231168,52sleep10-21swapper/119:05:021
139591230168,50phc2sys0-21swapper/319:06:433
118272204171,22sleep20-21swapper/219:07:042
2106521720,5sleep01234499cyclictest20:35:150
41298920,70rtkit-daemon0-21swapper/119:10:011
139291620,1ptp4l401ktimersoftd/323:39:083
225482590,7sleep01234499cyclictest19:30:160
211862590,2sleep00-21swapper/022:50:170
282402580,8sleep11234599cyclictest21:55:271
139291550,1ptp4l401ktimersoftd/323:00:253
139291520,1ptp4l391rcuc/323:15:163
180642500,2sleep00-21swapper/022:45:010
41298480,11rtkit-daemon0-21swapper/122:23:001
156202480,2sleep30-21swapper/323:45:173
12347994741,4cyclictest7293-21cron21:15:003
152602450,2sleep10-21swapper/120:20:281
139291450,0ptp4l401ktimersoftd/300:39:293
139291440,0ptp4l401ktimersoftd/321:51:173
139291430,0ptp4l401ktimersoftd/323:28:333
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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