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2026-03-19 - 23:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Thu Mar 19, 2026 12:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
263332230169,50sleep30-21swapper/307:09:323
263722228200,19sleep10-21swapper/107:09:591
262772206172,23sleep20-21swapper/207:08:472
260582204171,23sleep00-21swapper/007:05:560
2637428363,11sleep30-21swapper/307:10:013
26668994941,5cyclictest3615-21grep07:30:012
139291440,1ptp4l401ktimersoftd/311:10:263
139291440,1ptp4l401ktimersoftd/311:10:263
139291440,0ptp4l401ktimersoftd/308:50:183
26669994337,3cyclictest41-21ksoftirqd/308:50:013
139291430,0ptp4l401ktimersoftd/309:53:103
26669994136,3cyclictest41-21ksoftirqd/309:00:003
26669994136,3cyclictest41-21ksoftirqd/308:15:003
41298400,2rtkit-daemon0-21swapper/111:59:491
26669994035,3cyclictest41-21ksoftirqd/309:20:013
26666994035,3cyclictest31338-21kernelversion10:40:180
26669993934,3cyclictest41-21ksoftirqd/308:20:013
26668993933,4cyclictest33-21ksoftirqd/211:50:112
26667993932,4cyclictest25-21ksoftirqd/110:58:201
26669993832,4cyclictest41-21ksoftirqd/310:13:173
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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