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2026-04-29 - 12:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Wed Apr 29, 2026 00:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591208175,22phc2sys0-21swapper/319:05:013
267842206173,22sleep20-21swapper/219:08:362
266512205170,23sleep10-21swapper/119:06:501
268862203168,23sleep00-21swapper/019:09:550
1395918561,16phc2sys0-21swapper/319:10:013
27189996428,5cyclictest41-21ksoftirqd/319:19:123
139291620,1ptp4l401ktimersoftd/323:35:153
228572590,4sleep32718999cyclictest22:20:163
324952580,2sleep00-21swapper/021:30:260
139291520,1ptp4l401ktimersoftd/321:05:483
261412510,2sleep20-21swapper/220:10:212
121072510,1sleep10-21swapper/100:10:251
27189995041,3cyclictest41-21ksoftirqd/320:05:153
2718999467,11cyclictest41-21ksoftirqd/319:40:283
27189994617,7cyclictest41-21ksoftirqd/300:15:203
27189994616,4cyclictest41-21ksoftirqd/300:05:003
27189994616,3cyclictest41-21ksoftirqd/323:55:013
27189994615,4cyclictest41-21ksoftirqd/323:05:213
2718999461,3cyclictest121rcu_preempt19:30:183
321892450,1sleep00-21swapper/023:45:250
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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