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2026-03-16 - 05:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Mon Mar 16, 2026 00:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591235168,22phc2sys0-21swapper/319:08:443
61832228168,49sleep10-21swapper/119:06:561
63162205172,22sleep00-21swapper/019:08:380
62982204171,22sleep20-21swapper/219:08:242
1678621790,6sleep0671099cyclictest19:30:170
2436221400,7sleep2671299cyclictest19:45:182
1947021380,7sleep2671299cyclictest21:50:192
234842780,2sleep10-21swapper/100:15:001
671299658,17cyclictest0-21swapper/220:45:272
98822640,2sleep10-21swapper/122:40:011
6712996410,10cyclictest11376-21sed19:20:012
139291630,1ptp4l401ktimersoftd/321:59:113
6712996210,17cyclictest7529-21irqrtprio19:10:182
671299598,16cyclictest12320-21date22:45:002
671299598,10cyclictest0-21swapper/223:15:162
6712995910,17cyclictest32154-21cat21:10:172
671299568,9cyclictest9581-21df_abs23:45:142
671299557,16cyclictest5238-21apt-get22:30:122
671299547,15cyclictest17253-21ls19:30:202
671299546,9cyclictest0-21swapper/219:20:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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