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2025-11-24 - 21:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Mon Nov 24, 2025 12:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
136691214170,33phc2sys0-21swapper/307:09:243
81662208173,24sleep10-21swapper/107:09:161
79382204171,22sleep00-21swapper/007:06:180
60362204170,22sleep20-21swapper/207:05:072
1366918262,11phc2sys0-21swapper/307:10:003
136591740,1ptp4l391rcuc/308:50:143
132822680,2sleep00-21swapper/008:25:210
247652560,1sleep10-21swapper/112:10:281
15532560,2sleep00-21swapper/009:10:140
36362500,3sleep00-21swapper/008:05:230
302512490,1sleep20-21swapper/209:00:212
136591410,0ptp4l401ktimersoftd/312:01:483
136591410,0ptp4l401ktimersoftd/311:42:023
8516994027,10cyclictest33-21ksoftirqd/211:55:152
51698400,2rtkit-daemon515-21rtkit-daemon07:10:161
136591400,1ptp4l401ktimersoftd/311:14:143
136591400,1ptp4l401ktimersoftd/311:04:323
8516993927,10cyclictest33-21ksoftirqd/208:55:242
136591390,0ptp4l401ktimersoftd/311:15:193
8514993829,7cyclictest9-21ksoftirqd/012:01:350
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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