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2025-05-03 - 01:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Fri May 02, 2025 12:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
210512213169,32sleep20-21swapper/207:06:362
211502210176,23sleep30-21swapper/307:07:553
212662207174,22sleep00-21swapper/007:09:230
209562205173,21sleep10-21swapper/107:05:311
3058621480,3sleep12160499cyclictest07:25:281
137291690,1ptp4l21759-21tr07:10:163
53022620,2sleep20-21swapper/207:40:272
79052600,2sleep37897-21turbostat12:20:013
232612560,1sleep20-21swapper/208:20:172
137291560,1ptp4l401ktimersoftd/310:20:283
238642520,2sleep20-21swapper/211:45:132
246312510,4sleep00-21swapper/011:45:190
2160699492,44cyclictest22367-21sh10:35:013
226832450,1sleep00-21swapper/011:40:260
137291450,1ptp4l401ktimersoftd/307:17:223
137291430,0ptp4l401ktimersoftd/310:10:323
137291430,0ptp4l401ktimersoftd/310:05:253
137291430,0ptp4l401ktimersoftd/309:49:423
21606994235,4cyclictest3484-21cron07:39:593
137291420,0ptp4l401ktimersoftd/309:35:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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