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2026-08-25 - 08:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Tue Aug 25, 2026 00:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1254122120,4sleep112539-21od19:06:101
1496822050,4sleep014976-21od19:06:140
139591205172,21phc2sys0-21swapper/319:09:123
62102204170,22sleep20-21swapper/219:06:582
385121640,8sleep3699999cyclictest19:32:513
385121640,8sleep3699999cyclictest19:32:513
2019221610,7sleep2699899cyclictest19:32:302
2019221610,7sleep2699899cyclictest19:32:292
1268721540,3sleep311860-21fstime19:20:183
966221470,2sleep00-21swapper/019:40:200
91242810,3sleep29094-21execl19:12:262
21702740,3sleep3391rcuc/319:25:553
213392720,4sleep121360-21grep19:33:181
213392720,4sleep121360-21grep19:33:181
164352680,5sleep216443-21spawn19:25:382
90832670,3sleep09075-21od19:29:370
29982660,5sleep0111rcuc/019:30:340
29982660,5sleep0111rcuc/019:30:330
107652660,3sleep110769-21sh19:29:101
90332650,3sleep39031-21execl19:11:343
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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