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2026-05-12 - 19:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Tue May 12, 2026 12:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
25382226200,17sleep10-21swapper/107:07:581
25382226200,17sleep10-21swapper/107:07:581
4832208174,22sleep20-21swapper/207:05:022
4832208174,22sleep20-21swapper/207:05:022
23742206172,23sleep00-21swapper/007:06:130
23742206172,23sleep00-21swapper/007:06:130
139591206172,22phc2sys0-21swapper/307:05:453
139591206172,22phc2sys0-21swapper/307:05:453
139591137111,14phc2sys0-21swapper/307:10:013
3067996530,8cyclictest33-21ksoftirqd/210:15:192
39702630,2sleep30-21swapper/311:40:163
3067996222,9cyclictest33-21ksoftirqd/208:25:272
72612580,2sleep00-21swapper/011:45:210
72612580,2sleep00-21swapper/011:45:210
3067995726,6cyclictest33-21ksoftirqd/210:40:142
3067995720,10cyclictest33-21ksoftirqd/211:30:192
3067995626,4cyclictest33-21ksoftirqd/208:50:232
266872550,1sleep10-21swapper/112:25:221
139291550,1ptp4l401ktimersoftd/310:55:243
139291550,1ptp4l401ktimersoftd/307:40:273
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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