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2026-06-07 - 05:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Sat Jun 06, 2026 00:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591240169,60phc2sys0-21swapper/319:07:213
53992213168,33sleep20-21swapper/219:09:382
51242206173,22sleep00-21swapper/019:06:020
51972205173,21sleep10-21swapper/119:07:011
139291880,1ptp4l19114-21ls21:50:213
5722997428,10cyclictest41-21ksoftirqd/323:35:253
5719997022,5cyclictest9-21ksoftirqd/023:35:110
5722996833,9cyclictest41-21ksoftirqd/321:45:003
5719996821,7cyclictest9-21ksoftirqd/022:15:190
5722996733,8cyclictest41-21ksoftirqd/323:05:013
5719996724,5cyclictest9-21ksoftirqd/019:15:270
5722996630,4cyclictest41-21ksoftirqd/319:40:253
5722996531,6cyclictest41-21ksoftirqd/322:40:003
5719996526,5cyclictest9-21ksoftirqd/021:15:160
5719996522,5cyclictest9-21ksoftirqd/019:55:270
5722996432,8cyclictest41-21ksoftirqd/320:10:013
5722996432,7cyclictest41-21ksoftirqd/321:35:003
5722996430,8cyclictest41-21ksoftirqd/320:45:233
5722996429,8cyclictest41-21ksoftirqd/320:10:163
5722996427,8cyclictest41-21ksoftirqd/320:34:593
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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