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2026-01-12 - 09:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Mon Jan 12, 2026 00:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591208174,22phc2sys0-21swapper/319:08:273
72892207173,22sleep10-21swapper/119:08:391
71772204171,22sleep20-21swapper/219:07:122
71182204170,23sleep00-21swapper/019:06:250
2595021730,6sleep0768799cyclictest23:10:150
7690996411,13cyclictest28549-21awk19:50:283
7689996429,4cyclictest33-21ksoftirqd/222:25:252
7689996329,6cyclictest33-21ksoftirqd/220:15:002
7688996323,4cyclictest25-21ksoftirqd/121:15:451
7689996224,6cyclictest33-21ksoftirqd/223:00:122
7689996129,4cyclictest33-21ksoftirqd/223:30:202
7689996126,7cyclictest33-21ksoftirqd/221:30:012
7689996126,4cyclictest33-21ksoftirqd/221:40:002
7689996029,6cyclictest33-21ksoftirqd/223:40:172
7689996029,6cyclictest33-21ksoftirqd/222:55:252
7689996029,6cyclictest33-21ksoftirqd/221:05:122
7689996029,3cyclictest33-21ksoftirqd/200:15:182
7689996028,11cyclictest33-21ksoftirqd/200:00:252
7689996028,11cyclictest33-21ksoftirqd/200:00:252
7689996026,4cyclictest33-21ksoftirqd/219:55:202
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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