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2025-12-11 - 18:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Thu Dec 11, 2025 12:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
136691229164,22phc2sys0-21swapper/307:07:443
59092206173,22sleep10-21swapper/107:09:401
59082206172,23sleep00-21swapper/007:09:380
57232206172,23sleep20-21swapper/207:07:142
2053321670,6sleep2628699cyclictest09:54:592
59382162123,14sleep20-21swapper/207:10:012
128421410,7sleep0628499cyclictest12:35:250
196972690,2sleep30-21swapper/307:35:233
6284996212,17cyclictest4569-21awk08:10:270
166272580,5sleep116629-21irqrtprio09:45:211
133391570,9getstats0-21swapper/312:26:033
133391570,9getstats0-21swapper/312:26:033
628499520,3cyclictest26464-21runrttasks08:58:170
628499510,3cyclictest21371-21seq08:46:210
133391470,1getstats0-21swapper/307:30:593
628499430,3cyclictest11871-21seq08:26:120
51698430,7rtkit-daemon0-21swapper/109:53:511
136591430,0ptp4l401ktimersoftd/309:49:173
136591430,0ptp4l401ktimersoftd/309:09:573
628499425,23cyclictest26981-21seq12:20:440
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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