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2026-07-14 - 00:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Mon Jul 13, 2026 12:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15222236169,22sleep20-21swapper/207:07:472
16492230163,22sleep00-21swapper/007:09:210
139591215182,21phc2sys0-21swapper/307:06:273
14492203170,22sleep10-21swapper/107:06:541
2685421600,3sleep1200199cyclictest10:15:201
670821560,4sleep3200399cyclictest08:25:233
170329161,22sleep20-21swapper/207:10:012
308392710,2sleep20-21swapper/210:25:002
10662620,1sleep20-21swapper/208:15:182
139291590,1ptp4l401ktimersoftd/309:29:413
1395915335,9phc2sys0-21swapper/307:10:013
139291530,1ptp4l401ktimersoftd/312:32:423
2002995144,4cyclictest14103-21sh09:50:002
42022500,4sleep125-21ksoftirqd/107:15:001
63062460,2sleep00-21swapper/008:25:190
200299450,3cyclictest22129-21kworker/2:110:10:262
2000994527,15cyclictest9-21ksoftirqd/010:04:310
2000994410,21cyclictest19576-21seq08:51:380
139291430,0ptp4l401ktimersoftd/307:52:173
139291420,0ptp4l401ktimersoftd/308:55:453
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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