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2026-08-10 - 04:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Mon Aug 10, 2026 00:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591233170,21phc2sys0-21swapper/319:06:433
323072205171,23sleep10-21swapper/119:08:071
321292205172,22sleep20-21swapper/219:05:462
322542204170,22sleep00-21swapper/019:07:240
233521780,5sleep03274699cyclictest22:35:210
300321460,8sleep33274999cyclictest20:20:243
1395918460,15phc2sys0-21swapper/319:10:023
139291630,1ptp4l401ktimersoftd/321:52:323
139291570,1ptp4l401ktimersoftd/323:57:113
139291560,1ptp4l401ktimersoftd/300:25:003
3274799521,3cyclictest26085-21ls20:00:361
202212490,2sleep10-21swapper/119:50:181
122002490,2sleep00-21swapper/019:35:010
32749994438,4cyclictest20070-21cron23:15:003
32749994231,9cyclictest41-21ksoftirqd/323:20:163
32749994231,9cyclictest41-21ksoftirqd/323:20:163
32747994235,4cyclictest25-21ksoftirqd/123:00:011
3274699421,39cyclictest2159-21ls23:45:000
139291420,0ptp4l401ktimersoftd/320:26:073
139291420,0ptp4l401ktimersoftd/319:30:183
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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