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2026-10-01 - 01:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Wed Sep 30, 2026 12:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591231169,50phc2sys0-21swapper/307:07:413
75922211177,23sleep20-21swapper/207:09:292
76072205172,22sleep00-21swapper/007:09:400
74562204172,22sleep10-21swapper/107:07:471
246832770,2sleep20-21swapper/208:50:262
792899615,53cyclictest0-21swapper/112:15:251
792899601,56cyclictest0-21swapper/108:55:251
302962580,2sleep00-21swapper/011:15:240
792899571,54cyclictest0-21swapper/109:10:261
139291570,1ptp4l401ktimersoftd/310:05:093
792899560,12cyclictest26166-21latency_hist11:10:001
139291530,0ptp4l401ktimersoftd/310:40:133
792899521,15cyclictest6660-21apt-get10:30:101
792899521,15cyclictest6660-21apt-get10:30:101
792899520,10cyclictest0-21swapper/107:35:001
792899511,18cyclictest27977-21ls11:10:241
792899511,15cyclictest32198-21ls11:20:241
135752500,2sleep30-21swapper/311:50:133
176892490,2sleep30-21swapper/309:45:163
139291490,0ptp4l401ktimersoftd/307:12:453
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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