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2025-12-17 - 09:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Wed Dec 17, 2025 00:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
44172236169,22sleep30-21swapper/319:06:093
45072204171,22sleep10-21swapper/119:07:201
45082203170,22sleep20-21swapper/219:07:222
44122202169,22sleep00-21swapper/019:06:070
5004996932,8cyclictest33-21ksoftirqd/221:00:002
139291690,1ptp4l401ktimersoftd/319:56:173
139291670,1ptp4l401ktimersoftd/300:33:413
5004996528,6cyclictest33-21ksoftirqd/200:25:152
5004996522,4cyclictest33-21ksoftirqd/220:35:252
5004996429,10cyclictest33-21ksoftirqd/221:50:002
139291640,1ptp4l401ktimersoftd/322:25:283
5004996229,5cyclictest33-21ksoftirqd/219:55:252
5004996227,10cyclictest33-21ksoftirqd/220:05:002
5004996129,9cyclictest33-21ksoftirqd/222:30:142
5004996129,6cyclictest33-21ksoftirqd/221:35:152
5004996128,5cyclictest33-21ksoftirqd/200:15:172
5004996128,3cyclictest33-21ksoftirqd/219:10:252
5004996120,6cyclictest33-21ksoftirqd/221:05:142
5004996029,5cyclictest33-21ksoftirqd/223:55:142
5004996029,5cyclictest33-21ksoftirqd/222:30:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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