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2026-03-21 - 00:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Fri Mar 20, 2026 12:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
249762232171,49sleep00-21swapper/007:05:530
139591230167,51phc2sys0-21swapper/307:09:483
250502207173,23sleep20-21swapper/207:06:512
252672205173,21sleep10-21swapper/107:09:361
1392911090,1ptp4l20885-21ptp4l10:20:233
2559399660,3cyclictest12309-21cpuspeed_turbos12:20:121
25594996433,7cyclictest33-21ksoftirqd/208:19:592
25594996429,9cyclictest33-21ksoftirqd/207:20:002
25594996429,6cyclictest33-21ksoftirqd/212:35:002
25592996429,5cyclictest9-21ksoftirqd/007:30:010
25592996330,6cyclictest9-21ksoftirqd/011:05:180
25592996329,3cyclictest9-21ksoftirqd/009:19:590
25592996328,6cyclictest9-21ksoftirqd/009:05:150
25594996226,6cyclictest33-21ksoftirqd/210:45:002
25594996226,5cyclictest33-21ksoftirqd/208:15:002
25592996224,4cyclictest9-21ksoftirqd/009:45:210
25594996132,7cyclictest33-21ksoftirqd/207:44:592
25594996124,8cyclictest33-21ksoftirqd/210:00:262
25594996124,6cyclictest33-21ksoftirqd/207:30:152
25593996115,15cyclictest29384-21df_abs10:40:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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