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2026-09-24 - 20:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Thu Sep 24, 2026 12:46:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
175472233169,52sleep30-21swapper/307:06:293
176622225197,18sleep00-21swapper/007:07:590
178042206171,23sleep20-21swapper/207:09:452
177452205172,22sleep10-21swapper/107:09:041
1782628663,15sleep10-21swapper/107:10:021
135191850,1getstats0-21swapper/310:35:483
1811799602,10cyclictest6635-21latency_hist09:00:000
1811799602,10cyclictest6635-21latency_hist09:00:000
135191580,2getstats0-21swapper/307:10:283
1811799577,7cyclictest29553-21expr08:40:110
1811799577,7cyclictest14901-21cut09:15:190
1811799551,10cyclictest12134-21latency_hist08:05:010
1811799542,10cyclictest19852-21awk07:10:280
18118995316,5cyclictest25-21ksoftirqd/109:00:001
18118995316,5cyclictest25-21ksoftirqd/109:00:001
1811799536,5cyclictest29890-21latency_hist10:55:000
1811799532,10cyclictest15080-21cat12:40:010
1811799530,11cyclictest9931-21date08:00:000
1811799530,11cyclictest9931-21date08:00:000
126582530,1sleep30-21swapper/312:35:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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