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2026-09-21 - 16:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Mon Sep 21, 2026 12:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
45702210175,23sleep10-21swapper/107:07:271
46762209169,21sleep30-21swapper/307:08:493
46932204170,22sleep00-21swapper/007:09:020
45092204171,22sleep20-21swapper/207:06:402
3047321430,6sleep1506799cyclictest09:05:291
2767821320,4sleep2506899cyclictest07:55:172
5067996321,9cyclictest25-21ksoftirqd/110:10:191
257072610,3sleep10-21swapper/107:50:191
506799558,11cyclictest25-21ksoftirqd/108:10:161
5069995448,3cyclictest6863-21wc08:19:593
5066995321,4cyclictest9-21ksoftirqd/010:25:180
5066995321,4cyclictest9-21ksoftirqd/010:25:180
83882490,2sleep20-21swapper/210:35:242
506799486,9cyclictest25-21ksoftirqd/108:50:141
5067994813,11cyclictest25-21ksoftirqd/109:05:011
506799480,3cyclictest121rcu_preempt09:40:001
5069994731,13cyclictest41-21ksoftirqd/307:11:133
5067994610,5cyclictest25-21ksoftirqd/110:20:261
5067994437,4cyclictest25-21ksoftirqd/110:55:001
506799439,10cyclictest25-21ksoftirqd/110:35:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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