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2026-08-13 - 07:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Thu Aug 13, 2026 00:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
280442237170,22sleep10-21swapper/119:08:481
281182235169,22sleep30-21swapper/319:09:463
260102206173,22sleep20-21swapper/219:05:082
279862202169,21sleep00-21swapper/019:08:030
407121590,4sleep12843799cyclictest23:55:231
1449821460,7sleep02843699cyclictest22:00:480
2843899717,62cyclictest19883-21kworker/2:220:25:252
104832580,2sleep30-21swapper/300:10:133
139291560,1ptp4l401ktimersoftd/323:38:313
139291550,1ptp4l401ktimersoftd/319:22:563
2843899536,45cyclictest11221-21kworker/2:223:20:252
160122530,2sleep30-21swapper/300:20:203
160122530,2sleep30-21swapper/300:20:203
139291490,1ptp4l401ktimersoftd/323:01:043
28438994728,16cyclictest33-21ksoftirqd/223:05:002
2843799471,43cyclictest2951-21cron21:40:001
139291460,1ptp4l0-21swapper/321:45:293
139291460,1ptp4l0-21swapper/321:45:293
41298450,1rtkit-daemon0-21swapper/121:03:061
139291450,0ptp4l401ktimersoftd/319:35:023
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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