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2026-07-07 - 20:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Tue Jul 07, 2026 12:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591213169,32phc2sys0-21swapper/307:09:303
211532207174,22sleep20-21swapper/207:08:102
211462204171,21sleep00-21swapper/007:08:040
191182204169,23sleep10-21swapper/107:05:081
85662740,2sleep20-21swapper/212:15:232
21598996631,8cyclictest41-21ksoftirqd/310:35:003
21598996431,7cyclictest41-21ksoftirqd/307:20:003
21598996323,4cyclictest41-21ksoftirqd/311:55:193
269042620,2sleep10-21swapper/107:20:161
21598996227,7cyclictest41-21ksoftirqd/311:45:213
21598996227,7cyclictest41-21ksoftirqd/311:45:213
21598996224,4cyclictest41-21ksoftirqd/308:15:153
21598996223,7cyclictest41-21ksoftirqd/311:50:133
21598996223,7cyclictest41-21ksoftirqd/311:50:133
21598996130,8cyclictest41-21ksoftirqd/307:49:213
21598996130,4cyclictest41-21ksoftirqd/310:20:003
21598996130,4cyclictest41-21ksoftirqd/310:20:003
21598996130,4cyclictest41-21ksoftirqd/309:30:283
21598996127,8cyclictest41-21ksoftirqd/312:30:153
21598996126,7cyclictest41-21ksoftirqd/307:55:133
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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