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2026-03-16 - 01:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Sun Mar 15, 2026 12:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
212922228161,22sleep10-21swapper/107:09:121
212762211165,35sleep00-21swapper/007:08:580
212792206173,22sleep30-21swapper/307:09:023
212412206171,23sleep20-21swapper/207:08:332
139591147121,14phc2sys0-21swapper/307:10:013
2616221400,7sleep02164699cyclictest10:40:160
1392911380,1ptp4l29478-21/usr/sbin/munin11:55:173
2135528763,15sleep10-21swapper/107:10:011
21649996332,8cyclictest41-21ksoftirqd/310:10:003
21649996126,8cyclictest41-21ksoftirqd/310:45:003
21649996025,7cyclictest41-21ksoftirqd/309:15:253
21649995824,6cyclictest41-21ksoftirqd/310:20:253
21649995823,7cyclictest41-21ksoftirqd/309:00:003
21649995725,7cyclictest41-21ksoftirqd/312:10:143
21649995526,7cyclictest41-21ksoftirqd/310:20:013
21649995522,8cyclictest41-21ksoftirqd/310:35:133
21649995521,8cyclictest41-21ksoftirqd/308:48:193
21649995521,7cyclictest41-21ksoftirqd/307:30:193
21649995428,11cyclictest41-21ksoftirqd/308:50:193
21649995222,6cyclictest41-21ksoftirqd/310:50:213
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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