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2025-12-18 - 18:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Thu Dec 18, 2025 12:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
117162211170,29sleep00-21swapper/007:05:520
139591205171,22phc2sys0-21swapper/307:05:063
117022205173,21sleep10-21swapper/107:05:411
117452203170,22sleep20-21swapper/207:06:152
386221760,7sleep31232999cyclictest09:05:183
1367821220,2sleep30-21swapper/311:40:223
412981030,68rtkit-daemon0-21swapper/307:10:013
12327997423,7cyclictest25-21ksoftirqd/107:20:001
12327996632,3cyclictest25-21ksoftirqd/109:55:011
12327996332,3cyclictest25-21ksoftirqd/109:20:161
12326996328,7cyclictest9-21ksoftirqd/008:50:000
12327996228,3cyclictest25-21ksoftirqd/112:30:121
12327996228,3cyclictest25-21ksoftirqd/108:40:001
12327996129,4cyclictest25-21ksoftirqd/110:00:171
12327996025,4cyclictest25-21ksoftirqd/111:00:141
12326996029,3cyclictest9-21ksoftirqd/012:10:170
12327995929,4cyclictest25-21ksoftirqd/110:45:171
12327995921,10cyclictest25-21ksoftirqd/107:35:001
1232999587,7cyclictest7252-21head11:25:283
12327995829,4cyclictest25-21ksoftirqd/109:45:151
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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