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2025-12-23 - 10:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Tue Dec 23, 2025 00:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591209175,23phc2sys0-21swapper/319:05:103
259482208175,22sleep20-21swapper/219:05:332
262312204171,22sleep00-21swapper/019:09:090
261052202170,21sleep10-21swapper/119:07:291
139291670,1ptp4l401ktimersoftd/321:40:273
139291660,1ptp4l401ktimersoftd/300:07:333
176612640,2sleep017662-21ps23:20:210
139291560,1ptp4l401ktimersoftd/319:38:043
139291510,0ptp4l401ktimersoftd/321:57:213
139291500,0ptp4l401ktimersoftd/322:00:183
26592994633,10cyclictest25-21ksoftirqd/119:15:181
26592994633,10cyclictest25-21ksoftirqd/119:15:181
26591994533,9cyclictest9-21ksoftirqd/023:20:000
2659199442,39cyclictest8548-21cron00:10:010
139291440,0ptp4l401ktimersoftd/320:00:113
26593994338,3cyclictest22979-21wc22:25:152
26594994231,9cyclictest41-21ksoftirqd/323:25:113
139291420,0ptp4l401ktimersoftd/320:05:313
26593994136,3cyclictest8428-21turbostat21:54:592
26592994136,3cyclictest25-21ksoftirqd/123:00:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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