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2026-04-04 - 00:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Fri Apr 03, 2026 12:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591231169,50phc2sys0-21swapper/307:06:323
40312208173,23sleep10-21swapper/107:09:121
38102206172,22sleep00-21swapper/007:06:280
37872203168,23sleep20-21swapper/207:06:102
1181621510,3sleep10-21swapper/108:30:271
438799689,17cyclictest433-21polkitd08:50:241
300142640,2sleep10-21swapper/111:25:011
438799638,16cyclictest6125-21awk09:25:221
438799616,16cyclictest0-21swapper/112:20:181
46632580,1sleep20-21swapper/210:30:212
139291580,1ptp4l401ktimersoftd/308:20:263
438799563,51cyclictest0-21swapper/111:26:461
438799549,16cyclictest11777-21latency_hist11:55:001
438799549,16cyclictest11777-21latency_hist11:55:001
4389995246,4cyclictest12620-21date10:50:003
438799529,9cyclictest18066-21ps12:05:231
438799529,16cyclictest17417-21/usr/sbin/munin08:45:201
4387995211,8cyclictest7926-21interrupts11:45:161
4387995210,9cyclictest15834-21iostat10:55:171
4387995111,8cyclictest19506-21hddtemp_smartct09:55:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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