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2026-07-20 - 01:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Sun Jul 19, 2026 12:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591208174,22phc2sys0-21swapper/307:07:263
167632206173,21sleep10-21swapper/107:09:481
164472205171,23sleep20-21swapper/207:05:472
164402204171,22sleep00-21swapper/007:05:410
2094821580,6sleep21707299cyclictest07:15:272
17071997629,8cyclictest25-21ksoftirqd/111:35:131
17071996622,9cyclictest25-21ksoftirqd/107:45:211
17071996529,7cyclictest25-21ksoftirqd/111:40:131
17071996528,9cyclictest25-21ksoftirqd/109:45:001
17070996430,6cyclictest9-21ksoftirqd/012:00:130
17071996328,8cyclictest25-21ksoftirqd/108:30:271
17071996328,7cyclictest25-21ksoftirqd/108:45:171
17071996328,6cyclictest25-21ksoftirqd/112:15:221
17071996328,5cyclictest25-21ksoftirqd/109:05:001
145272630,1sleep00-21swapper/009:20:000
17071996227,5cyclictest25-21ksoftirqd/110:55:161
17071996226,6cyclictest25-21ksoftirqd/111:30:201
17071996223,6cyclictest25-21ksoftirqd/111:55:161
17071996222,7cyclictest25-21ksoftirqd/108:05:291
17071996127,7cyclictest25-21ksoftirqd/107:30:181
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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