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2026-07-04 - 20:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Sat Jul 04, 2026 12:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7762238171,22sleep20-21swapper/207:05:042
28522235167,22sleep00-21swapper/007:07:360
29812229162,22sleep30-21swapper/307:09:163
28182209175,22sleep10-21swapper/107:07:091
1496821680,5sleep2334099cyclictest09:45:282
30472147122,14sleep00-21swapper/007:10:010
3341996630,7cyclictest41-21ksoftirqd/308:15:153
3341996630,4cyclictest41-21ksoftirqd/310:50:003
3341996627,4cyclictest41-21ksoftirqd/311:55:003
3341996533,6cyclictest41-21ksoftirqd/309:04:593
3341996532,8cyclictest41-21ksoftirqd/311:00:143
3341996531,8cyclictest41-21ksoftirqd/308:50:173
3341996531,7cyclictest41-21ksoftirqd/308:05:253
3341996527,10cyclictest41-21ksoftirqd/312:05:193
3341996525,8cyclictest41-21ksoftirqd/312:15:133
3341996428,9cyclictest41-21ksoftirqd/309:55:163
3341996428,7cyclictest41-21ksoftirqd/308:45:143
3341996428,5cyclictest41-21ksoftirqd/307:15:173
3341996427,7cyclictest41-21ksoftirqd/312:35:243
3341996424,7cyclictest41-21ksoftirqd/308:20:263
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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