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2025-11-15 - 00:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Fri Nov 14, 2025 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
136691233166,23phc2sys0-21swapper/307:05:563
18252208163,33sleep20-21swapper/207:06:202
18792207162,35sleep10-21swapper/107:06:591
20922204171,22sleep00-21swapper/007:09:350
168972570,4sleep0246699cyclictest09:55:030
2469995628,8cyclictest41-21ksoftirqd/307:20:243
2466995626,10cyclictest9-21ksoftirqd/007:20:190
2466995619,5cyclictest9-21ksoftirqd/012:00:280
2469995519,8cyclictest41-21ksoftirqd/308:19:053
2466995525,10cyclictest9-21ksoftirqd/007:35:160
2466995523,7cyclictest9-21ksoftirqd/009:25:250
2466995523,6cyclictest9-21ksoftirqd/011:40:010
268722540,1sleep00-21swapper/011:20:280
2469995424,9cyclictest41-21ksoftirqd/308:40:013
2469995421,4cyclictest41-21ksoftirqd/307:40:163
2466995425,6cyclictest9-21ksoftirqd/008:30:230
2466995424,8cyclictest9-21ksoftirqd/007:50:140
2466995423,6cyclictest9-21ksoftirqd/012:30:140
2469995323,9cyclictest41-21ksoftirqd/310:05:153
2469995322,8cyclictest41-21ksoftirqd/310:00:263
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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