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2026-05-21 - 22:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Thu May 21, 2026 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591209176,22phc2sys0-21swapper/307:08:283
215072205170,23sleep10-21swapper/107:06:471
215632204170,22sleep00-21swapper/007:07:310
217202203169,23sleep20-21swapper/207:09:342
1395918262,11phc2sys0-21swapper/307:10:013
22053996720,3cyclictest9-21ksoftirqd/009:35:000
277482590,2sleep30-21swapper/309:35:173
22056995626,3cyclictest41-21ksoftirqd/309:15:253
22056995624,6cyclictest41-21ksoftirqd/310:30:003
22053995624,7cyclictest9-21ksoftirqd/009:55:140
17282560,4sleep22205599cyclictest08:40:232
197462550,3sleep10-21swapper/110:25:211
22056995320,4cyclictest41-21ksoftirqd/312:25:013
22056995223,7cyclictest41-21ksoftirqd/308:25:183
22056995222,8cyclictest41-21ksoftirqd/307:55:253
22056995221,4cyclictest41-21ksoftirqd/307:52:373
22056995215,7cyclictest41-21ksoftirqd/310:50:243
22053995219,3cyclictest9-21ksoftirqd/010:00:280
22056995124,6cyclictest41-21ksoftirqd/307:20:223
22056995119,7cyclictest41-21ksoftirqd/312:05:263
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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