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2026-06-04 - 04:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Thu Jun 04, 2026 00:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591207172,23phc2sys0-21swapper/319:05:493
155082206173,22sleep10-21swapper/119:07:081
155322205171,22sleep00-21swapper/019:07:270
154282203169,22sleep20-21swapper/219:06:082
157322148122,14sleep10-21swapper/119:10:011
1395916734,6phc2sys0-21swapper/319:10:013
16026995926,3cyclictest25-21ksoftirqd/122:25:001
16026995726,3cyclictest25-21ksoftirqd/123:45:121
139291560,1ptp4l401ktimersoftd/322:44:503
16026995524,6cyclictest25-21ksoftirqd/100:40:001
139291550,1ptp4l401ktimersoftd/322:39:323
16026995215,8cyclictest25-21ksoftirqd/120:00:171
139291520,1ptp4l401ktimersoftd/322:28:513
1602699519,7cyclictest25-21ksoftirqd/120:50:201
1602699519,7cyclictest25-21ksoftirqd/120:50:201
16026995120,6cyclictest25-21ksoftirqd/122:25:211
139291510,1ptp4l401ktimersoftd/321:43:013
1602699509,7cyclictest25-21ksoftirqd/123:05:211
16026995022,6cyclictest25-21ksoftirqd/121:00:151
16026995022,6cyclictest25-21ksoftirqd/120:45:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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