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2026-01-11 - 15:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Sun Jan 11, 2026 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591213185,18phc2sys0-21swapper/307:09:593
49372212168,32sleep20-21swapper/207:07:312
48692205171,22sleep10-21swapper/107:06:391
49032203170,22sleep00-21swapper/007:07:050
78912640,1sleep00-21swapper/007:15:150
5430996427,8cyclictest33-21ksoftirqd/207:15:272
5429996412,27cyclictest19558-21cat07:39:591
188912630,6sleep2543099cyclictest07:35:322
5430995924,4cyclictest33-21ksoftirqd/212:20:202
542999590,26cyclictest31245-21runrttasks10:19:481
5428995917,5cyclictest9-21ksoftirqd/007:30:240
5430995422,4cyclictest33-21ksoftirqd/207:25:142
543199531,9cyclictest16801-21chrt09:48:063
543099536,9cyclictest33-21ksoftirqd/211:00:152
543099534,9cyclictest33-21ksoftirqd/209:25:182
542899533,6cyclictest5480-21mailstats08:15:260
543199520,9cyclictest3499-21chrt10:27:383
543199520,9cyclictest3499-21chrt10:27:383
5430995216,3cyclictest33-21ksoftirqd/208:40:212
543199511,9cyclictest32363-21chrt09:11:293
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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