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2026-07-17 - 01:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Thu Jul 16, 2026 12:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
189352236169,22sleep10-21swapper/107:07:351
139591234170,52phc2sys0-21swapper/307:08:343
188532215180,23sleep20-21swapper/207:06:312
190782204170,22sleep00-21swapper/007:09:260
139591135110,14phc2sys0-21swapper/307:10:003
245142830,5sleep125-21ksoftirqd/111:50:121
19417996330,7cyclictest25-21ksoftirqd/112:25:181
19417996327,8cyclictest25-21ksoftirqd/109:30:271
19417996327,7cyclictest25-21ksoftirqd/109:15:241
139291630,1ptp4l401ktimersoftd/312:31:373
19417996230,7cyclictest25-21ksoftirqd/108:15:171
19417996126,7cyclictest25-21ksoftirqd/112:10:181
19417996126,7cyclictest25-21ksoftirqd/112:10:181
19417996126,7cyclictest25-21ksoftirqd/109:20:151
19417996125,7cyclictest25-21ksoftirqd/109:00:271
19417996124,5cyclictest25-21ksoftirqd/110:55:181
139291610,0ptp4l401ktimersoftd/312:16:193
19417996027,7cyclictest25-21ksoftirqd/108:40:201
19417995929,4cyclictest25-21ksoftirqd/107:10:191
19417995927,6cyclictest25-21ksoftirqd/107:35:191
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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