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2025-06-28 - 23:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Sat Jun 28, 2025 12:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
137391235171,22phc2sys0-21swapper/307:08:533
236492207174,22sleep10-21swapper/107:06:191
236502206172,23sleep20-21swapper/207:06:212
237402203171,22sleep00-21swapper/007:07:320
2543921700,7sleep22422699cyclictest11:40:242
137391153127,14phc2sys0-21swapper/307:10:003
1476821410,3sleep22422699cyclictest07:55:232
2422599646,10cyclictest20719-21latency_hist08:10:011
194542640,2sleep30-21swapper/310:20:273
137291640,1ptp4l401ktimersoftd/311:20:173
2422599634,18cyclictest13927-21grep07:55:141
2422599625,11cyclictest13587-21cpuspeed_turbos12:25:181
2422599622,11cyclictest17932-21awk12:35:001
18062620,4sleep09-21ksoftirqd/012:00:200
2422599615,10cyclictest6355-21tail11:00:301
2422599603,11cyclictest621-21grep07:25:291
2422599601,11cyclictest218-21systemd-journal10:05:001
2422599594,11cyclictest6669-21if_err_enp1s012:10:201
2422599591,16cyclictest0-21swapper/108:45:131
2422599591,11cyclictest16929-21cut08:00:221
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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