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2026-03-06 - 22:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Fri Mar 06, 2026 12:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591207175,21phc2sys0-21swapper/307:07:233
122492204170,22sleep20-21swapper/207:05:362
122802203168,23sleep10-21swapper/107:05:591
104632203168,23sleep00-21swapper/007:05:060
41298900,68rtkit-daemon0-21swapper/207:10:012
289972830,7sleep31289299cyclictest11:05:193
12889996115,22cyclictest28693-21fschecks_time11:05:160
8752590,2sleep20-21swapper/210:05:242
139291590,5ptp4l1289299cyclictest09:15:213
12022570,5sleep01198-21unixbench_multi07:50:270
143012540,2sleep20-21swapper/209:25:252
1288999530,2cyclictest0-21swapper/010:16:400
139291490,41ptp4l0-21swapper/307:10:013
48432480,2sleep30-21swapper/309:05:283
12891994842,3cyclictest312-21rs:main2
12889994612,20cyclictest15966-21seq08:22:040
139291450,1ptp4l401ktimersoftd/307:33:153
12892994539,3cyclictest24227-21tr08:40:173
12892994426,15cyclictest41-21ksoftirqd/310:15:103
12891994426,16cyclictest30359-21cron11:10:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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