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2026-04-27 - 15:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Mon Apr 27, 2026 12:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
114462232168,22sleep10-21swapper/107:08:161
139591206173,22phc2sys0-21swapper/307:05:483
115802204171,22sleep00-21swapper/007:09:560
113252204171,22sleep20-21swapper/207:06:442
139291700,48ptp4l0-21swapper/307:10:013
139291680,1ptp4l401ktimersoftd/309:10:103
139291610,1ptp4l401ktimersoftd/307:45:163
11882995827,3cyclictest9-21ksoftirqd/007:40:130
11882995825,7cyclictest9-21ksoftirqd/012:35:160
11883995723,4cyclictest25-21ksoftirqd/109:04:591
11882995627,3cyclictest9-21ksoftirqd/008:30:180
122622550,1sleep00-21swapper/011:40:120
11882995526,3cyclictest9-21ksoftirqd/011:15:150
11882995525,3cyclictest9-21ksoftirqd/009:20:270
11883995424,3cyclictest25-21ksoftirqd/111:50:001
11882995427,6cyclictest9-21ksoftirqd/010:02:400
71412530,3sleep2311rcuc/211:30:002
177722530,1sleep00-21swapper/010:45:120
11883995315,9cyclictest25-21ksoftirqd/111:20:161
228612490,1sleep20-21swapper/208:40:152
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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