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2026-10-10 - 01:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot2.osadl.org (updated Fri Oct 09, 2026 12:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
221332242175,22sleep20-21swapper/207:08:242
220942222193,19sleep10-21swapper/107:07:581
139591208174,23phc2sys0-21swapper/307:09:043
220932205171,22sleep00-21swapper/007:07:580
2225928363,11sleep20-21swapper/207:10:012
320422620,2sleep10-21swapper/109:45:001
243182540,3sleep10-21swapper/111:40:261
99912490,2sleep10-21swapper/111:10:251
2255199492,43cyclictest217-21systemd-journal08:15:000
179132480,2sleep20-21swapper/209:15:002
139291480,0ptp4l401ktimersoftd/310:57:073
22554994713,8cyclictest41-21ksoftirqd/307:35:203
2255299472,42cyclictest1818-21sshd12:04:151
2255199442,3cyclictest121rcu_preempt08:05:170
139291440,0ptp4l401ktimersoftd/311:40:223
139291430,0ptp4l401ktimersoftd/310:51:583
139291430,0ptp4l401ktimersoftd/310:10:033
2255199425,3cyclictest121rcu_preempt11:05:150
2255199425,2cyclictest121rcu_preempt09:25:200
139291420,0ptp4l401ktimersoftd/307:55:553
22554994131,5cyclictest41-21ksoftirqd/310:03:563
22552994136,3cyclictest25-21ksoftirqd/110:20:001
2255199414,2cyclictest121rcu_preempt09:50:010
2255199412,3cyclictest9-21ksoftirqd/008:39:590
22554994036,2cyclictest41-21ksoftirqd/308:55:003
22554994036,2cyclictest41-21ksoftirqd/308:55:003
22554994032,5cyclictest41-21ksoftirqd/311:30:103
22554994014,5cyclictest41-21ksoftirqd/311:20:183
22553994034,3cyclictest21097-21cron08:15:002
22552994035,3cyclictest25-21ksoftirqd/110:10:001
2255199406,3cyclictest9-21ksoftirqd/008:55:010
2255199406,3cyclictest9-21ksoftirqd/008:55:010
22551994035,2cyclictest9-21ksoftirqd/008:30:000
2255199400,3cyclictest121rcu_preempt11:55:250
22554993934,3cyclictest41-21ksoftirqd/310:30:003
22554993934,3cyclictest41-21ksoftirqd/310:00:003
22554993933,4cyclictest41-21ksoftirqd/312:24:163
22554993933,3cyclictest41-21ksoftirqd/308:45:003
22553993933,4cyclictest33-21ksoftirqd/209:32:572
22552993933,3cyclictest25-21ksoftirqd/108:50:001
22552993932,4cyclictest25-21ksoftirqd/109:20:011
22551993935,2cyclictest9-21ksoftirqd/011:55:000
2255199393,3cyclictest121rcu_preempt11:25:190
22554993832,3cyclictest41-21ksoftirqd/308:40:003
22554993831,4cyclictest41-21ksoftirqd/312:15:383
22554993831,4cyclictest41-21ksoftirqd/308:47:433
22552993834,2cyclictest25-21ksoftirqd/110:40:011
22552993833,3cyclictest25-21ksoftirqd/110:25:001
22552993832,4cyclictest25-21ksoftirqd/110:40:201
22552993832,3cyclictest25-21ksoftirqd/112:15:181
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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