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2026-04-12 - 07:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot2.osadl.org (updated Sun Apr 12, 2026 00:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139591237175,50phc2sys0-21swapper/319:05:073
258752221194,18sleep20-21swapper/219:09:582
258742207172,23sleep10-21swapper/119:09:571
256522204170,22sleep00-21swapper/019:07:070
269721370,5sleep32617199cyclictest21:40:263
219802550,3sleep321983-21irqrtprio23:30:183
66792520,3sleep30-21swapper/319:35:193
26170995043,4cyclictest17370-21cron20:00:002
26170995016,6cyclictest33-21ksoftirqd/222:45:172
215792490,2sleep30-21swapper/320:05:283
2617099436,3cyclictest121rcu_preempt23:40:152
26170994311,6cyclictest33-21ksoftirqd/220:20:132
139291430,0ptp4l401ktimersoftd/323:09:013
139291430,0ptp4l401ktimersoftd/321:12:533
2617099428,7cyclictest33-21ksoftirqd/221:30:162
2617099426,5cyclictest33-21ksoftirqd/200:05:012
26170994237,3cyclictest33-21ksoftirqd/200:25:012
26170994231,9cyclictest33-21ksoftirqd/221:35:272
26170994211,4cyclictest33-21ksoftirqd/222:35:272
139291420,0ptp4l401ktimersoftd/321:30:263
26171994122,3cyclictest41-21ksoftirqd/319:49:493
2617099416,5cyclictest33-21ksoftirqd/220:45:152
26170994134,4cyclictest18053-21cron00:30:002
2617099411,4cyclictest33-21ksoftirqd/221:50:002
26171994030,6cyclictest41-21ksoftirqd/300:05:123
2617099408,4cyclictest33-21ksoftirqd/223:00:002
2617099407,4cyclictest33-21ksoftirqd/220:00:152
2617099406,6cyclictest33-21ksoftirqd/223:50:242
2617099405,6cyclictest33-21ksoftirqd/223:30:182
2617099405,6cyclictest33-21ksoftirqd/223:10:252
2617099403,6cyclictest33-21ksoftirqd/221:50:142
2617099403,6cyclictest33-21ksoftirqd/220:30:212
26170994035,3cyclictest33-21ksoftirqd/220:25:282
2617099401,3cyclictest121rcu_preempt19:25:242
2617099401,2cyclictest121rcu_preempt21:15:172
26170994012,7cyclictest33-21ksoftirqd/222:00:222
26170994010,7cyclictest33-21ksoftirqd/219:40:002
139291400,1ptp4l401ktimersoftd/323:51:443
139291400,0ptp4l401ktimersoftd/320:44:533
2617099398,7cyclictest33-21ksoftirqd/221:05:142
2617099397,2cyclictest33-21ksoftirqd/223:00:222
2617099395,6cyclictest33-21ksoftirqd/222:10:202
2617099395,6cyclictest33-21ksoftirqd/222:10:202
2617099395,6cyclictest33-21ksoftirqd/220:05:132
26170993934,3cyclictest33-21ksoftirqd/200:35:002
2617099391,2cyclictest121rcu_preempt23:25:202
2616999390,6cyclictest6882-21idleruntime-cro20:45:001
26168993935,2cyclictest9-21ksoftirqd/021:15:000
26168993934,3cyclictest9-21ksoftirqd/023:20:000
26171993832,4cyclictest41-21ksoftirqd/320:12:183
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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