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2026-04-14 - 22:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot4.osadl.org (updated Tue Apr 14, 2026 12:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
32542232167,22sleep20-21swapper/207:07:532
138591213185,19phc2sys0-21swapper/307:06:593
31852205159,35sleep10-21swapper/107:06:581
31892202169,22sleep00-21swapper/007:07:020
3721996529,7cyclictest41-21ksoftirqd/307:35:263
3721996126,10cyclictest41-21ksoftirqd/308:25:213
3721996126,10cyclictest41-21ksoftirqd/308:25:203
3721996028,8cyclictest41-21ksoftirqd/309:05:213
3721996023,9cyclictest41-21ksoftirqd/308:40:003
3721995930,3cyclictest41-21ksoftirqd/312:20:193
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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