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2026-01-14 - 13:33
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot4.osadl.org (updated Wed Jan 14, 2026 00:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
228442203170,22sleep10-21swapper/119:05:451
230932202167,23sleep00-21swapper/019:08:590
221742202169,21sleep30-21swapper/319:05:193
228402200167,22sleep20-21swapper/219:05:432
2485821330,5sleep02346799cyclictest22:25:230
45482840,23sleep32347099cyclictest20:40:193
145892570,2sleep30-21swapper/323:10:183
217232460,1sleep20-21swapper/200:30:002
23469994540,3cyclictest33-21ksoftirqd/200:40:002
23469994540,3cyclictest33-21ksoftirqd/200:40:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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