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2025-11-30 - 11:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot4.osadl.org (updated Sun Nov 30, 2025 00:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
427791205172,22phc2sys0-21swapper/319:06:093
262202202168,22sleep10-21swapper/119:09:511
262142202167,23sleep00-21swapper/019:09:460
261282202169,22sleep20-21swapper/219:08:402
2536721570,2sleep12652599cyclictest20:10:241
427291690,1ptp4l401ktimersoftd/300:01:523
26525996611,12cyclictest23914-21/usr/sbin/munin21:10:291
26525996411,19cyclictest21656-21sendmail-mta22:14:171
26525996311,12cyclictest19738-21/usr/sbin/munin00:20:121
2652599629,12cyclictest23612-21/usr/sbin/munin23:20:251
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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