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2025-05-09 - 05:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot4.osadl.org (updated Fri May 09, 2025 00:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
292652203171,21sleep10-21swapper/119:09:461
134791201167,23phc2sys0-21swapper/319:05:433
290552200166,22sleep20-21swapper/219:07:012
289452199165,22sleep00-21swapper/019:05:340
292882161122,13sleep10-21swapper/119:10:021
134991730,1ptp4l0-21swapper/322:17:363
118372690,6sleep22958299cyclictest21:50:002
235352670,3sleep20-21swapper/222:10:262
29583996432,4cyclictest41-21ksoftirqd/319:35:003
77372630,5sleep20-21swapper/223:50:152
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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