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2025-10-13 - 17:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot4.osadl.org (updated Mon Oct 13, 2025 12:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
134791237168,22phc2sys0-21swapper/307:06:313
7162203170,22sleep20-21swapper/207:09:362
4532201166,23sleep00-21swapper/007:06:110
4182201167,22sleep10-21swapper/107:05:441
362621560,6sleep2106599cyclictest07:15:132
217182560,2sleep00-21swapper/010:00:190
145892560,2sleep00-21swapper/008:40:200
119512550,2sleep20-21swapper/211:50:212
5812500,2sleep30-21swapper/311:30:003
5812500,2sleep30-21swapper/311:29:593
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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