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2025-08-21 - 21:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot4.osadl.org (updated Thu Aug 21, 2025 12:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
134791228162,21phc2sys0-21swapper/307:07:093
300932204170,22sleep20-21swapper/207:08:062
300142202167,23sleep00-21swapper/007:07:030
300402201167,22sleep10-21swapper/107:07:241
369981030,75rtkit-daemon0-21swapper/307:10:013
140052720,2sleep10-21swapper/112:00:221
140052720,2sleep10-21swapper/112:00:221
40272600,4sleep2321ktimersoftd/208:25:202
11782580,3sleep0518-21/usr/sbin/munin10:30:180
134991560,1ptp4l401ktimersoftd/311:38:513
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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