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2026-05-30 - 02:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot4.osadl.org (updated Fri May 29, 2026 12:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591205171,22phc2sys0-21swapper/307:08:243
85822203168,23sleep00-21swapper/007:05:270
89262202167,24sleep10-21swapper/107:09:511
87022200167,22sleep20-21swapper/207:07:012
1384911150,1ptp4l10659-21fschecks_time08:50:153
1385918763,16phc2sys0-21swapper/307:10:023
134991590,9getstats0-21swapper/309:20:123
9232995725,5cyclictest9-21ksoftirqd/009:05:190
923299534,7cyclictest4092-21sed10:45:180
327082520,4sleep032712-21dump-pmu-power08:20:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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