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2026-07-14 - 05:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot4.osadl.org (updated Tue Jul 14, 2026 00:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591206172,23phc2sys0-21swapper/319:07:083
49862204172,22sleep10-21swapper/119:05:051
69742203170,22sleep20-21swapper/219:06:552
70962201166,23sleep00-21swapper/019:08:300
1977821160,2sleep2750499cyclictest23:55:142
132922790,6sleep2750499cyclictest23:40:222
7505996229,6cyclictest41-21ksoftirqd/321:50:243
7505996228,7cyclictest41-21ksoftirqd/322:35:253
7505996228,7cyclictest41-21ksoftirqd/319:30:193
7505996227,7cyclictest41-21ksoftirqd/323:15:213
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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