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2026-02-17 - 08:40
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rackdslot4.osadl.org (updated Tue Feb 17, 2026 00:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
69222207173,23sleep30-21swapper/319:07:443
69252204170,23sleep10-21swapper/119:07:461
70012199165,23sleep00-21swapper/019:08:450
69212199166,21sleep20-21swapper/219:07:422
2426421440,3sleep1739199cyclictest19:42:121
50798950,76rtkit-daemon0-21swapper/119:10:021
148712740,2sleep00-21swapper/022:40:140
7392997032,3cyclictest33-21ksoftirqd/221:55:132
7392996128,16cyclictest33-21ksoftirqd/220:20:212
228412610,4sleep0739099cyclictest20:45:160
7392996024,5cyclictest33-21ksoftirqd/220:20:002
245652600,2sleep00-21swapper/021:55:000
174752600,2sleep30-21swapper/323:50:133
7392995925,5cyclictest33-21ksoftirqd/223:59:592
7392995925,5cyclictest33-21ksoftirqd/200:00:002
739399587,8cyclictest5530-21grep23:25:193
739399587,8cyclictest5530-21grep23:25:193
739399585,5cyclictest8811-21grep19:10:243
7393995820,6cyclictest41-21ksoftirqd/321:20:183
7392995824,5cyclictest33-21ksoftirqd/220:05:002
7390995829,8cyclictest9-21ksoftirqd/022:05:130
7390995817,9cyclictest9-21ksoftirqd/020:20:120
7390995817,8cyclictest9-21ksoftirqd/023:35:240
7392995728,3cyclictest33-21ksoftirqd/223:40:152
7392995727,7cyclictest33-21ksoftirqd/223:00:002
7392995726,4cyclictest33-21ksoftirqd/200:25:152
7392995723,5cyclictest33-21ksoftirqd/221:05:192
7392995723,4cyclictest33-21ksoftirqd/222:25:132
7392995717,11cyclictest33-21ksoftirqd/220:40:192
7392995717,11cyclictest33-21ksoftirqd/220:40:192
7390995725,4cyclictest9-21ksoftirqd/020:00:190
739399567,7cyclictest27904-21cut23:05:193
739399566,6cyclictest24886-21cpuspeed_turbos20:50:133
739399565,7cyclictest17254-21cpuspeed_turbos22:45:123
739399565,7cyclictest17254-21cpuspeed_turbos22:45:123
7392995522,6cyclictest33-21ksoftirqd/219:50:162
7392995520,6cyclictest33-21ksoftirqd/200:10:012
7390995525,4cyclictest9-21ksoftirqd/021:55:130
739399547,6cyclictest32589-21if_enp4s023:15:163
7392995426,4cyclictest33-21ksoftirqd/223:00:262
7392995423,6cyclictest33-21ksoftirqd/223:55:002
7392995422,6cyclictest33-21ksoftirqd/222:45:242
7392995422,6cyclictest33-21ksoftirqd/222:45:242
7392995422,5cyclictest33-21ksoftirqd/221:30:002
7392995422,5cyclictest33-21ksoftirqd/200:20:232
7392995419,5cyclictest33-21ksoftirqd/200:35:002
739399537,6cyclictest18027-21sed21:40:193
739399537,6cyclictest18027-21sed21:40:193
7392995330,3cyclictest33-21ksoftirqd/222:40:192
7392995322,6cyclictest33-21ksoftirqd/223:10:012
7392995322,6cyclictest33-21ksoftirqd/220:50:192
7392995322,6cyclictest33-21ksoftirqd/219:30:122
7392995322,6cyclictest33-21ksoftirqd/200:00:182
7392995320,7cyclictest33-21ksoftirqd/221:10:282
7392995320,7cyclictest33-21ksoftirqd/221:10:272
7392995320,5cyclictest33-21ksoftirqd/219:40:182
7392995319,7cyclictest33-21ksoftirqd/220:10:132
7392995317,15cyclictest33-21ksoftirqd/220:30:162
43752530,3sleep10-21swapper/121:14:061
43752530,3sleep10-21swapper/121:14:061
138491530,1ptp4l391rcuc/323:20:283
739399524,6cyclictest5616-21irqrtprio22:20:193
739399524,6cyclictest13410-21latency19:20:203
7392995224,10cyclictest33-21ksoftirqd/221:50:002
7392995221,6cyclictest33-21ksoftirqd/222:05:162
7392995221,6cyclictest33-21ksoftirqd/221:50:272
7392995221,6cyclictest33-21ksoftirqd/220:45:192
7392995221,6cyclictest33-21ksoftirqd/200:10:232
7392995221,5cyclictest33-21ksoftirqd/223:10:192
7392995221,5cyclictest33-21ksoftirqd/222:10:162
7392995221,4cyclictest33-21ksoftirqd/221:00:202
7392995219,6cyclictest33-21ksoftirqd/222:00:122
7392995219,5cyclictest33-21ksoftirqd/220:00:162
7392995219,5cyclictest33-21ksoftirqd/219:15:002
7392995218,6cyclictest33-21ksoftirqd/223:35:012
739399515,6cyclictest14517-21latency_hist22:40:003
739399514,6cyclictest32094-21cat22:10:003
7392995123,4cyclictest33-21ksoftirqd/223:25:162
7392995123,4cyclictest33-21ksoftirqd/223:25:162
7392995121,5cyclictest33-21ksoftirqd/220:35:222
7392995120,5cyclictest33-21ksoftirqd/220:25:252
7392995120,4cyclictest33-21ksoftirqd/200:15:142
7392995120,11cyclictest33-21ksoftirqd/219:45:182
7392995119,4cyclictest33-21ksoftirqd/223:35:132
7392995118,6cyclictest33-21ksoftirqd/221:35:192
7393995025,7cyclictest41-21ksoftirqd/320:40:193
7393995025,7cyclictest41-21ksoftirqd/320:40:183
7392995021,6cyclictest33-21ksoftirqd/222:30:232
7392995020,4cyclictest33-21ksoftirqd/221:15:132
7392995019,9cyclictest33-21ksoftirqd/222:20:232
7392995019,4cyclictest33-21ksoftirqd/200:35:142
7392995018,6cyclictest33-21ksoftirqd/222:50:142
7392995018,6cyclictest33-21ksoftirqd/220:55:172
7392995018,6cyclictest33-21ksoftirqd/219:25:012
7392995018,5cyclictest33-21ksoftirqd/223:50:002
7392995017,6cyclictest33-21ksoftirqd/223:20:002
7392995017,6cyclictest33-21ksoftirqd/219:25:222
739099503,6cyclictest9-21ksoftirqd/021:20:260
7390995031,8cyclictest9-21ksoftirqd/019:35:140
739399495,7cyclictest5917-21cut21:15:243
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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