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2026-02-05 - 00:34
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rackdslot4.osadl.org (updated Wed Feb 04, 2026 12:45:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591203168,23phc2sys0-21swapper/307:07:153
301472202169,22sleep00-21swapper/007:06:160
303572201168,22sleep10-21swapper/107:08:541
301442200168,21sleep20-21swapper/207:06:142
304442157117,14sleep00-21swapper/007:10:010
30736997110,11cyclictest3104-21sendmail07:20:001
30736997013,27cyclictest16791-21cut07:45:181
30736996912,10cyclictest15911-21uname12:05:211
30735996729,7cyclictest9-21ksoftirqd/010:00:010
30736996612,11cyclictest10287-21sed08:35:271
30735996633,5cyclictest9-21ksoftirqd/012:15:010
30735996633,5cyclictest9-21ksoftirqd/011:50:000
30735996631,6cyclictest9-21ksoftirqd/010:30:000
30735996630,5cyclictest9-21ksoftirqd/007:40:000
30736996513,9cyclictest23377-21idleruntime-cro10:10:001
30736996412,10cyclictest4435-21sed08:25:191
30736996411,9cyclictest15739-21latency_hist08:49:591
30736996411,11cyclictest13312-21ls08:45:001
30735996430,5cyclictest9-21ksoftirqd/008:55:150
3073699639,17cyclictest29303-21latency_hist12:35:001
3073699638,18cyclictest0-21swapper/109:40:001
3073699638,17cyclictest0-21swapper/110:55:001
3073699637,17cyclictest0-21swapper/112:15:281
30736996313,10cyclictest8756-21grep09:40:121
30736996311,10cyclictest703-21latency_hist07:15:011
30736996311,10cyclictest26458-21df_abs10:15:131
30736996311,10cyclictest20068-21ptp4l-jitter08:55:221
30736996310,17cyclictest0-21swapper/110:20:251
30736996310,10cyclictest27009-21cut09:10:191
30735996335,8cyclictest9-21ksoftirqd/009:40:000
30735996332,5cyclictest9-21ksoftirqd/012:00:000
30735996332,5cyclictest9-21ksoftirqd/012:00:000
30735996332,5cyclictest9-21ksoftirqd/010:15:000
30735996329,7cyclictest9-21ksoftirqd/007:15:180
30735996329,6cyclictest9-21ksoftirqd/011:05:000
30735996328,5cyclictest9-21ksoftirqd/012:30:230
30737996216,8cyclictest33-21ksoftirqd/210:05:202
3073699629,9cyclictest31593-21df_abs11:30:131
3073699629,16cyclictest20857-21cron11:10:011
3073699628,9cyclictest0-21swapper/111:55:151
3073699628,9cyclictest0-21swapper/111:55:151
30735996233,3cyclictest9-21ksoftirqd/008:25:000
30735996231,4cyclictest9-21ksoftirqd/010:00:240
30735996229,4cyclictest9-21ksoftirqd/007:50:200
30735996228,4cyclictest9-21ksoftirqd/010:05:140
30735996227,7cyclictest9-21ksoftirqd/010:15:130
3073699619,11cyclictest11414-21cpuspeed_turbos09:45:131
3073699619,10cyclictest28824-21fschecks_count08:10:141
30736996112,9cyclictest26569-21if_err_enp4s008:05:171
30736996110,11cyclictest17443-21mailstats08:50:251
30735996131,4cyclictest9-21ksoftirqd/012:15:250
30735996131,4cyclictest9-21ksoftirqd/008:30:220
30735996130,6cyclictest9-21ksoftirqd/011:10:010
30735996130,6cyclictest9-21ksoftirqd/008:30:000
30735996130,3cyclictest9-21ksoftirqd/012:30:000
30735996129,6cyclictest9-21ksoftirqd/009:05:250
30735996129,5cyclictest9-21ksoftirqd/008:45:140
30735996128,6cyclictest9-21ksoftirqd/009:30:150
30735996128,4cyclictest9-21ksoftirqd/007:25:220
30735996127,7cyclictest9-21ksoftirqd/011:10:260
30735996127,4cyclictest9-21ksoftirqd/010:50:180
30735996125,7cyclictest9-21ksoftirqd/009:25:230
3073699608,11cyclictest16701-21fschecks_count09:55:151
3073699607,18cyclictest0-21swapper/107:55:231
3073699607,15cyclictest0-21swapper/108:20:211
30736996013,9cyclictest32729-21chrt10:25:271
30736996012,15cyclictest8457-21timedrift11:50:261
30736996010,9cyclictest6687-21if_enp1s007:25:191
30736996010,9cyclictest6431-21df_abs10:40:151
30736996010,9cyclictest1536-21fschecks_count10:30:161
30735996032,4cyclictest9-21ksoftirqd/007:20:260
30735996030,5cyclictest9-21ksoftirqd/009:40:260
30735996030,4cyclictest9-21ksoftirqd/009:00:200
30735996029,6cyclictest9-21ksoftirqd/011:25:000
30735996029,6cyclictest9-21ksoftirqd/009:45:270
30735996029,6cyclictest9-21ksoftirqd/008:40:260
30735996029,6cyclictest9-21ksoftirqd/007:30:260
30735996027,6cyclictest9-21ksoftirqd/009:20:230
30735996027,5cyclictest9-21ksoftirqd/008:00:130
30735996027,4cyclictest9-21ksoftirqd/010:35:170
30735996026,7cyclictest9-21ksoftirqd/008:05:230
30735996025,4cyclictest9-21ksoftirqd/009:50:250
3073699599,11cyclictest24466-21date12:25:001
3073699598,9cyclictest0-21swapper/111:25:141
30736995910,12cyclictest21035-21latency_hist11:10:011
30736995910,11cyclictest3545-21cut07:20:141
30736995910,10cyclictest6279-21cstates08:30:131
30736995910,10cyclictest25469-21timerwakeupswit11:15:261
30735995929,5cyclictest9-21ksoftirqd/010:45:230
30735995929,3cyclictest9-21ksoftirqd/009:15:160
30735995928,7cyclictest9-21ksoftirqd/007:40:130
30735995928,6cyclictest9-21ksoftirqd/011:55:000
30735995927,7cyclictest9-21ksoftirqd/012:00:190
30735995926,6cyclictest9-21ksoftirqd/011:30:000
30735995926,6cyclictest9-21ksoftirqd/009:10:250
30735995926,6cyclictest9-21ksoftirqd/008:15:020
30735995924,6cyclictest9-21ksoftirqd/007:50:000
30735995923,8cyclictest9-21ksoftirqd/012:35:180
3073699588,9cyclictest0-21swapper/107:35:161
3073699587,18cyclictest0-21swapper/111:00:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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