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2026-01-19 - 17:21
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rackdslot4.osadl.org (updated Mon Jan 19, 2026 12:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
247702201167,22sleep30-21swapper/307:09:443
246122195161,22sleep00-21swapper/007:07:400
247682194162,21sleep10-21swapper/107:09:421
247692193161,21sleep20-21swapper/207:09:432
183621610,7sleep12509399cyclictest11:45:201
719321530,6sleep32509599cyclictest08:40:253
166462660,7sleep22509499cyclictest11:10:192
138491650,1ptp4l401ktimersoftd/308:50:193
260762640,2sleep20-21swapper/210:25:132
81342610,1sleep10-21swapper/112:00:001
25095996025,4cyclictest41-21ksoftirqd/312:00:003
25095995735,2cyclictest41-21ksoftirqd/311:00:223
93272560,2sleep10-21swapper/107:40:251
25095995526,6cyclictest41-21ksoftirqd/309:15:153
25095995524,4cyclictest41-21ksoftirqd/309:20:193
138491550,1ptp4l401ktimersoftd/308:02:323
138491550,1ptp4l401ktimersoftd/307:15:243
25095995222,4cyclictest41-21ksoftirqd/309:40:153
25095995215,7cyclictest41-21ksoftirqd/309:25:273
25095995025,7cyclictest41-21ksoftirqd/307:55:143
25095995022,4cyclictest41-21ksoftirqd/310:10:243
25095995022,4cyclictest41-21ksoftirqd/310:10:233
25095994922,7cyclictest41-21ksoftirqd/309:30:193
25095994922,4cyclictest41-21ksoftirqd/307:39:133
25095994921,7cyclictest41-21ksoftirqd/311:05:133
25095994921,3cyclictest41-21ksoftirqd/311:40:133
25095994917,4cyclictest41-21ksoftirqd/311:25:203
233332480,1sleep123337-21cat10:20:111
164512480,1sleep00-21swapper/011:10:170
25095994721,7cyclictest41-21ksoftirqd/309:45:283
25095994720,7cyclictest41-21ksoftirqd/308:05:253
25095994715,3cyclictest41-21ksoftirqd/311:50:123
25095994714,4cyclictest41-21ksoftirqd/309:59:593
25095994626,2cyclictest41-21ksoftirqd/309:35:183
25095994619,7cyclictest41-21ksoftirqd/310:05:013
25095994619,6cyclictest41-21ksoftirqd/308:35:133
25095994616,3cyclictest41-21ksoftirqd/307:20:253
2509599457,4cyclictest41-21ksoftirqd/311:48:303
25095994510,4cyclictest41-21ksoftirqd/310:30:003
2509599446,4cyclictest41-21ksoftirqd/312:06:563
2509599446,4cyclictest41-21ksoftirqd/309:04:343
2509599443,2cyclictest25850-21grep07:10:163
25095994430,11cyclictest41-21ksoftirqd/308:55:163
25095994415,6cyclictest41-21ksoftirqd/311:20:233
25095994414,3cyclictest41-21ksoftirqd/310:10:013
2509599437,4cyclictest41-21ksoftirqd/310:18:033
2509599436,4cyclictest41-21ksoftirqd/312:27:493
2509599436,4cyclictest41-21ksoftirqd/310:46:523
2509599436,4cyclictest41-21ksoftirqd/310:46:523
2509599435,4cyclictest41-21ksoftirqd/308:13:243
25095994315,3cyclictest41-21ksoftirqd/308:22:303
25095994310,7cyclictest41-21ksoftirqd/311:35:243
2509599429,3cyclictest41-21ksoftirqd/310:55:263
2509599427,4cyclictest41-21ksoftirqd/308:31:003
2509599427,4cyclictest41-21ksoftirqd/307:34:403
2509599426,4cyclictest41-21ksoftirqd/312:13:173
2509599426,4cyclictest41-21ksoftirqd/311:19:373
2509599424,4cyclictest41-21ksoftirqd/311:10:063
25095994215,3cyclictest41-21ksoftirqd/308:25:263
25095994212,7cyclictest41-21ksoftirqd/309:50:223
138491420,0ptp4l401ktimersoftd/308:15:213
2509599416,5cyclictest41-21ksoftirqd/312:36:043
2509599414,4cyclictest41-21ksoftirqd/307:25:543
2509599413,3cyclictest121rcu_preempt09:10:253
138491410,0ptp4l401ktimersoftd/308:45:283
2509599406,3cyclictest41-21ksoftirqd/307:50:163
2509599406,3cyclictest41-21ksoftirqd/307:50:163
2509599403,4cyclictest41-21ksoftirqd/312:21:073
2509599403,4cyclictest41-21ksoftirqd/307:46:003
25095994024,12cyclictest41-21ksoftirqd/310:20:143
50798390,7rtkit-daemon0-21swapper/112:26:271
2509599394,8cyclictest41-21ksoftirqd/310:52:363
2509599393,4cyclictest41-21ksoftirqd/310:44:553
25095993933,3cyclictest41-21ksoftirqd/312:30:163
25094993910,27cyclictest0-21swapper/210:15:242
2509599384,4cyclictest41-21ksoftirqd/310:35:123
25095993814,6cyclictest41-21ksoftirqd/309:05:133
25093993831,4cyclictest25-21ksoftirqd/109:40:011
2509599379,7cyclictest41-21ksoftirqd/307:45:003
25095993732,3cyclictest41-21ksoftirqd/312:05:003
25095993730,3cyclictest41-21ksoftirqd/310:30:113
25094993732,3cyclictest33-21ksoftirqd/211:53:122
25094993730,4cyclictest33-21ksoftirqd/207:33:412
25095993630,3cyclictest41-21ksoftirqd/312:20:003
2509599360,2cyclictest121rcu_preempt11:30:203
25094993631,3cyclictest33-21ksoftirqd/212:05:102
25094993631,3cyclictest33-21ksoftirqd/209:08:442
25094993630,4cyclictest33-21ksoftirqd/212:36:112
25094993630,4cyclictest33-21ksoftirqd/212:33:512
25094993630,4cyclictest33-21ksoftirqd/209:18:182
25094993630,4cyclictest33-21ksoftirqd/208:07:142
25093993630,4cyclictest25-21ksoftirqd/108:20:371
25093993630,4cyclictest25-21ksoftirqd/107:20:121
25093993629,4cyclictest25-21ksoftirqd/112:23:071
25092993630,4cyclictest9-21ksoftirqd/009:52:190
25092993630,4cyclictest9-21ksoftirqd/008:40:100
25092993629,5cyclictest9-21ksoftirqd/009:13:590
50798350,6rtkit-daemon9-21ksoftirqd/008:02:530
25094993529,4cyclictest33-21ksoftirqd/211:48:472
25094993529,4cyclictest33-21ksoftirqd/210:44:032
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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