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2026-02-26 - 22:11
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rackdslot4.osadl.org (updated Thu Feb 26, 2026 12:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
144982204172,21sleep20-21swapper/207:07:342
144392203169,22sleep00-21swapper/007:06:480
145282202168,23sleep10-21swapper/107:07:561
138591202168,23phc2sys0-21swapper/307:05:043
239521830,5sleep21498999cyclictest08:55:002
147022162122,14sleep00-21swapper/007:10:010
147022162122,14sleep00-21swapper/007:10:010
1974221600,4sleep21498999cyclictest10:35:142
2032321400,7sleep11498899cyclictest07:20:121
14990997310,23cyclictest20606-21cut08:25:183
99592610,2sleep30-21swapper/309:10:143
186492570,5sleep11498899cyclictest08:20:211
138491550,1ptp4l391rcuc/307:35:263
271642540,2sleep027168-21cpuspeed09:45:130
14989995322,6cyclictest33-21ksoftirqd/211:59:592
300702520,1sleep00-21swapper/007:40:130
22812510,1sleep30-21swapper/310:00:133
138491480,1ptp4l391rcuc/307:30:383
1499099476,26cyclictest25154-21sort09:40:153
14989994510,6cyclictest33-21ksoftirqd/207:20:012
1499099441,30cyclictest1328-21sshd10:29:303
1499099441,30cyclictest1328-21sshd10:29:303
14990994338,3cyclictest17006-21cron09:24:593
1499099430,33cyclictest0-21swapper/308:10:013
14989994336,4cyclictest33-21ksoftirqd/208:15:002
138491430,0ptp4l401ktimersoftd/312:15:153
14989994237,3cyclictest33-21ksoftirqd/208:25:002
138491420,1ptp4l401ktimersoftd/310:10:143
138491420,0ptp4l401ktimersoftd/311:00:253
1498999417,8cyclictest33-21ksoftirqd/211:15:012
1498999417,6cyclictest33-21ksoftirqd/209:30:162
1498999414,3cyclictest121rcu_preempt11:45:192
14989994135,3cyclictest33-21ksoftirqd/210:00:002
14989994111,5cyclictest33-21ksoftirqd/212:35:162
14989994111,5cyclictest33-21ksoftirqd/212:35:162
14989994110,6cyclictest33-21ksoftirqd/212:05:142
1498999409,5cyclictest33-21ksoftirqd/208:00:182
14989994037,2cyclictest311rcuc/211:00:132
14989994035,3cyclictest33-21ksoftirqd/207:55:132
14989994035,3cyclictest33-21ksoftirqd/207:55:132
14989994034,3cyclictest33-21ksoftirqd/211:40:002
14989994017,11cyclictest33-21ksoftirqd/209:45:272
14988994035,3cyclictest25-21ksoftirqd/107:59:591
14988994035,3cyclictest25-21ksoftirqd/107:59:591
1498899403,4cyclictest0-21swapper/108:49:591
14987994035,3cyclictest9-21ksoftirqd/009:40:000
1498999398,5cyclictest33-21ksoftirqd/210:40:162
1498999396,2cyclictest121rcu_preempt07:45:232
14989993936,2cyclictest33-21ksoftirqd/211:55:012
14989993935,3cyclictest33-21ksoftirqd/211:35:002
14989993933,3cyclictest33-21ksoftirqd/207:45:002
1498999390,8cyclictest33-21ksoftirqd/209:25:012
1498999385,4cyclictest33-21ksoftirqd/210:25:122
1498999385,4cyclictest33-21ksoftirqd/210:25:122
14989993835,2cyclictest33-21ksoftirqd/211:00:002
14989993834,3cyclictest33-21ksoftirqd/207:10:122
14989993834,3cyclictest33-21ksoftirqd/207:10:122
14989993833,3cyclictest33-21ksoftirqd/210:15:002
14989993833,3cyclictest33-21ksoftirqd/210:05:002
14989993833,3cyclictest33-21ksoftirqd/209:05:152
14989993833,3cyclictest33-21ksoftirqd/208:35:282
14989993832,4cyclictest33-21ksoftirqd/207:36:302
14989993832,3cyclictest33-21ksoftirqd/211:15:282
14989993832,3cyclictest33-21ksoftirqd/208:50:002
1498999382,4cyclictest33-21ksoftirqd/208:30:142
14988993834,2cyclictest25-21ksoftirqd/109:49:591
14988993833,3cyclictest25-21ksoftirqd/109:40:011
14988993833,3cyclictest25-21ksoftirqd/108:30:011
1499099374,30cyclictest13550-21open_files09:15:213
14990993730,5cyclictest41-21ksoftirqd/308:22:393
1499099372,33cyclictest9809-21latency_hist11:20:003
1498999378,6cyclictest33-21ksoftirqd/207:50:222
1498999376,4cyclictest33-21ksoftirqd/207:30:202
14989993732,3cyclictest33-21ksoftirqd/212:30:182
14989993731,4cyclictest33-21ksoftirqd/210:49:492
14989993731,4cyclictest33-21ksoftirqd/209:13:372
14989993731,4cyclictest33-21ksoftirqd/208:40:122
14989993730,4cyclictest33-21ksoftirqd/212:02:432
14989993725,3cyclictest33-21ksoftirqd/209:40:002
14989993721,4cyclictest33-21ksoftirqd/209:05:012
1498999371,3cyclictest121rcu_preempt09:40:272
14989993710,7cyclictest33-21ksoftirqd/208:55:162
14989993710,7cyclictest33-21ksoftirqd/208:55:152
14988993731,4cyclictest25-21ksoftirqd/107:19:361
1499099365,29cyclictest17216-21awk11:35:013
1499099364,20cyclictest6918-21dump-pmu-power10:10:013
14990993630,4cyclictest41-21ksoftirqd/312:38:193
14990993630,4cyclictest41-21ksoftirqd/312:38:193
14990993630,4cyclictest41-21ksoftirqd/308:51:533
14990993613,20cyclictest6527-21sed11:10:253
1498999366,5cyclictest33-21ksoftirqd/211:20:222
1498999366,5cyclictest33-21ksoftirqd/208:25:142
1498999365,8cyclictest33-21ksoftirqd/208:20:002
14989993631,3cyclictest33-21ksoftirqd/212:20:132
14989993631,3cyclictest33-21ksoftirqd/212:20:002
14989993631,3cyclictest33-21ksoftirqd/212:10:122
14989993631,3cyclictest33-21ksoftirqd/211:10:012
14989993631,3cyclictest33-21ksoftirqd/210:20:002
14989993631,3cyclictest33-21ksoftirqd/209:15:202
14989993629,4cyclictest33-21ksoftirqd/210:32:122
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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