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2026-07-05 - 14:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sun Jul 05, 2026 00:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591227162,22phc2sys0-21swapper/319:09:063
93112205139,22sleep00-21swapper/019:09:240
91692203171,21sleep20-21swapper/219:07:342
92872202169,22sleep10-21swapper/119:09:041
80622700,4sleep00-21swapper/000:30:210
980599690,30cyclictest8139-21/usr/sbin/munin23:25:192
980599670,22cyclictest28859-21mailstats19:45:232
980599661,28cyclictest8369-21/usr/sbin/munin22:20:222
980599660,21cyclictest6150-21/usr/sbin/munin20:05:222
980599650,22cyclictest4661-21/usr/sbin/munin23:20:192
980599650,22cyclictest223-21systemd-journal00:28:272
980599650,21cyclictest7898-21cut00:30:202
980599640,30cyclictest32035-21sshd19:54:452
980599640,22cyclictest22675-21/usr/sbin/munin23:55:182
980599631,21cyclictest28683-21timerwakeupswit21:55:252
980599620,30cyclictest20320-21/usr/sbin/munin21:40:182
138491600,1ptp4l401ktimersoftd/321:01:243
980599590,20cyclictest5919-21missed_timers21:10:232
980599590,20cyclictest5919-21missed_timers21:10:232
980599590,19cyclictest30775-21phc2sys22:00:232
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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