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2026-08-01 - 22:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sat Aug 01, 2026 12:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
325942213164,37sleep10-21swapper/107:09:591
323202204168,25sleep20-21swapper/207:06:262
325602200167,21sleep00-21swapper/007:09:330
138591200166,22phc2sys0-21swapper/307:06:163
2254721500,5sleep250399cyclictest07:55:012
3123421400,5sleep050199cyclictest09:15:210
503995712,8cyclictest33-21ksoftirqd/209:20:002
503995624,4cyclictest33-21ksoftirqd/208:25:192
1385915537,11phc2sys0-21swapper/307:10:013
503995022,6cyclictest33-21ksoftirqd/210:35:002
503995021,4cyclictest33-21ksoftirqd/210:10:252
503995021,4cyclictest33-21ksoftirqd/209:05:162
503994921,6cyclictest33-21ksoftirqd/209:50:192
501994930,3cyclictest9-21ksoftirqd/008:38:580
503994821,7cyclictest33-21ksoftirqd/209:05:012
503994818,4cyclictest33-21ksoftirqd/212:15:202
503994814,6cyclictest33-21ksoftirqd/209:14:592
503994727,3cyclictest33-21ksoftirqd/212:20:192
503994722,7cyclictest33-21ksoftirqd/211:55:202
503994717,3cyclictest33-21ksoftirqd/208:15:162
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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