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2026-05-28 - 05:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Thu May 28, 2026 00:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591226162,22phc2sys0-21swapper/319:09:563
194512215151,22sleep00-21swapper/019:06:540
196312202169,22sleep10-21swapper/119:09:161
196322201168,21sleep20-21swapper/219:09:172
1065921680,5sleep21998799cyclictest19:55:172
1357921540,2sleep21998799cyclictest00:20:182
1969428162,10sleep20-21swapper/219:10:012
217902720,1sleep30-21swapper/321:20:233
19987997119,10cyclictest33-21ksoftirqd/222:25:232
19985996725,6cyclictest9-21ksoftirqd/000:35:220
19987996422,5cyclictest33-21ksoftirqd/220:30:192
19986996333,4cyclictest25-21ksoftirqd/119:50:131
19986996222,4cyclictest25-21ksoftirqd/100:00:171
19985996229,6cyclictest9-21ksoftirqd/023:00:180
19985996219,8cyclictest9-21ksoftirqd/019:10:230
19987996119,10cyclictest33-21ksoftirqd/221:45:262
19986996121,9cyclictest25-21ksoftirqd/100:11:131
19985996129,7cyclictest9-21ksoftirqd/021:50:150
19986996030,3cyclictest25-21ksoftirqd/123:10:001
19986996029,4cyclictest25-21ksoftirqd/120:50:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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