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2026-01-09 - 04:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Fri Jan 09, 2026 00:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
123072232167,21sleep20-21swapper/219:06:492
124952205171,23sleep30-21swapper/319:09:073
122502202169,22sleep10-21swapper/119:06:041
124352201167,22sleep00-21swapper/019:08:200
3174321400,7sleep11285899cyclictest21:55:251
653921310,2sleep01285799cyclictest23:15:220
1286099650,25cyclictest0-21swapper/321:20:323
138491630,1ptp4l10214-21/usr/sbin/munin22:20:173
300052620,2sleep00-21swapper/000:05:010
259102620,1sleep30-21swapper/320:40:173
1285799581,11cyclictest3982-21sed21:00:180
1285799577,10cyclictest13397-21sed00:35:120
219172540,1sleep00-21swapper/021:35:260
1285799544,9cyclictest3705-21irqrtprio23:10:170
1285799544,9cyclictest11863-21grep20:10:230
1285799543,9cyclictest3133-21tr00:15:150
1285799534,9cyclictest25531-21cstates20:40:130
1285799534,10cyclictest19011-21tr19:20:210
1286099524,21cyclictest0-21swapper/322:27:523
1285799524,9cyclictest4305-21grep22:05:240
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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