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2026-06-10 - 04:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Wed Jun 10, 2026 00:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
316612203168,23sleep30-21swapper/319:06:463
317242202169,22sleep20-21swapper/219:07:342
315682202169,22sleep10-21swapper/119:05:401
316632199166,21sleep00-21swapper/019:06:470
3018421640,7sleep23220499cyclictest21:15:192
515221460,4sleep33220599cyclictest20:25:133
1385918765,12phc2sys0-21swapper/319:10:003
32202996734,3cyclictest9-21ksoftirqd/020:40:010
32205996323,7cyclictest41-21ksoftirqd/321:00:223
32205996323,7cyclictest41-21ksoftirqd/321:00:223
32205996224,4cyclictest41-21ksoftirqd/300:10:243
32202996120,4cyclictest9-21ksoftirqd/020:44:320
32202996024,4cyclictest9-21ksoftirqd/022:15:010
32203995921,3cyclictest25-21ksoftirqd/121:25:001
32202995926,3cyclictest9-21ksoftirqd/022:36:220
32205995828,4cyclictest41-21ksoftirqd/321:15:283
32205995825,6cyclictest41-21ksoftirqd/320:25:003
32202995818,4cyclictest9-21ksoftirqd/023:00:230
32202995815,4cyclictest9-21ksoftirqd/021:50:120
32205995722,3cyclictest41-21ksoftirqd/320:45:233
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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