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2026-08-05 - 15:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Wed Aug 05, 2026 00:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2733822590,29sleep227343-21fschecks_count19:05:162
289282204169,23sleep10-21swapper/119:08:391
138591204170,23phc2sys0-21swapper/319:05:573
289112202168,22sleep00-21swapper/019:08:250
138591133108,14phc2sys0-21swapper/319:10:013
17112780,3sleep31712-21dump-pmu-power21:30:003
29327995932,3cyclictest33-21ksoftirqd/223:00:012
160652590,6sleep22932799cyclictest21:55:272
29325995510,12cyclictest2970-21awk23:40:220
29327995324,7cyclictest33-21ksoftirqd/222:15:182
29325995010,19cyclictest3891-21awk21:30:280
29327994820,7cyclictest33-21ksoftirqd/223:10:002
29327994819,3cyclictest33-21ksoftirqd/223:25:162
2932599485,11cyclictest31359-21cat23:35:010
29327994719,4cyclictest33-21ksoftirqd/200:00:192
29327994716,6cyclictest33-21ksoftirqd/222:44:592
2932799460,2cyclictest121rcu_preempt21:15:282
29327994515,4cyclictest33-21ksoftirqd/221:00:012
2932699452,10cyclictest12473-21hddtemp_smartct21:50:151
138491450,1ptp4l401ktimersoftd/300:19:313
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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