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2026-08-03 - 23:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Mon Aug 03, 2026 12:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591204170,23phc2sys0-21swapper/307:06:543
39722203170,21sleep00-21swapper/007:07:320
38952203167,24sleep10-21swapper/107:06:341
40782201168,22sleep20-21swapper/207:08:552
275052750,3sleep227509-21irqrtprio10:05:182
275052750,3sleep227509-21irqrtprio10:05:182
4463996431,8cyclictest25-21ksoftirqd/109:20:221
4463996428,10cyclictest25-21ksoftirqd/112:20:121
4463996330,6cyclictest25-21ksoftirqd/110:50:191
4463996327,5cyclictest25-21ksoftirqd/110:10:131
4463996128,8cyclictest25-21ksoftirqd/107:40:231
4463996128,8cyclictest25-21ksoftirqd/107:40:231
4463996126,7cyclictest25-21ksoftirqd/109:00:201
4463996123,8cyclictest25-21ksoftirqd/107:30:251
303042610,2sleep230302-21tr11:15:192
4464996026,5cyclictest33-21ksoftirqd/208:55:182
4463996031,4cyclictest25-21ksoftirqd/109:10:221
4463996029,8cyclictest25-21ksoftirqd/111:12:591
4463996029,7cyclictest25-21ksoftirqd/112:10:151
4463996027,9cyclictest25-21ksoftirqd/109:40:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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