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2026-01-19 - 11:11
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Mon Jan 19, 2026 00:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1102923280,42sleep20-21swapper/219:05:122
129122205170,23sleep30-21swapper/319:08:523
128382200166,23sleep10-21swapper/119:07:531
127552198165,23sleep00-21swapper/019:06:480
13294997732,6cyclictest33-21ksoftirqd/221:30:002
13294997124,5cyclictest33-21ksoftirqd/221:05:232
312022700,1sleep231203-21/usr/sbin/munin21:55:142
151902660,7sleep21329499cyclictest20:15:252
13294996322,9cyclictest33-21ksoftirqd/219:20:272
13295996231,4cyclictest41-21ksoftirqd/319:10:173
13294995928,9cyclictest33-21ksoftirqd/220:45:172
13294995928,2cyclictest33-21ksoftirqd/221:20:132
13294995922,11cyclictest33-21ksoftirqd/221:15:182
13294995919,4cyclictest33-21ksoftirqd/220:00:252
13295995825,9cyclictest41-21ksoftirqd/321:45:263
138491570,1ptp4l401ktimersoftd/320:33:153
138491560,1ptp4l401ktimersoftd/321:19:433
13294995629,4cyclictest33-21ksoftirqd/221:45:122
13294995624,9cyclictest33-21ksoftirqd/220:20:272
13294995621,4cyclictest33-21ksoftirqd/223:20:202
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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