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2026-09-07 - 18:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Mon Sep 07, 2026 12:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
145512203166,25sleep30-21swapper/307:07:203
146912202169,22sleep10-21swapper/107:09:111
146322202169,22sleep20-21swapper/207:08:252
144642202169,22sleep00-21swapper/007:06:140
1800721630,4sleep21520399cyclictest08:20:122
1070821500,7sleep11520299cyclictest10:15:141
420721220,2sleep20-21swapper/211:05:212
138491700,1ptp4l391rcuc/311:55:143
138491640,0ptp4l401ktimersoftd/312:22:193
17182570,2sleep20-21swapper/209:55:212
15202995513,13cyclictest25-21ksoftirqd/108:25:241
138491550,1ptp4l391rcuc/308:45:183
138491550,0ptp4l401ktimersoftd/310:04:303
1520199542,5cyclictest15483-21latency_hist11:30:000
1520199531,6cyclictest8388-21fschecks_time08:00:140
1520199531,6cyclictest8388-21fschecks_time08:00:140
138491530,1ptp4l401ktimersoftd/308:57:383
138491530,1ptp4l401ktimersoftd/308:57:383
1520199522,5cyclictest101ktimersoftd/009:20:000
1520199521,5cyclictest22339-21grep09:30:260
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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