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2026-04-05 - 04:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sun Apr 05, 2026 00:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591229170,48phc2sys0-21swapper/319:08:333
168982203170,21sleep20-21swapper/219:09:352
168422203169,23sleep10-21swapper/119:08:491
165872201166,23sleep00-21swapper/019:05:390
2879421450,4sleep21722699cyclictest22:45:282
86472570,5sleep01722499cyclictest19:55:250
264842560,5sleep21722699cyclictest20:33:422
1722499550,16cyclictest22532-21basename23:40:170
1722699542,11cyclictest518-21cut19:40:182
1722699533,9cyclictest23194-21missed_timers21:30:232
125772530,3sleep012579-21df_abs21:10:150
202362520,2sleep20-21swapper/220:20:182
1722699519,5cyclictest33-21ksoftirqd/222:15:062
1722699501,10cyclictest9925-21cstates23:15:122
1722699500,10cyclictest20575-21/usr/sbin/munin23:35:212
1722499503,5cyclictest0-21swapper/021:00:270
138491500,1ptp4l0-21swapper/322:44:563
188092490,4sleep018814-21timerwakeupswit21:20:260
50798480,1rtkit-daemon506-21rtkit-daemon23:38:101
1722699485,6cyclictest5013-21df_abs00:10:132
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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