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2026-09-04 - 11:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Fri Sep 04, 2026 00:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591208163,34phc2sys0-21swapper/319:07:213
276552202168,22sleep20-21swapper/219:05:572
276322200166,22sleep10-21swapper/119:05:401
277252197165,21sleep00-21swapper/019:06:520
138491730,1ptp4l391rcuc/319:50:293
138491720,1ptp4l391rcuc/323:10:273
28268996531,6cyclictest33-21ksoftirqd/221:55:202
28268996531,6cyclictest33-21ksoftirqd/221:55:202
28268996327,6cyclictest33-21ksoftirqd/223:55:002
28268996232,4cyclictest33-21ksoftirqd/221:25:152
28268996131,4cyclictest33-21ksoftirqd/223:10:162
28268996129,8cyclictest33-21ksoftirqd/221:40:282
28268996129,6cyclictest33-21ksoftirqd/222:20:202
28268996129,10cyclictest33-21ksoftirqd/220:50:132
28268996128,9cyclictest33-21ksoftirqd/219:25:222
28268996128,6cyclictest33-21ksoftirqd/221:08:412
28268996127,4cyclictest33-21ksoftirqd/222:25:222
2826899606,7cyclictest33-21ksoftirqd/222:55:122
28268996030,3cyclictest33-21ksoftirqd/222:15:182
28268996029,4cyclictest33-21ksoftirqd/219:45:282
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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