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2026-03-12 - 22:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Thu Mar 12, 2026 12:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
236972203168,23sleep00-21swapper/007:07:080
138591203169,23phc2sys0-21swapper/307:09:033
236942201169,21sleep20-21swapper/207:07:062
237412200168,21sleep10-21swapper/107:07:411
138491800,1ptp4l32096-21diskstats07:25:153
138491660,1ptp4l401ktimersoftd/309:40:153
62272650,6sleep22421699cyclictest12:00:112
24214996424,6cyclictest9-21ksoftirqd/009:50:260
24214996128,6cyclictest9-21ksoftirqd/011:10:010
24214996127,6cyclictest9-21ksoftirqd/011:25:260
24214996123,7cyclictest9-21ksoftirqd/008:25:170
24214996030,8cyclictest9-21ksoftirqd/009:50:000
24214996029,4cyclictest9-21ksoftirqd/011:40:000
24214996027,4cyclictest9-21ksoftirqd/009:25:140
24216995913,4cyclictest33-21ksoftirqd/208:40:232
24214995931,8cyclictest9-21ksoftirqd/009:55:180
24214995928,4cyclictest9-21ksoftirqd/010:20:270
24214995927,5cyclictest9-21ksoftirqd/010:10:180
24214995927,4cyclictest9-21ksoftirqd/011:15:120
24214995926,4cyclictest9-21ksoftirqd/012:30:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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