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2026-07-14 - 01:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Mon Jul 13, 2026 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
124442231166,22sleep00-21swapper/007:09:410
138591221158,52phc2sys0-21swapper/307:07:523
123392203170,22sleep10-21swapper/107:08:211
121782203171,21sleep20-21swapper/207:06:172
462021770,7sleep01276799cyclictest12:15:240
41462710,2sleep20-21swapper/210:05:212
12770996825,10cyclictest41-21ksoftirqd/309:10:273
12770996634,4cyclictest41-21ksoftirqd/308:40:173
12769996434,3cyclictest33-21ksoftirqd/210:35:012
12770996331,4cyclictest41-21ksoftirqd/311:15:253
12770996231,3cyclictest41-21ksoftirqd/311:45:003
12770996231,3cyclictest41-21ksoftirqd/311:45:003
12770996229,4cyclictest41-21ksoftirqd/307:10:233
12770996133,3cyclictest41-21ksoftirqd/308:55:163
12770996127,4cyclictest41-21ksoftirqd/311:39:593
12769996132,3cyclictest33-21ksoftirqd/209:00:192
12770996030,4cyclictest41-21ksoftirqd/309:55:213
12770996029,4cyclictest41-21ksoftirqd/308:10:183
12770996028,3cyclictest41-21ksoftirqd/309:30:003
12769996032,3cyclictest33-21ksoftirqd/208:15:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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