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2026-03-25 - 17:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Wed Mar 25, 2026 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
253362225161,21sleep10-21swapper/107:06:131
138591205170,23phc2sys0-21swapper/307:06:563
256312202170,21sleep20-21swapper/207:09:562
253582202168,22sleep00-21swapper/007:06:280
1358821610,4sleep02592899cyclictest07:50:010
279432710,5sleep227942-21latency_hist11:35:002
25931996327,9cyclictest41-21ksoftirqd/311:10:003
25931996230,9cyclictest41-21ksoftirqd/312:25:273
25931996230,4cyclictest41-21ksoftirqd/307:20:173
25931996130,9cyclictest41-21ksoftirqd/307:50:013
25931996129,8cyclictest41-21ksoftirqd/307:40:143
25931996127,9cyclictest41-21ksoftirqd/309:00:013
25931996126,4cyclictest41-21ksoftirqd/311:25:233
25931996124,9cyclictest41-21ksoftirqd/308:00:163
25931996030,4cyclictest41-21ksoftirqd/308:05:273
25931996027,7cyclictest41-21ksoftirqd/311:50:133
25931996025,4cyclictest41-21ksoftirqd/308:35:263
25931996021,8cyclictest41-21ksoftirqd/309:20:193
25931995928,8cyclictest41-21ksoftirqd/311:40:143
25931995927,7cyclictest41-21ksoftirqd/310:50:193
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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