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2026-09-03 - 08:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Thu Sep 03, 2026 00:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
204492204170,23sleep20-21swapper/219:05:472
204492204170,23sleep20-21swapper/219:05:472
206902202170,21sleep10-21swapper/119:08:541
206902202170,21sleep10-21swapper/119:08:541
138591202168,22phc2sys0-21swapper/319:05:333
138591202168,22phc2sys0-21swapper/319:05:333
206322198166,21sleep00-21swapper/019:08:100
206322198166,21sleep00-21swapper/019:08:100
179982870,27sleep341-21ksoftirqd/322:20:003
138491660,1ptp4l401ktimersoftd/320:16:313
138491650,1ptp4l401ktimersoftd/321:40:153
163022590,2sleep00-21swapper/023:20:190
138491580,1ptp4l401ktimersoftd/323:07:053
285892560,2sleep30-21swapper/319:25:013
21067995622,9cyclictest33-21ksoftirqd/200:35:212
276752550,2sleep327679-21unixbench_multi21:30:263
276752550,2sleep327679-21unixbench_multi21:30:263
21067995529,9cyclictest33-21ksoftirqd/219:25:182
138491550,1ptp4l401ktimersoftd/322:50:223
21067995429,9cyclictest33-21ksoftirqd/220:55:192
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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