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2026-05-21 - 12:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Thu May 21, 2026 00:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591221162,47phc2sys0-21swapper/319:06:013
217982204171,22sleep00-21swapper/019:08:280
217682202168,23sleep20-21swapper/219:08:052
215652202169,22sleep10-21swapper/119:05:281
3206321670,6sleep12220899cyclictest21:40:001
66652830,5sleep1223-21systemd-journal23:00:001
22209996632,6cyclictest33-21ksoftirqd/200:15:002
22209996229,10cyclictest33-21ksoftirqd/221:00:142
22209996129,9cyclictest33-21ksoftirqd/220:55:182
22209996129,8cyclictest33-21ksoftirqd/222:20:172
22209996126,4cyclictest33-21ksoftirqd/219:30:242
22209996030,8cyclictest33-21ksoftirqd/222:15:182
22209996027,7cyclictest33-21ksoftirqd/223:35:182
22209996027,6cyclictest33-21ksoftirqd/200:15:172
22209996026,6cyclictest33-21ksoftirqd/222:30:002
22209995930,4cyclictest33-21ksoftirqd/223:55:142
22209995925,10cyclictest33-21ksoftirqd/223:05:012
22209995923,10cyclictest33-21ksoftirqd/222:30:132
22209995922,6cyclictest33-21ksoftirqd/220:25:242
22209995918,11cyclictest33-21ksoftirqd/219:10:182
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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