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2026-07-26 - 21:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sun Jul 26, 2026 12:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591231163,23phc2sys0-21swapper/307:09:203
296832203168,23sleep10-21swapper/107:08:141
296842200168,21sleep20-21swapper/207:08:162
296272198165,22sleep00-21swapper/007:07:300
890621760,6sleep03011999cyclictest07:30:200
3011999690,23cyclictest19360-21awk11:10:000
3011999680,25cyclictest29392-21awk12:35:000
3011999670,25cyclictest24128-21grep09:05:250
3011999660,25cyclictest24990-21expr10:15:130
3011999651,23cyclictest19984-21cpuspeed09:00:130
3011999651,23cyclictest19984-21cpuspeed09:00:120
3011999650,26cyclictest0-21swapper/012:05:000
3011999640,33cyclictest12747-21tune2fs09:50:150
3011999640,27cyclictest15619-21tune2fs07:45:130
3011999630,25cyclictest25455-21sed11:20:180
3011999630,24cyclictest29949-21cpuspeed_turbos09:20:120
3011999630,24cyclictest20352sleep009:29:020
3011999622,57cyclictest30648-21grep07:10:150
3011999620,25cyclictest18999-21awk10:00:290
3011999600,32cyclictest28898-21grep08:10:240
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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