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2026-06-09 - 02:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Mon Jun 08, 2026 12:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
44982228161,22sleep00-21swapper/007:09:150
43602204170,22sleep20-21swapper/207:07:282
138591204171,22phc2sys0-21swapper/307:06:583
42192202170,22sleep10-21swapper/107:05:381
1385918662,16phc2sys0-21swapper/307:10:013
484899720,30cyclictest23556-21cut12:05:242
484899626,19cyclictest319782sleep208:02:272
484899621,24cyclictest19184-21chrt07:37:282
164762620,1sleep10-21swapper/111:50:251
484899610,28cyclictest24324-21chrt08:50:502
484899570,23cyclictest16588-21chrt07:30:382
484899541,22cyclictest19436-21chrt11:58:572
484899540,24cyclictest21888-21taskset08:46:042
484899530,28cyclictest31539-21awk11:15:262
484899530,22cyclictest7021-21chrt07:14:132
4849995221,3cyclictest41-21ksoftirqd/307:45:053
484899520,22cyclictest27128-21chrt10:02:432
484999519,5cyclictest41-21ksoftirqd/309:24:033
4849995117,3cyclictest41-21ksoftirqd/310:51:523
4849995115,4cyclictest41-21ksoftirqd/310:49:313
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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