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2026-02-21 - 03:00
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Fri Feb 20, 2026 12:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591233166,23phc2sys0-21swapper/307:05:553
120562200167,22sleep10-21swapper/107:06:051
120572199166,22sleep20-21swapper/207:06:072
122222198166,21sleep00-21swapper/007:08:140
3220221750,6sleep01265999cyclictest11:00:240
1385918662,16phc2sys0-21swapper/307:10:013
191582830,6sleep01265999cyclictest10:35:160
135191620,4getstats41-21ksoftirqd/310:30:183
12662996230,6cyclictest41-21ksoftirqd/310:40:113
169432610,7sleep01265999cyclictest11:35:230
12662996128,5cyclictest41-21ksoftirqd/309:40:123
12662996025,7cyclictest41-21ksoftirqd/311:05:243
118452600,7sleep21266199cyclictest08:10:252
12662995929,4cyclictest41-21ksoftirqd/312:00:263
12662995927,7cyclictest41-21ksoftirqd/310:20:123
12662995927,7cyclictest41-21ksoftirqd/308:35:123
12662995926,7cyclictest41-21ksoftirqd/311:00:133
12662995830,11cyclictest41-21ksoftirqd/310:35:193
12662995725,4cyclictest41-21ksoftirqd/312:10:013
12662995526,8cyclictest41-21ksoftirqd/311:10:213
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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