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2026-08-14 - 00:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Thu Aug 13, 2026 12:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591203170,22phc2sys0-21swapper/307:05:573
56972199167,21sleep20-21swapper/207:06:282
507981990,170rtkit-daemon0-21swapper/007:08:460
56962195162,22sleep10-21swapper/107:06:271
1385918363,11phc2sys0-21swapper/307:10:013
296442610,4sleep029647-21timerandwakeup12:15:270
138491580,8ptp4l401ktimersoftd/311:18:523
60822560,2sleep20-21swapper/211:30:132
119892550,3sleep00-21swapper/009:30:190
138491530,8ptp4l401ktimersoftd/309:22:263
138491520,1ptp4l401ktimersoftd/312:26:393
315972480,4sleep031602-21missed_timers12:20:210
6264994741,4cyclictest30383-21awk10:10:011
626399471,43cyclictest13411-21grep08:30:000
138491450,0ptp4l401ktimersoftd/312:31:023
138491430,0ptp4l401ktimersoftd/311:22:243
138491430,0ptp4l401ktimersoftd/309:37:413
626399426,7cyclictest9-21ksoftirqd/010:45:190
138491420,0ptp4l401ktimersoftd/310:53:283
138491420,0ptp4l401ktimersoftd/310:30:143
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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