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2026-06-18 - 21:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Thu Jun 18, 2026 12:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1305822410,16sleep30-21swapper/307:05:233
136642203169,22sleep10-21swapper/107:09:081
136402203170,22sleep20-21swapper/207:08:502
135762201168,22sleep00-21swapper/007:08:000
1189621440,6sleep31403599cyclictest09:15:143
1148921410,2sleep11403399cyclictest10:20:111
28722820,2sleep12873-21mailstats07:50:251
1403299719,18cyclictest22255-21latency10:40:190
138491650,1ptp4l391rcuc/309:10:243
93382550,2sleep29339-21grep11:20:142
138491550,1ptp4l401ktimersoftd/309:22:553
322072540,4sleep1231rcuc/112:05:221
264202520,2sleep20-21swapper/207:35:132
50798470,2rtkit-daemon0-21swapper/107:32:251
50798470,10rtkit-daemon0-21swapper/112:00:261
138491440,0ptp4l401ktimersoftd/307:38:123
14032994312,18cyclictest22079-21cut09:35:180
138491430,0ptp4l401ktimersoftd/311:35:273
138491430,0ptp4l401ktimersoftd/311:10:263
138491430,0ptp4l401ktimersoftd/308:30:043
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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