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2026-08-07 - 04:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Fri Aug 07, 2026 00:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591220153,23phc2sys0-21swapper/319:05:303
301872203170,22sleep00-21swapper/019:06:400
302422202168,22sleep20-21swapper/219:07:192
301882201168,22sleep10-21swapper/119:06:411
3126821810,6sleep33089399cyclictest21:20:183
1652821550,7sleep03089099cyclictest00:05:190
154162760,2sleep20-21swapper/200:05:012
269952610,2sleep00-21swapper/021:10:200
213042600,2sleep20-21swapper/200:15:162
189952580,5sleep233-21ksoftirqd/219:50:142
214302570,5sleep321436-21irqrtprio23:10:183
214302570,5sleep321436-21irqrtprio23:10:183
138491550,1ptp4l401ktimersoftd/321:30:273
3089199470,45cyclictest0-21swapper/121:30:231
30890994740,4cyclictest20306-21cron23:10:000
3089199450,43cyclictest0-21swapper/119:40:141
3089199450,43cyclictest0-21swapper/119:40:141
138491430,0ptp4l401ktimersoftd/300:07:363
30892994237,3cyclictest33-21ksoftirqd/222:00:002
138491420,0ptp4l401ktimersoftd/319:36:173
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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