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2026-08-12 - 23:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Wed Aug 12, 2026 12:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591205171,23phc2sys0-21swapper/307:06:143
189582204171,22sleep20-21swapper/207:07:102
188752203169,22sleep10-21swapper/107:06:041
190122200167,22sleep00-21swapper/007:07:450
1409421690,4sleep125-21ksoftirqd/110:14:551
1385918263,10phc2sys0-21swapper/307:10:003
1385918263,10phc2sys0-21swapper/307:10:003
138491650,1ptp4l401ktimersoftd/312:36:273
76592610,4sleep21948199cyclictest07:50:142
150222590,2sleep20-21swapper/208:05:142
138491530,1ptp4l401ktimersoftd/308:43:383
19480994943,3cyclictest16654-21latency_hist09:15:001
19482994641,3cyclictest3904-21cron12:05:003
138491430,1ptp4l391rcuc/309:05:563
138491430,0ptp4l401ktimersoftd/312:10:033
19481994236,3cyclictest33-21ksoftirqd/211:00:012
19479994237,3cyclictest12752-21fschecks_count08:00:170
138491420,0ptp4l401ktimersoftd/308:21:453
19481994130,9cyclictest33-21ksoftirqd/210:10:232
1948199412,36cyclictest23556-21switchtime09:25:242
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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