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2026-05-02 - 01:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Fri May 01, 2026 12:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
207282233166,22sleep00-21swapper/007:08:090
138591204170,23phc2sys0-21swapper/307:08:343
206382201169,21sleep20-21swapper/207:06:582
206472200167,22sleep10-21swapper/107:07:061
134991970,9getstats0-21swapper/310:45:493
21171996227,4cyclictest25-21ksoftirqd/108:50:001
2117299611,3cyclictest1319-21snmpd09:52:432
138491610,1ptp4l401ktimersoftd/308:18:373
21171996025,4cyclictest25-21ksoftirqd/112:20:011
138491590,0ptp4l401ktimersoftd/307:58:493
21170995829,4cyclictest9-21ksoftirqd/012:20:130
163062580,3sleep00-21swapper/008:05:130
21170995726,3cyclictest9-21ksoftirqd/012:30:010
21171995623,9cyclictest25-21ksoftirqd/107:20:201
21170995627,3cyclictest9-21ksoftirqd/009:30:270
21171995526,4cyclictest25-21ksoftirqd/110:35:191
21170995526,4cyclictest9-21ksoftirqd/007:35:140
21170995525,4cyclictest9-21ksoftirqd/012:35:210
60792540,1sleep10-21swapper/111:00:141
21171995423,4cyclictest25-21ksoftirqd/112:20:121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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