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2026-06-27 - 04:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sat Jun 27, 2026 00:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
327402229163,22sleep30-21swapper/319:09:133
325122204170,23sleep10-21swapper/119:06:141
3132203169,22sleep20-21swapper/219:09:462
325432202169,22sleep00-21swapper/019:06:380
1687521440,5sleep366399cyclictest00:00:143
997121360,5sleep366399cyclictest23:45:183
33328061,10sleep10-21swapper/119:10:001
1385916854,8phc2sys0-21swapper/319:10:003
138491630,1ptp4l401ktimersoftd/320:57:163
661996023,8cyclictest25-21ksoftirqd/123:05:261
138491600,1ptp4l401ktimersoftd/323:18:443
661995820,10cyclictest25-21ksoftirqd/122:40:251
661995630,7cyclictest25-21ksoftirqd/119:30:121
661995627,8cyclictest25-21ksoftirqd/121:40:141
661995623,6cyclictest25-21ksoftirqd/100:15:131
661995622,4cyclictest25-21ksoftirqd/121:00:151
138491550,1ptp4l401ktimersoftd/319:50:253
661995426,3cyclictest25-21ksoftirqd/123:49:241
661995425,3cyclictest25-21ksoftirqd/122:22:141
661995423,8cyclictest25-21ksoftirqd/122:35:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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