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2026-01-30 - 15:22
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Fri Jan 30, 2026 12:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591232166,22phc2sys0-21swapper/307:06:183
324342203169,22sleep10-21swapper/107:05:011
20902201168,22sleep20-21swapper/207:07:442
20362198166,20sleep00-21swapper/007:07:010
2072321570,6sleep3261699cyclictest11:00:203
2567621480,2sleep00-21swapper/007:55:150
2614997326,4cyclictest25-21ksoftirqd/109:20:001
2614997237,4cyclictest25-21ksoftirqd/109:00:001
2614996835,5cyclictest25-21ksoftirqd/108:35:011
2614996618,10cyclictest25-21ksoftirqd/107:45:191
2614996535,4cyclictest25-21ksoftirqd/108:25:001
2613996532,4cyclictest9-21ksoftirqd/008:40:230
2614996436,9cyclictest25-21ksoftirqd/112:00:001
2614996424,5cyclictest25-21ksoftirqd/109:30:201
2614996230,4cyclictest25-21ksoftirqd/111:00:141
2613996222,5cyclictest9-21ksoftirqd/009:50:250
2614996128,4cyclictest25-21ksoftirqd/108:45:171
2614996126,8cyclictest25-21ksoftirqd/109:58:301
2614996125,12cyclictest25-21ksoftirqd/111:10:121
2616996027,2cyclictest41-21ksoftirqd/308:59:293
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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