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2026-08-19 - 11:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Wed Aug 19, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
310382204169,23sleep30-21swapper/319:08:513
308292203171,21sleep10-21swapper/119:06:081
309272202168,22sleep20-21swapper/219:07:262
310402201167,22sleep00-21swapper/019:08:520
3048821450,6sleep23142199cyclictest20:10:282
671121370,3sleep13142099cyclictest22:40:141
21862750,25sleep09-21ksoftirqd/021:25:200
31421996931,7cyclictest33-21ksoftirqd/222:05:262
31421996535,4cyclictest33-21ksoftirqd/219:54:592
31421996435,4cyclictest33-21ksoftirqd/221:15:012
31421996331,7cyclictest33-21ksoftirqd/222:50:252
31421996231,4cyclictest33-21ksoftirqd/219:25:132
31421996229,6cyclictest33-21ksoftirqd/222:40:002
31421996229,6cyclictest33-21ksoftirqd/221:50:132
31421996225,4cyclictest33-21ksoftirqd/223:20:222
3142299613,10cyclictest30804-21ls00:35:013
3142299613,10cyclictest30804-21ls00:35:003
31421996131,5cyclictest33-21ksoftirqd/220:05:202
31421996129,6cyclictest33-21ksoftirqd/221:40:152
31421996129,6cyclictest33-21ksoftirqd/219:45:262
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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