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2026-03-20 - 19:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Fri Mar 20, 2026 12:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591229162,22phc2sys0-21swapper/307:05:503
251782201166,23sleep20-21swapper/207:07:292
231652201166,23sleep00-21swapper/007:05:110
250372198166,21sleep10-21swapper/107:05:401
1049321640,7sleep32567699cyclictest07:43:363
2714221530,5sleep32567699cyclictest07:10:243
1649021500,6sleep02567399cyclictest12:15:200
260332870,1sleep00-21swapper/012:35:180
53062570,2sleep20-21swapper/211:54:592
37032570,6sleep32567699cyclictest07:30:133
138491540,1ptp4l401ktimersoftd/308:39:363
2567499531,10cyclictest30355-21latency_hist09:30:011
138491510,0ptp4l401ktimersoftd/311:54:273
138491480,1ptp4l401ktimersoftd/309:53:173
25675994526,3cyclictest33-21ksoftirqd/212:10:122
2567599450,2cyclictest0-21swapper/211:00:232
2567599440,2cyclictest0-21swapper/211:10:232
2567499441,40cyclictest27696-21apt10:30:011
25676994330,11cyclictest41-21ksoftirqd/311:25:013
25675994316,25cyclictest0-21swapper/208:35:332
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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