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2026-01-20 - 12:58
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Tue Jan 20, 2026 00:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
28172203170,22sleep20-21swapper/219:07:412
28162202167,23sleep10-21swapper/119:07:391
138591202168,23phc2sys0-21swapper/319:05:503
28402200166,22sleep00-21swapper/019:08:000
19022570,2sleep10-21swapper/123:25:141
3449995323,3cyclictest25-21ksoftirqd/122:55:181
3449995322,4cyclictest25-21ksoftirqd/123:00:121
138491530,1ptp4l401ktimersoftd/323:14:063
3449995123,4cyclictest25-21ksoftirqd/121:10:121
3449995119,4cyclictest25-21ksoftirqd/123:35:001
3449995021,4cyclictest25-21ksoftirqd/100:30:251
3449995019,4cyclictest25-21ksoftirqd/120:50:231
3449995019,3cyclictest25-21ksoftirqd/123:10:221
3449995016,4cyclictest25-21ksoftirqd/121:55:011
3449994920,3cyclictest25-21ksoftirqd/123:45:231
3449994916,7cyclictest25-21ksoftirqd/100:20:191
138491490,1ptp4l401ktimersoftd/321:42:123
138491490,1ptp4l401ktimersoftd/321:42:123
3449994719,5cyclictest25-21ksoftirqd/100:35:141
3449994719,3cyclictest25-21ksoftirqd/119:40:191
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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