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2026-08-31 - 05:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Mon Aug 31, 2026 00:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591236168,23phc2sys0-21swapper/319:08:053
182742206174,21sleep20-21swapper/219:07:532
181352201167,22sleep00-21swapper/019:06:090
181312201167,23sleep10-21swapper/119:06:071
325221530,1sleep30-21swapper/300:05:003
1844029069,11sleep20-21swapper/219:10:022
134991770,7getstats1873599cyclictest00:24:013
18733997132,3cyclictest25-21ksoftirqd/122:25:221
1873599627,11cyclictest23044-21cat23:40:003
258392610,4sleep0101ktimersoftd/022:40:000
1873599608,11cyclictest11821-21cut21:05:203
1873599595,11cyclictest16510-21df_abs22:20:153
1873599586,12cyclictest19800-21cut21:20:263
1873599586,11cyclictest24112-21sed20:25:143
1873599586,11cyclictest14885-21cut22:15:223
1873599577,16cyclictest25885-21/usr/sbin/munin23:45:203
1873599576,17cyclictest8363-21latency_hist22:05:013
138491560,1ptp4l25272-21wc19:20:283
1873599556,10cyclictest22834-21sed19:15:243
138491550,1ptp4l391rcuc/323:20:273
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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