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2026-08-16 - 20:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sun Aug 16, 2026 12:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
205282204170,22sleep10-21swapper/107:06:181
138591204170,22phc2sys0-21swapper/307:07:393
206922202170,21sleep20-21swapper/207:08:242
205492202169,22sleep00-21swapper/007:06:330
2386021570,6sleep22111499cyclictest11:35:132
2701721440,4sleep22111499cyclictest07:20:192
2082128263,10sleep20-21swapper/207:10:012
2111299774,31cyclictest12598-21cut09:00:200
2111299701,27cyclictest0-21swapper/008:25:010
2111299700,32cyclictest18600-21/usr/sbin/munin11:25:180
2111299631,24cyclictest30912-21/usr/sbin/munin11:50:150
87752560,7sleep22111499cyclictest11:05:122
21114995623,4cyclictest33-21ksoftirqd/208:55:012
228892550,4sleep10-21swapper/108:15:301
21114995514,4cyclictest33-21ksoftirqd/211:30:262
123812550,2sleep30-21swapper/312:15:253
21114995422,8cyclictest33-21ksoftirqd/210:35:002
21114995413,10cyclictest33-21ksoftirqd/210:10:002
21114995313,9cyclictest33-21ksoftirqd/207:50:132
252052510,1sleep00-21swapper/010:30:240
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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