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2026-05-23 - 13:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sat May 23, 2026 00:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591212167,33phc2sys0-21swapper/319:08:593
232052202169,21sleep20-21swapper/219:08:372
230652202167,23sleep10-21swapper/119:06:471
231212199166,22sleep00-21swapper/019:07:300
2189021510,6sleep02360599cyclictest00:25:260
205232850,3sleep30-21swapper/323:20:183
2331428262,11sleep10-21swapper/119:10:001
290932770,6sleep02360599cyclictest20:25:170
152812520,4sleep215286-21cpuspeed_turbos00:15:142
324652460,2sleep10-21swapper/119:25:201
23607994236,3cyclictest8470-21cron20:50:002
23607994134,5cyclictest33-21ksoftirqd/223:55:002
23608994036,2cyclictest41-21ksoftirqd/323:55:013
23607994035,3cyclictest33-21ksoftirqd/221:51:082
138491400,1ptp4l401ktimersoftd/321:53:073
138491400,0ptp4l401ktimersoftd/300:20:213
138491390,0ptp4l401ktimersoftd/322:39:563
23608993733,3cyclictest41-21ksoftirqd/322:54:593
23608993732,3cyclictest41-21ksoftirqd/321:00:003
23607993731,4cyclictest33-21ksoftirqd/219:49:172
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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