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2026-03-27 - 18:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Fri Mar 27, 2026 12:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591203169,23phc2sys0-21swapper/307:06:403
87992202168,23sleep10-21swapper/107:07:471
86732202167,23sleep00-21swapper/007:06:090
86702201167,22sleep20-21swapper/207:06:072
1791021360,6sleep1927199cyclictest09:35:211
1385918762,16phc2sys0-21swapper/307:10:003
138491690,1ptp4l401ktimersoftd/309:16:333
145272680,6sleep3401ktimersoftd/310:35:003
20942590,7sleep3927399cyclictest08:00:123
99342520,2sleep20-21swapper/209:20:142
138491470,1ptp4l401ktimersoftd/312:20:153
9271994636,6cyclictest25-21ksoftirqd/109:45:121
138491460,0ptp4l401ktimersoftd/308:11:143
927199450,1cyclictest0-21swapper/108:00:121
927199440,42cyclictest0-21swapper/108:57:421
138491440,0ptp4l401ktimersoftd/308:38:563
927199430,2cyclictest0-21swapper/108:40:031
138491430,1ptp4l401ktimersoftd/310:41:463
138491420,0ptp4l401ktimersoftd/311:20:273
138491420,0ptp4l401ktimersoftd/310:20:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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