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2026-06-28 - 13:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sun Jun 28, 2026 00:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591206172,23phc2sys0-21swapper/319:07:163
145932204170,22sleep10-21swapper/119:06:251
148112202169,22sleep20-21swapper/219:09:122
147472201168,21sleep00-21swapper/019:08:210
138491610,1ptp4l401ktimersoftd/321:50:513
115722540,2sleep20-21swapper/200:25:232
81162530,2sleep30-21swapper/300:20:143
1516699533,7cyclictest23235-21df_abs19:25:160
138491530,1ptp4l401ktimersoftd/321:38:223
15166995021,7cyclictest9-21ksoftirqd/020:19:350
138491500,1ptp4l401ktimersoftd/320:22:153
1516699494,7cyclictest16675-21timerwakeupswit22:25:260
15166994920,3cyclictest9-21ksoftirqd/022:51:470
15167994841,4cyclictest29389-21sshd22:53:061
138491480,0ptp4l401ktimersoftd/300:33:413
1516699474,6cyclictest31551-21mailstats21:50:250
1516699472,5cyclictest9-21ksoftirqd/000:00:010
15168994633,9cyclictest33-21ksoftirqd/220:15:222
1516699465,6cyclictest2044-21awk00:05:280
1516899424,5cyclictest33-21ksoftirqd/221:55:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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