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2026-07-07 - 03:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Mon Jul 06, 2026 12:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591234205,19phc2sys0-21swapper/307:09:593
195552201167,22sleep20-21swapper/207:08:002
195802200166,22sleep00-21swapper/007:08:180
195592200166,23sleep10-21swapper/107:08:031
720821650,6sleep02001199cyclictest08:55:010
138491670,1ptp4l401ktimersoftd/307:24:103
138491600,1ptp4l401ktimersoftd/312:06:463
273102500,2sleep30-21swapper/308:30:003
134991500,1getstats0-21swapper/311:13:563
230722490,3sleep20-21swapper/210:30:142
20012994942,4cyclictest19716-21sh08:15:001
134991490,9getstats0-21swapper/311:18:563
101592480,2sleep1241ktimersoftd/110:05:101
188812470,3sleep30-21swapper/312:30:213
138491460,0ptp4l401ktimersoftd/310:55:443
20012994517,26cyclictest22449-21kworker/1:110:56:051
20011994538,4cyclictest24644-21cron08:25:000
2001199452,6cyclictest9-21ksoftirqd/012:00:290
138491440,0ptp4l401ktimersoftd/312:16:533
138491420,0ptp4l401ktimersoftd/311:44:503
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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