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2026-08-13 - 12:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Thu Aug 13, 2026 00:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591206170,24phc2sys0-21swapper/319:05:073
26972203169,22sleep20-21swapper/219:08:322
26912202169,22sleep10-21swapper/119:08:271
27492201169,21sleep00-21swapper/019:09:100
282228363,11sleep20-21swapper/219:10:002
138491650,1ptp4l401ktimersoftd/300:36:293
165912610,1sleep00-21swapper/022:50:220
53812600,2sleep00-21swapper/022:30:110
195432570,6sleep3311699cyclictest19:40:253
3116995523,7cyclictest41-21ksoftirqd/323:59:593
29132530,5sleep22917-21cpuspeed_turbos21:20:142
176242530,4sleep3391rcuc/320:45:003
3116995233,3cyclictest41-21ksoftirqd/322:55:223
208152520,2sleep00-21swapper/019:45:160
3116995128,2cyclictest41-21ksoftirqd/319:10:263
3116995018,3cyclictest41-21ksoftirqd/322:50:253
3116994921,4cyclictest41-21ksoftirqd/321:45:243
3116994914,4cyclictest41-21ksoftirqd/321:34:593
165122490,2sleep20-21swapper/221:45:202
3116994717,7cyclictest41-21ksoftirqd/300:10:263
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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