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2026-09-13 - 08:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sun Sep 13, 2026 00:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
113132204170,22sleep30-21swapper/319:07:563
113102203170,21sleep00-21swapper/019:07:510
113422201169,21sleep20-21swapper/219:08:182
111732200167,22sleep10-21swapper/119:06:131
138491660,1ptp4l401ktimersoftd/323:25:253
28402630,6sleep11191599cyclictest00:15:221
11916996327,5cyclictest33-21ksoftirqd/220:05:012
11916996327,5cyclictest33-21ksoftirqd/220:05:002
11916996230,6cyclictest33-21ksoftirqd/220:35:232
11916996129,6cyclictest33-21ksoftirqd/220:25:162
11916996127,10cyclictest33-21ksoftirqd/222:45:002
28652600,3sleep32867-21irqrtprio22:05:193
11916996025,3cyclictest33-21ksoftirqd/221:30:272
11916996023,3cyclictest33-21ksoftirqd/221:40:092
11916995927,6cyclictest33-21ksoftirqd/220:10:012
11916995828,9cyclictest33-21ksoftirqd/219:20:202
11916995828,5cyclictest33-21ksoftirqd/223:10:162
11916995826,9cyclictest33-21ksoftirqd/220:15:282
11916995725,5cyclictest33-21ksoftirqd/222:20:162
11916995722,5cyclictest33-21ksoftirqd/222:35:202
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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