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2026-06-08 - 02:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sun Jun 07, 2026 12:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591234166,24phc2sys0-21swapper/307:09:453
307322231167,22sleep10-21swapper/107:09:061
307282204171,22sleep20-21swapper/207:09:042
304942202168,23sleep00-21swapper/007:06:010
138491660,1ptp4l4372-21diskstats08:25:143
3124999650,27cyclictest15211-21grep10:55:230
3124999640,19cyclictest31799-21df_inode07:10:150
138491610,1ptp4l401ktimersoftd/311:53:113
3124999596,17cyclictest32308-21missed_timers12:35:210
138491590,1ptp4l401ktimersoftd/309:50:173
3124999580,26cyclictest9362-21df_abs09:40:130
138491580,1ptp4l401ktimersoftd/311:15:203
138491570,1ptp4l401ktimersoftd/307:45:203
191812550,3sleep20-21swapper/211:05:152
3124999540,20cyclictest1099-21/usr/sbin/munin11:35:240
31250994819,27cyclictest0-21swapper/109:21:031
18042480,2sleep10-21swapper/108:20:151
99992470,2sleep10-21swapper/107:30:201
3125199470,4cyclictest30300-21ptp4l10:20:232
138491450,0ptp4l401ktimersoftd/309:33:073
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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