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2026-06-16 - 18:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Tue Jun 16, 2026 12:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591206175,21phc2sys0-21swapper/307:06:583
173422202172,20sleep20-21swapper/207:07:592
173362202168,23sleep10-21swapper/107:07:531
174252200168,21sleep00-21swapper/007:08:580
185632590,2sleep10-21swapper/112:35:161
138491590,1ptp4l401ktimersoftd/308:10:433
138491580,1ptp4l401ktimersoftd/309:49:433
138491570,1ptp4l401ktimersoftd/308:01:393
138491560,1ptp4l401ktimersoftd/307:18:113
301232530,2sleep00-21swapper/008:40:110
103352500,4sleep21780199cyclictest12:20:012
17801994917,6cyclictest33-21ksoftirqd/211:55:152
303232480,27sleep125-21ksoftirqd/107:35:011
17801994815,8cyclictest33-21ksoftirqd/209:45:172
17801994720,6cyclictest33-21ksoftirqd/211:20:212
17801994717,6cyclictest33-21ksoftirqd/212:30:162
17801994717,6cyclictest33-21ksoftirqd/212:30:162
17801994716,6cyclictest33-21ksoftirqd/208:30:142
17801994715,7cyclictest33-21ksoftirqd/209:30:012
17801994712,6cyclictest33-21ksoftirqd/207:35:202
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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