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2026-05-22 - 00:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Thu May 21, 2026 12:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
188032235171,21sleep10-21swapper/107:08:101
138591205171,23phc2sys0-21swapper/307:06:283
186022203170,22sleep20-21swapper/207:05:342
167322202168,22sleep00-21swapper/007:05:080
1760721400,4sleep31924599cyclictest08:10:133
19245996232,2cyclictest41-21ksoftirqd/310:00:133
19262590,1sleep00-21swapper/008:45:020
1924299595,21cyclictest16662-21taskset08:06:570
19245995620,3cyclictest41-21ksoftirqd/312:40:003
228452530,3sleep341-21ksoftirqd/307:15:223
19245995221,4cyclictest41-21ksoftirqd/312:15:273
19245995219,6cyclictest41-21ksoftirqd/308:30:143
19245995121,7cyclictest41-21ksoftirqd/311:05:013
1924299512,18cyclictest0-21swapper/010:27:500
19245995029,3cyclictest41-21ksoftirqd/309:10:163
19245995023,7cyclictest41-21ksoftirqd/310:55:263
19245995023,7cyclictest41-21ksoftirqd/310:55:263
19245995019,4cyclictest41-21ksoftirqd/309:50:183
19245995019,3cyclictest41-21ksoftirqd/307:10:173
19245995016,4cyclictest41-21ksoftirqd/312:25:153
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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