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2026-02-18 - 16:09
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Wed Feb 18, 2026 12:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591205159,34phc2sys0-21swapper/307:05:333
49292201168,22sleep10-21swapper/107:06:161
50952200167,22sleep00-21swapper/007:08:190
49902199167,21sleep20-21swapper/207:07:042
522328160,12sleep00-21swapper/007:10:000
5517996622,4cyclictest33-21ksoftirqd/211:25:212
5517996427,8cyclictest33-21ksoftirqd/212:35:222
138491620,52ptp4l0-21swapper/307:10:013
5517996130,7cyclictest33-21ksoftirqd/210:40:152
5517996129,6cyclictest33-21ksoftirqd/207:20:012
5517996129,5cyclictest33-21ksoftirqd/212:25:012
5517996127,9cyclictest33-21ksoftirqd/210:35:202
5517996030,7cyclictest33-21ksoftirqd/207:20:122
5517996029,3cyclictest33-21ksoftirqd/212:00:002
5517996025,8cyclictest33-21ksoftirqd/212:30:232
5517995930,7cyclictest33-21ksoftirqd/209:00:132
5517995930,6cyclictest33-21ksoftirqd/209:55:002
277472590,4sleep30-21swapper/312:10:173
5517995827,10cyclictest33-21ksoftirqd/210:00:252
5517995826,4cyclictest33-21ksoftirqd/210:45:162
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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