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2026-07-08 - 17:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Wed Jul 08, 2026 12:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
263862205172,21sleep00-21swapper/007:05:400
265382202168,23sleep30-21swapper/307:07:403
266732200166,23sleep10-21swapper/107:09:191
265472200167,22sleep20-21swapper/207:07:472
997421520,6sleep02701999cyclictest10:55:150
997421520,6sleep02701999cyclictest10:55:150
174732700,2sleep00-21swapper/011:10:140
77942630,5sleep17797-21irqrtprio10:50:171
89922600,6sleep38993-21ls12:00:003
21702580,3sleep02175-21cpuspeed_turbos07:25:130
2702299551,51cyclictest31540-21cron10:35:013
322052500,4sleep10-21swapper/107:20:131
27020995044,3cyclictest6761-21sh07:35:001
50798460,5rtkit-daemon9472-21apache207:15:213
2672624633,7sleep30-21swapper/307:10:013
138491440,1ptp4l401ktimersoftd/310:40:323
2702299435,3cyclictest41-21ksoftirqd/310:50:273
138491430,0ptp4l401ktimersoftd/308:16:413
138491430,0ptp4l401ktimersoftd/307:40:343
138491430,0ptp4l401ktimersoftd/307:38:053
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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