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2026-07-28 - 10:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Tue Jul 28, 2026 00:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591205141,52phc2sys0-21swapper/319:08:253
115232205171,23sleep20-21swapper/219:08:512
114072204170,23sleep10-21swapper/119:07:211
112662202168,22sleep00-21swapper/019:05:400
691121540,5sleep31196599cyclictest20:04:593
2468721400,4sleep21196499cyclictest20:40:132
138491670,1ptp4l401ktimersoftd/300:15:453
255392650,4sleep00-21swapper/020:40:190
138491630,1ptp4l401ktimersoftd/319:13:453
11962995926,5cyclictest9-21ksoftirqd/019:30:130
11962995826,5cyclictest9-21ksoftirqd/022:05:270
11962995825,5cyclictest9-21ksoftirqd/021:40:120
138491560,1ptp4l401ktimersoftd/322:47:453
1196299566,10cyclictest9-21ksoftirqd/000:40:000
11962995622,5cyclictest9-21ksoftirqd/022:40:240
11962995622,5cyclictest9-21ksoftirqd/019:25:240
1196299556,7cyclictest9-21ksoftirqd/022:22:190
11962995428,7cyclictest9-21ksoftirqd/023:57:310
11962995418,6cyclictest9-21ksoftirqd/019:40:260
53942530,3sleep25397-21irqrtprio21:05:202
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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