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2026-05-06 - 09:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Wed May 06, 2026 00:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591208173,23phc2sys0-21swapper/319:06:343
166172202169,21sleep10-21swapper/119:09:571
165532201168,22sleep00-21swapper/019:09:080
164422200168,21sleep20-21swapper/219:07:412
952621410,7sleep21691599cyclictest23:15:012
1662228763,15sleep10-21swapper/119:10:011
16916996629,4cyclictest41-21ksoftirqd/323:15:003
16916996131,9cyclictest41-21ksoftirqd/323:25:003
16916996130,3cyclictest41-21ksoftirqd/323:15:123
16916996130,3cyclictest41-21ksoftirqd/323:15:123
16916996129,4cyclictest41-21ksoftirqd/320:15:203
194852600,2sleep00-21swapper/023:35:000
16916996028,4cyclictest41-21ksoftirqd/323:45:163
16916995930,8cyclictest41-21ksoftirqd/322:05:123
16916995924,4cyclictest41-21ksoftirqd/321:40:173
16916995921,4cyclictest41-21ksoftirqd/322:57:393
16916995920,4cyclictest41-21ksoftirqd/319:26:303
16916995826,8cyclictest41-21ksoftirqd/300:15:273
16916995826,8cyclictest41-21ksoftirqd/300:15:273
16916995822,4cyclictest41-21ksoftirqd/321:45:463
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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