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2026-05-02 - 10:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sat May 02, 2026 00:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591239170,23phc2sys0-21swapper/319:09:073
178492205170,23sleep10-21swapper/119:09:481
175802202168,23sleep20-21swapper/219:06:222
177552201167,22sleep00-21swapper/019:08:330
18308996910,17cyclictest2496-21sshd00:03:151
18310996837,2cyclictest41-21ksoftirqd/321:55:173
1830899671,21cyclictest25746-21df_abs23:45:141
1830899660,30cyclictest20179-21date23:35:011
18310996431,9cyclictest41-21ksoftirqd/322:05:183
18310996431,7cyclictest41-21ksoftirqd/322:45:013
18310996420,6cyclictest41-21ksoftirqd/323:17:073
1830899640,27cyclictest30397-21date20:40:001
18310996325,8cyclictest41-21ksoftirqd/323:25:143
18310996322,9cyclictest41-21ksoftirqd/321:40:103
18310996223,8cyclictest41-21ksoftirqd/323:40:133
18310996129,9cyclictest41-21ksoftirqd/323:35:173
18310996127,4cyclictest41-21ksoftirqd/321:20:223
1830899610,20cyclictest3036-21chrt20:50:031
18310996028,9cyclictest41-21ksoftirqd/321:30:233
18310996028,8cyclictest41-21ksoftirqd/300:35:173
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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