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2026-06-22 - 17:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Mon Jun 22, 2026 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
46172206171,23sleep30-21swapper/307:08:403
43782202169,22sleep10-21swapper/107:05:321
44962201167,22sleep00-21swapper/007:07:050
44112201168,22sleep20-21swapper/207:05:582
2902421720,7sleep1502499cyclictest07:55:271
1532521710,7sleep3502699cyclictest09:40:153
473128664,12sleep30-21swapper/307:10:003
302682620,6sleep2502599cyclictest12:20:172
113382550,2sleep20-21swapper/210:35:272
187252530,3sleep218728-21processes07:35:222
63582510,2sleep20-21swapper/207:10:222
5024995121,3cyclictest25-21ksoftirqd/110:05:001
8122500,3sleep00-21swapper/010:15:180
5023995043,4cyclictest31924-21cron10:15:000
502699495,6cyclictest41-21ksoftirqd/309:05:133
5026994942,4cyclictest15554-21cut08:35:183
502499499,7cyclictest25-21ksoftirqd/110:15:001
155472490,3sleep115552-21irqrtprio08:35:181
5026994824,8cyclictest41-21ksoftirqd/309:00:183
5024994816,4cyclictest25-21ksoftirqd/107:20:191
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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