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2026-08-11 - 22:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Tue Aug 11, 2026 12:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
48202234168,21sleep20-21swapper/207:06:102
48982207174,22sleep30-21swapper/307:07:113
48512204170,22sleep10-21swapper/107:06:331
48232201166,23sleep00-21swapper/007:06:120
2093621350,2sleep20-21swapper/207:40:162
209332750,2sleep10-21swapper/112:00:151
541799550,25cyclictest26040-21grep10:00:173
541799541,50cyclictest20091-21ls09:50:003
541799530,49cyclictest9873-21unixbench_multi10:30:273
134991520,3getstats13350irq/39-mmc110:20:253
541799500,24cyclictest10309-21grep09:30:133
5415994741,3cyclictest2807-21apt12:30:001
541799460,15cyclictest0-21swapper/312:20:213
5417994526,16cyclictest41-21ksoftirqd/309:40:093
541799431,24cyclictest1319-21snmpd10:17:373
5416994338,3cyclictest7581-21cron11:35:002
138491420,0ptp4l401ktimersoftd/312:12:493
138491420,0ptp4l401ktimersoftd/310:25:503
138491420,0ptp4l401ktimersoftd/308:25:303
138491420,0ptp4l401ktimersoftd/307:52:373
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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