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2026-09-02 - 20:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Wed Sep 02, 2026 12:45:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591210142,24phc2sys0-21swapper/307:09:173
55872207172,23sleep10-21swapper/107:05:591
55552203169,22sleep20-21swapper/207:05:372
36832199167,21sleep00-21swapper/007:05:070
138591133108,14phc2sys0-21swapper/307:10:013
590328262,11sleep00-21swapper/007:10:010
325002680,2sleep30-21swapper/308:00:253
218802590,2sleep00-21swapper/012:00:200
6197995824,8cyclictest41-21ksoftirqd/307:55:183
276212570,2sleep3401ktimersoftd/307:50:263
134991570,6getstats619799cyclictest09:04:213
138491560,1ptp4l401ktimersoftd/311:30:243
6197995527,3cyclictest41-21ksoftirqd/311:55:133
6197995424,4cyclictest41-21ksoftirqd/311:25:193
138491540,1ptp4l401ktimersoftd/307:45:213
6197995225,7cyclictest41-21ksoftirqd/307:35:163
6197995121,3cyclictest41-21ksoftirqd/310:20:143
6197995021,4cyclictest41-21ksoftirqd/311:20:263
6197995015,6cyclictest41-21ksoftirqd/310:54:593
6197994923,7cyclictest41-21ksoftirqd/312:20:153
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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