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2026-07-29 - 23:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Wed Jul 29, 2026 12:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591223163,49phc2sys0-21swapper/307:08:203
138591223163,49phc2sys0-21swapper/307:08:203
9082206172,23sleep10-21swapper/107:08:381
9082206172,23sleep10-21swapper/107:08:371
6612201168,22sleep20-21swapper/207:05:422
6612201168,22sleep20-21swapper/207:05:412
6862199164,23sleep00-21swapper/007:06:000
6862199164,23sleep00-21swapper/007:06:000
1493921190,1sleep10-21swapper/111:55:211
497421170,2sleep30-21swapper/307:15:213
101328562,15sleep30-21swapper/307:10:013
250142660,5sleep125-21ksoftirqd/107:55:231
107372650,2sleep20-21swapper/207:25:282
1309996334,4cyclictest9-21ksoftirqd/010:20:000
1309996130,4cyclictest9-21ksoftirqd/011:55:150
1309995929,4cyclictest9-21ksoftirqd/008:30:250
1309995825,4cyclictest9-21ksoftirqd/011:15:130
1309995733,3cyclictest9-21ksoftirqd/009:15:190
1309995627,4cyclictest9-21ksoftirqd/011:35:140
1309995625,7cyclictest9-21ksoftirqd/008:25:250
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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