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2026-07-09 - 06:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Thu Jul 09, 2026 00:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
12132223162,50sleep10-21swapper/119:06:461
138591204170,23phc2sys0-21swapper/319:06:053
11622201168,22sleep20-21swapper/219:06:072
12222200168,22sleep00-21swapper/019:06:530
3172121570,7sleep1177599cyclictest20:10:121
22752850,5sleep125-21ksoftirqd/119:10:151
1777996831,8cyclictest41-21ksoftirqd/319:15:003
1777996531,7cyclictest41-21ksoftirqd/320:30:003
1777996433,7cyclictest41-21ksoftirqd/320:50:013
1777996431,4cyclictest41-21ksoftirqd/322:41:223
1777996431,4cyclictest41-21ksoftirqd/322:41:223
1777996430,8cyclictest41-21ksoftirqd/322:16:173
1777996332,4cyclictest41-21ksoftirqd/323:10:153
1777996330,9cyclictest41-21ksoftirqd/322:25:013
177599630,23cyclictest16198-21taskset20:42:571
1777996230,12cyclictest41-21ksoftirqd/322:10:173
1777996230,12cyclictest41-21ksoftirqd/322:10:173
1777996229,5cyclictest41-21ksoftirqd/320:20:193
1777996229,4cyclictest41-21ksoftirqd/323:25:113
1777996229,4cyclictest41-21ksoftirqd/321:35:183
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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