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2026-03-13 - 13:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Fri Mar 13, 2026 00:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
287892246203,33sleep20-21swapper/219:08:592
138591228162,22phc2sys0-21swapper/319:07:273
286952205171,23sleep10-21swapper/119:07:451
287252199166,22sleep00-21swapper/019:08:080
812621570,2sleep30-21swapper/320:35:243
29319996624,7cyclictest9-21ksoftirqd/023:10:210
29319996624,7cyclictest9-21ksoftirqd/023:10:200
29319996623,4cyclictest9-21ksoftirqd/021:39:590
29319996122,7cyclictest9-21ksoftirqd/023:26:530
2932099607,6cyclictest25-21ksoftirqd/100:07:081
29319996022,5cyclictest9-21ksoftirqd/020:05:000
29319996021,6cyclictest9-21ksoftirqd/022:41:090
29319996020,7cyclictest9-21ksoftirqd/021:40:270
29319996019,9cyclictest9-21ksoftirqd/020:35:260
29319995923,4cyclictest9-21ksoftirqd/022:53:030
29319995923,3cyclictest9-21ksoftirqd/023:36:480
29319995922,4cyclictest9-21ksoftirqd/021:46:490
29319995921,4cyclictest9-21ksoftirqd/022:29:040
29319995825,9cyclictest9-21ksoftirqd/022:35:180
29319995822,6cyclictest9-21ksoftirqd/022:17:290
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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