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2026-06-23 - 05:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Tue Jun 23, 2026 00:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591233166,22phc2sys0-21swapper/319:08:443
255462205170,23sleep10-21swapper/119:09:281
255552203170,22sleep00-21swapper/019:09:350
254082202170,21sleep20-21swapper/219:07:402
2604721650,6sleep12588299cyclictest20:15:101
497321380,4sleep22588399cyclictest21:40:242
2423921370,2sleep00-21swapper/000:30:190
1114321250,4sleep22588399cyclictest00:05:132
2588399641,30cyclictest5994-21/usr/sbin/munin21:45:072
190282590,2sleep10-21swapper/123:15:181
2588399580,26cyclictest22631-21grep21:10:272
135191580,1getstats0-21swapper/323:39:583
2588399527,21cyclictest27463-21gzip20:15:232
135191500,7getstats2588499cyclictest22:24:583
138491480,1ptp4l401ktimersoftd/322:52:333
138491470,1ptp4l401ktimersoftd/300:04:393
138491440,0ptp4l401ktimersoftd/321:46:443
138491430,0ptp4l401ktimersoftd/323:31:063
138491430,0ptp4l401ktimersoftd/321:00:473
2588399422,6cyclictest121rcu_preempt22:00:152
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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