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2026-05-04 - 08:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Mon May 04, 2026 00:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
18232206170,24sleep00-21swapper/019:08:460
138591204171,22phc2sys0-21swapper/319:05:033
18582201169,21sleep20-21swapper/219:09:132
16512201168,22sleep10-21swapper/119:06:371
1195921380,6sleep2222099cyclictest20:35:002
203442790,5sleep220345-21irqrtprio19:45:172
197722630,6sleep2222099cyclictest20:50:122
2218996225,5cyclictest9-21ksoftirqd/022:55:160
2218996222,6cyclictest9-21ksoftirqd/023:30:170
44042610,3sleep30-21swapper/320:20:013
2218996124,6cyclictest9-21ksoftirqd/021:20:250
2218996124,6cyclictest9-21ksoftirqd/020:20:220
2218996124,5cyclictest9-21ksoftirqd/021:30:160
2218996124,5cyclictest9-21ksoftirqd/019:35:240
2218996124,5cyclictest9-21ksoftirqd/000:05:220
2218996123,6cyclictest9-21ksoftirqd/020:25:260
2218996123,5cyclictest9-21ksoftirqd/021:45:140
2218996123,5cyclictest9-21ksoftirqd/020:05:240
2218996123,5cyclictest9-21ksoftirqd/019:20:130
2218996122,6cyclictest9-21ksoftirqd/019:30:130
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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