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2026-06-21 - 15:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sun Jun 21, 2026 00:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
60122790,57sleep10-21swapper/119:05:001
29812229162,22sleep00-21swapper/019:09:110
28712211167,32sleep20-21swapper/219:07:442
138591205171,23phc2sys0-21swapper/319:05:543
2378621480,5sleep1333799cyclictest19:50:191
257142670,5sleep2333899cyclictest00:15:132
138491620,1ptp4l401ktimersoftd/322:47:203
50798610,1rtkit-daemon0-21swapper/100:15:291
165022600,3sleep10-21swapper/120:40:171
138491590,1ptp4l401ktimersoftd/321:19:093
184042580,2sleep00-21swapper/000:00:150
1385915637,11phc2sys0-21swapper/319:10:013
3338995216,34cyclictest0-21swapper/221:33:452
170892510,2sleep00-21swapper/023:55:250
138491500,0ptp4l401ktimersoftd/323:06:373
135191470,6getstats333999cyclictest20:59:283
138491460,0ptp4l401ktimersoftd/322:02:593
3339994527,16cyclictest41-21ksoftirqd/323:25:003
3338994526,16cyclictest33-21ksoftirqd/220:26:232
182012450,4sleep2311rcuc/200:00:132
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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