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2026-07-24 - 20:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Fri Jul 24, 2026 12:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
55062207172,23sleep30-21swapper/307:06:223
56852202169,22sleep00-21swapper/007:08:420
56302202169,22sleep20-21swapper/207:07:592
55162202169,22sleep10-21swapper/107:06:291
300322650,2sleep20-21swapper/209:00:202
6087996432,7cyclictest33-21ksoftirqd/211:55:002
608899635,11cyclictest23097-21grep10:55:253
6087996332,9cyclictest33-21ksoftirqd/208:40:012
58382630,4sleep15839-21unixbench_singl11:25:281
6087996230,6cyclictest33-21ksoftirqd/211:40:222
6087996230,6cyclictest33-21ksoftirqd/211:40:222
138491620,1ptp4l0-21swapper/312:34:313
608899615,12cyclictest29764-21irqrtprio11:10:183
608899605,10cyclictest23693-21latency_hist09:54:593
608899604,12cyclictest6458-21cat10:25:003
608899604,12cyclictest11183-21cat09:29:593
608899604,11cyclictest24776-21missed_timers07:45:223
6087996027,6cyclictest33-21ksoftirqd/211:30:242
608899595,11cyclictest13542-21sshd09:34:393
608899594,16cyclictest20225-21awk07:35:273
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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