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2025-11-24 - 17:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Mon Nov 24, 2025 12:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
201402206172,22sleep30-21swapper/307:05:113
221272202167,23sleep20-21swapper/207:06:492
221262201167,22sleep10-21swapper/107:06:491
220632198162,24sleep00-21swapper/007:05:590
1332021610,5sleep32266899cyclictest12:15:143
427291670,2ptp4l401ktimersoftd/310:20:253
427291560,1ptp4l401ktimersoftd/307:35:223
151212510,3sleep30-21swapper/310:10:013
219252500,2sleep10-21swapper/112:30:191
427291490,1ptp4l401ktimersoftd/307:10:023
314532490,3sleep20-21swapper/211:45:192
22668994639,4cyclictest41-21ksoftirqd/311:24:593
22667994617,27cyclictest0-21swapper/210:25:172
427291440,0ptp4l401ktimersoftd/308:17:123
427291430,0ptp4l401ktimersoftd/311:45:313
427291430,0ptp4l401ktimersoftd/310:04:163
22668994339,2cyclictest41-21ksoftirqd/312:40:003
2266799431,2cyclictest0-21swapper/207:40:182
427291420,0ptp4l401ktimersoftd/308:20:293
22668994237,3cyclictest41-21ksoftirqd/312:25:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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