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2026-05-03 - 00:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sat May 02, 2026 12:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
131812205172,22sleep10-21swapper/107:08:481
130332204171,22sleep30-21swapper/307:06:533
132622202168,23sleep20-21swapper/207:09:482
132052202170,21sleep00-21swapper/007:09:060
3024821660,6sleep01372799cyclictest07:40:260
1400721560,6sleep11372999cyclictest09:20:001
11882840,3sleep30-21swapper/311:05:013
113752690,7sleep2321ktimersoftd/212:30:002
13730995932,18cyclictest33-21ksoftirqd/207:50:002
220632530,3sleep222068-21irqrtprio08:30:192
220632530,3sleep222068-21irqrtprio08:30:192
167422530,2sleep20-21swapper/211:35:122
1372999490,3cyclictest16167-21runrttasks10:28:431
13730994833,12cyclictest33-21ksoftirqd/208:05:002
1372999471,2cyclictest0-21swapper/109:50:231
13731994640,3cyclictest18748-21grep10:35:003
1373099440,42cyclictest0-21swapper/211:30:222
1385914333,4phc2sys0-21swapper/307:10:023
138491430,0ptp4l401ktimersoftd/310:50:263
138491420,0ptp4l401ktimersoftd/312:10:133
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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