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2026-06-30 - 04:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Tue Jun 30, 2026 00:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
89872203171,21sleep10-21swapper/119:07:101
89872203171,21sleep10-21swapper/119:07:091
89162203170,22sleep00-21swapper/019:06:160
89162203170,22sleep00-21swapper/019:06:150
89502202169,22sleep20-21swapper/219:06:412
89502202169,22sleep20-21swapper/219:06:412
138591202169,22phc2sys0-21swapper/319:07:303
138591202169,22phc2sys0-21swapper/319:07:293
1967521350,4sleep3951099cyclictest20:35:123
2656421210,5sleep1950899cyclictest23:00:001
138491710,1ptp4l391rcuc/323:25:243
138491660,8ptp4l401ktimersoftd/319:31:573
142792650,4sleep30-21swapper/322:35:113
9507996230,4cyclictest9-21ksoftirqd/020:10:150
9507996229,4cyclictest9-21ksoftirqd/023:10:000
9507996223,10cyclictest9-21ksoftirqd/019:10:160
9507996122,11cyclictest9-21ksoftirqd/020:50:180
9507996122,11cyclictest9-21ksoftirqd/020:50:180
9507996026,4cyclictest9-21ksoftirqd/023:20:130
9507996024,3cyclictest9-21ksoftirqd/023:55:110
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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