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2026-06-19 - 22:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Fri Jun 19, 2026 12:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591221175,35phc2sys0-21swapper/307:07:583
56882202168,23sleep20-21swapper/207:06:102
56672202168,22sleep10-21swapper/107:05:541
56712200168,21sleep00-21swapper/007:05:560
223421590,6sleep2628599cyclictest10:15:132
138491620,1ptp4l401ktimersoftd/310:05:053
138491610,1ptp4l401ktimersoftd/311:15:153
260622570,2sleep20-21swapper/211:00:262
138491570,1ptp4l401ktimersoftd/312:11:163
628499474,5cyclictest9352-21latency_hist10:30:011
628499474,5cyclictest9352-21latency_hist10:30:011
628599461,2cyclictest0-21swapper/209:25:232
628599461,2cyclictest0-21swapper/209:25:232
8952450,3sleep2321ktimersoftd/210:10:242
628599450,2cyclictest0-21swapper/209:40:232
6284994533,10cyclictest25-21ksoftirqd/108:30:001
6284994533,10cyclictest25-21ksoftirqd/108:30:001
6286994337,3cyclictest41-21ksoftirqd/311:00:003
6283994337,4cyclictest19068-21cron09:45:000
6284994236,3cyclictest19069-21cron09:45:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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