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2026-02-25 - 09:53
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Wed Feb 25, 2026 00:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1958322760,8sleep125-21ksoftirqd/119:05:251
1958322760,8sleep125-21ksoftirqd/119:05:241
199612203169,22sleep30-21swapper/319:05:563
199612203169,22sleep30-21swapper/319:05:563
202782202168,22sleep20-21swapper/219:09:572
202782202168,22sleep20-21swapper/219:09:562
200242201168,22sleep00-21swapper/019:06:380
200242201168,22sleep00-21swapper/019:06:370
224342760,6sleep32077599cyclictest20:15:233
20774996526,8cyclictest33-21ksoftirqd/223:45:222
20774996425,6cyclictest33-21ksoftirqd/222:15:262
249672630,3sleep20-21swapper/219:15:252
20774996131,10cyclictest33-21ksoftirqd/221:10:262
20774996028,4cyclictest33-21ksoftirqd/220:55:012
20774996023,6cyclictest33-21ksoftirqd/219:45:002
20774995927,6cyclictest33-21ksoftirqd/200:25:142
20774995926,3cyclictest33-21ksoftirqd/223:15:002
20774995827,8cyclictest33-21ksoftirqd/220:15:002
20774995827,5cyclictest33-21ksoftirqd/200:20:262
20774995826,9cyclictest33-21ksoftirqd/222:00:132
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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