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2026-06-21 - 02:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sat Jun 20, 2026 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
216522231165,22sleep00-21swapper/007:05:590
217272229162,22sleep20-21swapper/207:06:582
138591203169,22phc2sys0-21swapper/307:08:233
216182202168,23sleep10-21swapper/107:05:321
2446021750,4sleep32226599cyclictest12:39:593
138491650,1ptp4l401ktimersoftd/310:00:593
163682600,3sleep00-21swapper/010:10:240
138491600,52ptp4l0-21swapper/307:10:013
50798570,18rtkit-daemon8001-21uniq07:45:151
138491570,1ptp4l401ktimersoftd/311:25:223
138491570,1ptp4l401ktimersoftd/310:40:133
145412530,5sleep214544-21latency_hist09:04:592
130112530,2sleep30-21swapper/312:15:163
258512510,2sleep30-21swapper/307:15:213
258512510,2sleep30-21swapper/307:15:213
138491470,1ptp4l401ktimersoftd/312:11:413
22264994537,5cyclictest4581-21cron09:50:012
135191450,1getstats0-21swapper/309:24:213
138491440,0ptp4l401ktimersoftd/309:08:553
135191430,2getstats0-21swapper/310:39:223
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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