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2026-05-03 - 19:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sun May 03, 2026 12:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591232167,53phc2sys0-21swapper/307:06:273
291202203171,21sleep20-21swapper/207:08:562
289532201167,22sleep00-21swapper/007:06:450
289542200166,22sleep10-21swapper/107:06:461
1873521600,3sleep02950699cyclictest07:50:250
29507996623,4cyclictest25-21ksoftirqd/110:55:251
29507996524,10cyclictest25-21ksoftirqd/109:13:031
29506996520,8cyclictest9-21ksoftirqd/011:20:120
29507996420,4cyclictest25-21ksoftirqd/107:55:191
29506996432,4cyclictest9-21ksoftirqd/007:35:000
29507996328,3cyclictest25-21ksoftirqd/107:40:221
29506996333,6cyclictest9-21ksoftirqd/009:15:160
138491630,1ptp4l401ktimersoftd/309:24:103
29507996229,3cyclictest25-21ksoftirqd/109:40:001
29506996229,4cyclictest9-21ksoftirqd/012:20:220
29507996124,4cyclictest25-21ksoftirqd/109:30:151
29506996130,4cyclictest9-21ksoftirqd/008:25:270
29506996129,5cyclictest9-21ksoftirqd/007:20:000
29506996129,4cyclictest9-21ksoftirqd/009:25:160
151742610,4sleep30-21swapper/312:05:193
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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