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2026-07-25 - 20:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sat Jul 25, 2026 12:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
325752203170,22sleep20-21swapper/207:08:372
138591202168,23phc2sys0-21swapper/307:07:003
325742201167,23sleep10-21swapper/107:08:361
325512199166,22sleep00-21swapper/007:08:190
1501021630,3sleep254299cyclictest10:50:292
1501021630,3sleep254299cyclictest10:50:292
201721250,2sleep10-21swapper/112:35:231
232612680,2sleep00-21swapper/012:14:590
169512570,3sleep20-21swapper/210:55:192
54299456,24cyclictest203762chrt08:50:512
543994428,14cyclictest41-21ksoftirqd/307:15:043
543994323,17cyclictest3485-21perf11:35:013
138491430,0ptp4l401ktimersoftd/307:44:293
541994237,2cyclictest25-21ksoftirqd/109:20:001
540994235,4cyclictest20309-21cron07:50:000
138491420,0ptp4l401ktimersoftd/311:35:143
138491420,0ptp4l401ktimersoftd/308:21:583
54399412,36cyclictest20697-21sh12:10:003
542994135,4cyclictest8533-21cron09:35:002
138491410,0ptp4l401ktimersoftd/308:40:093
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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