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2026-04-19 - 16:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sun Apr 19, 2026 12:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
53592201167,22sleep20-21swapper/207:09:082
53582201166,24sleep10-21swapper/107:09:061
138591200165,23phc2sys0-21swapper/307:08:003
52682198164,22sleep00-21swapper/007:07:570
220321680,7sleep0572999cyclictest08:05:200
477321350,5sleep2573199cyclictest08:10:202
942521170,3sleep3573299cyclictest10:30:173
138491790,1ptp4l391rcuc/309:50:183
138491760,1ptp4l391rcuc/309:55:173
573299689,18cyclictest30804-21latency_hist09:05:013
302042640,4sleep3573299cyclictest10:05:263
50872610,2sleep30-21swapper/309:15:253
573299560,3cyclictest18182-21seq11:51:223
233952560,2sleep3401ktimersoftd/307:45:133
138491550,1ptp4l391rcuc/309:30:233
286782520,2sleep20-21swapper/212:15:152
138491440,0ptp4l401ktimersoftd/307:33:153
138491440,0ptp4l401ktimersoftd/307:33:153
573299421,3cyclictest0-21swapper/310:29:193
138491410,34ptp4l0-21swapper/307:10:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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