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2026-07-06 - 02:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sun Jul 05, 2026 12:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591211144,23phc2sys0-21swapper/307:06:073
120912205170,23sleep10-21swapper/107:09:221
120972203169,22sleep20-21swapper/207:09:272
120952200166,22sleep00-21swapper/007:09:250
369721690,6sleep21244099cyclictest12:15:232
1244099660,24cyclictest8524-21ps12:25:232
1244099651,23cyclictest1-21systemd07:20:192
1244099610,25cyclictest6844-21awk08:00:282
138491580,1ptp4l391rcuc/307:20:223
1244099570,22cyclictest15012-21cpuspeed_turbos08:20:122
1244099530,25cyclictest25356-21sed07:35:162
1244099521,24cyclictest1145-21gunzip12:10:262
138491500,0ptp4l401ktimersoftd/310:48:203
1244099500,24cyclictest10462-21sed12:30:192
1214524735,5sleep30-21swapper/307:10:003
138491440,1ptp4l401ktimersoftd/311:30:233
138491440,0ptp4l401ktimersoftd/308:45:483
1244099440,27cyclictest30603-21irqstats09:55:192
1244099440,27cyclictest30603-21irqstats09:55:192
1243899449,6cyclictest9-21ksoftirqd/008:20:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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