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2026-06-04 - 23:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Thu Jun 04, 2026 12:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
98152226162,52sleep20-21swapper/207:08:182
98182203170,21sleep00-21swapper/007:08:200
138591203169,22phc2sys0-21swapper/307:05:373
97942201167,23sleep10-21swapper/107:08:021
1385918664,12phc2sys0-21swapper/307:10:013
31912570,5sleep01024599cyclictest09:05:150
138491530,1ptp4l401ktimersoftd/312:12:053
96802510,2sleep00-21swapper/009:15:260
126092490,3sleep21024799cyclictest07:15:002
116112480,2sleep20-21swapper/211:30:262
138491450,1ptp4l401ktimersoftd/311:03:053
138491440,0ptp4l401ktimersoftd/312:16:383
138491430,0ptp4l401ktimersoftd/307:56:193
138491420,0ptp4l401ktimersoftd/309:18:273
138491420,0ptp4l401ktimersoftd/307:31:033
138491410,0ptp4l401ktimersoftd/311:55:483
138491410,0ptp4l401ktimersoftd/309:21:283
138491410,0ptp4l401ktimersoftd/308:32:173
138491410,0ptp4l401ktimersoftd/307:25:193
10247994123,4cyclictest33-21ksoftirqd/208:13:092
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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