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2026-02-25 - 22:14
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Wed Feb 25, 2026 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
186832204169,23sleep30-21swapper/307:07:523
185942201168,22sleep10-21swapper/107:06:411
187672200168,21sleep20-21swapper/207:08:512
187572197163,22sleep00-21swapper/007:08:490
1385918363,11phc2sys0-21swapper/307:10:003
66302690,2sleep30-21swapper/310:00:133
138491660,11ptp4l1915099cyclictest11:05:393
138491650,1ptp4l401ktimersoftd/312:20:303
138491610,1ptp4l401ktimersoftd/309:05:173
1914799608,10cyclictest1303-21runrttasks11:46:130
1914799599,17cyclictest12835-21/usr/sbin/munin08:00:220
1914799596,10cyclictest22466-21sed09:25:200
1914799585,12cyclictest0-21swapper/010:40:150
1914799578,11cyclictest2291-21sed09:50:180
1914799577,16cyclictest7169-21irqrtprio12:10:170
1914799576,15cyclictest1303-21runrttasks10:25:170
1914799566,11cyclictest25507-21timerandwakeup09:30:240
138491560,1ptp4l401ktimersoftd/309:44:003
1914799557,10cyclictest4376-21fschecks_time09:55:160
1914799553,10cyclictest0-21swapper/009:05:190
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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