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2026-06-25 - 00:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Wed Jun 24, 2026 12:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
174442208173,23sleep30-21swapper/307:09:223
173342202169,22sleep00-21swapper/007:07:530
172852202170,22sleep20-21swapper/207:07:232
172542202169,22sleep10-21swapper/107:06:581
777321510,5sleep31779199cyclictest11:05:253
1385918262,11phc2sys0-21swapper/307:10:013
120952790,5sleep212099-21irqrtprio11:15:192
138491740,1ptp4l391rcuc/310:00:003
1779099730,22cyclictest16778-21phc2sys-jitter08:10:222
138491680,1ptp4l31383-21irqstats07:35:203
1779099650,22cyclictest3584-21cut12:05:002
1779099650,22cyclictest29815-21grep08:35:282
1779099650,22cyclictest29815-21grep08:35:282
1779099640,26cyclictest12279-21cat08:00:262
1779099620,20cyclictest21324-21sed10:30:142
1779099610,24cyclictest14872-21vmstat08:05:292
85272600,2sleep30-21swapper/307:55:133
1779099600,19cyclictest16354-21hddtemp_smartct10:20:152
1779099580,24cyclictest24855-21mailstats10:35:252
1779099570,25cyclictest27130-21sshd07:25:432
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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