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2026-08-10 - 21:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Mon Aug 10, 2026 12:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
10412226163,52sleep20-21swapper/207:05:402
138591202168,23phc2sys0-21swapper/307:09:323
13952199166,22sleep10-21swapper/107:09:571
11322196163,22sleep00-21swapper/007:06:500
138591161121,14phc2sys0-21swapper/307:10:013
169799635,17cyclictest0-21swapper/012:25:280
169799595,16cyclictest0-21swapper/011:15:140
169799595,15cyclictest0-21swapper/008:15:180
169799565,9cyclictest0-21swapper/012:10:250
169799565,9cyclictest0-21swapper/012:10:250
138491560,1ptp4l401ktimersoftd/309:31:243
169799559,16cyclictest16471-21cat08:45:130
169799558,17cyclictest24030-21cstates12:15:110
169799549,16cyclictest26133-21grep10:10:130
169799544,15cyclictest0-21swapper/009:30:240
138491540,1ptp4l401ktimersoftd/310:36:313
138491530,1ptp4l401ktimersoftd/310:32:583
138491530,1ptp4l401ktimersoftd/309:43:183
169799528,15cyclictest6270-21latency_hist08:25:000
169799528,15cyclictest6270-21latency_hist08:25:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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