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2026-06-29 - 04:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Mon Jun 29, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591223163,48phc2sys0-21swapper/319:09:463
239882217173,19sleep10-21swapper/119:05:591
239872205171,22sleep00-21swapper/019:05:580
242992204170,22sleep20-21swapper/219:09:542
2430928162,10sleep10-21swapper/119:10:001
24603997630,4cyclictest33-21ksoftirqd/222:48:082
24604996631,4cyclictest41-21ksoftirqd/300:25:003
24603996628,8cyclictest33-21ksoftirqd/223:15:292
24603996628,8cyclictest33-21ksoftirqd/223:15:292
8492620,3sleep30-21swapper/321:35:233
24603996127,4cyclictest33-21ksoftirqd/220:00:162
24603996118,8cyclictest33-21ksoftirqd/222:40:002
24603996021,4cyclictest33-21ksoftirqd/219:40:282
24603995928,10cyclictest33-21ksoftirqd/223:25:242
24603995921,8cyclictest33-21ksoftirqd/221:10:192
24603995919,4cyclictest33-21ksoftirqd/220:25:242
24603995916,8cyclictest33-21ksoftirqd/221:35:222
24603995823,6cyclictest33-21ksoftirqd/221:45:162
24603995823,4cyclictest33-21ksoftirqd/220:40:242
24603995819,4cyclictest33-21ksoftirqd/222:55:232
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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