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2026-08-25 - 23:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Tue Aug 25, 2026 12:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591235168,22phc2sys0-21swapper/307:09:053
105722201169,21sleep20-21swapper/207:09:352
105412200166,22sleep10-21swapper/107:09:101
104072199166,21sleep00-21swapper/007:07:320
1089899716,27cyclictest12470-21proc_pri10:25:250
1090199685,11cyclictest3489-21sendmail-msp08:00:003
1090199685,11cyclictest3489-21sendmail-msp08:00:003
1090199608,9cyclictest11558-21basename07:10:163
1090199598,9cyclictest18714-21latency_hist11:45:013
1090199598,16cyclictest16984-21irqrtprio09:30:203
1090199588,9cyclictest22183-21irqrtprio07:30:183
1090199586,15cyclictest2315-21gnome-shell10:27:583
1090199583,17cyclictest0-21swapper/311:10:143
1090199583,16cyclictest0-21swapper/307:15:013
317872570,3sleep30-21swapper/310:00:173
206662570,5sleep320664-21cron08:35:003
1090199578,9cyclictest1283-21sed12:15:003
1090199576,16cyclictest26251-21df_abs08:45:143
1090199576,11cyclictest25927-21cut07:40:013
1090199568,10cyclictest24469-21sed08:40:183
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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