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2026-09-06 - 01:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sat Sep 05, 2026 12:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
253912206171,23sleep30-21swapper/307:05:023
275142203170,22sleep20-21swapper/207:08:002
275902201167,22sleep10-21swapper/107:08:581
253932201167,22sleep00-21swapper/007:05:040
27965995121,3cyclictest41-21ksoftirqd/309:42:393
27965995021,3cyclictest41-21ksoftirqd/310:11:193
2796599501,46cyclictest25395-21cron11:25:023
27965994821,3cyclictest41-21ksoftirqd/312:02:163
27965994740,4cyclictest22924-21cat11:20:013
27965994717,9cyclictest41-21ksoftirqd/310:00:423
2796599458,5cyclictest41-21ksoftirqd/307:54:403
138491440,0ptp4l401ktimersoftd/311:27:373
2796599438,5cyclictest41-21ksoftirqd/312:14:573
2796599438,4cyclictest41-21ksoftirqd/310:26:253
2796599426,4cyclictest41-21ksoftirqd/310:49:073
27964994231,9cyclictest33-21ksoftirqd/208:30:282
138491420,0ptp4l401ktimersoftd/309:07:563
27965994115,3cyclictest41-21ksoftirqd/308:19:473
27963994135,3cyclictest25-21ksoftirqd/108:15:171
138491410,0ptp4l401ktimersoftd/307:42:113
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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