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2026-06-17 - 07:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Wed Jun 17, 2026 00:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
239692204170,23sleep10-21swapper/119:07:551
238892204170,22sleep30-21swapper/319:06:523
240002203169,22sleep20-21swapper/219:08:192
239362201166,23sleep00-21swapper/019:07:290
2205121530,3sleep12442599cyclictest21:15:151
497221380,5sleep12442599cyclictest19:35:131
497221380,5sleep12442599cyclictest19:35:131
2442699660,23cyclictest1114-21cat20:30:252
2442699660,22cyclictest20077-21cat20:05:182
2442699630,22cyclictest18254-21ptp4l21:05:242
2442699630,21cyclictest18075-21date00:20:272
2442699630,21cyclictest18075-21date00:20:262
2442699620,30cyclictest11270-21/usr/sbin/munin00:10:212
2442699620,23cyclictest6688-21expr00:00:132
322322610,3sleep132237-21cpuspeed_turbos19:25:141
2442699600,25cyclictest25501-21sensors00:35:242
2442699600,21cyclictest16119-21timerwakeupswit21:00:252
173682600,4sleep217370-21irqrtprio23:15:182
99892590,1sleep20-21swapper/200:05:252
2442699590,23cyclictest3561-21mailstats20:35:252
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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