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2026-08-03 - 11:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Mon Aug 03, 2026 00:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
53612208173,23sleep30-21swapper/319:09:443
53492204171,22sleep10-21swapper/119:09:341
50322204170,23sleep20-21swapper/219:05:332
50582201167,22sleep00-21swapper/019:05:470
427921500,8sleep3567999cyclictest21:15:153
1423321440,6sleep2567899cyclictest20:30:172
5679996023,8cyclictest41-21ksoftirqd/300:38:333
5679996022,8cyclictest41-21ksoftirqd/300:22:383
5679996019,7cyclictest41-21ksoftirqd/322:35:053
5678996029,8cyclictest33-21ksoftirqd/221:25:312
5679995921,8cyclictest41-21ksoftirqd/323:42:463
5679995921,7cyclictest41-21ksoftirqd/323:19:063
5678995927,9cyclictest33-21ksoftirqd/223:05:002
5678995926,10cyclictest33-21ksoftirqd/223:50:142
5679995826,6cyclictest41-21ksoftirqd/320:05:133
5679995822,9cyclictest41-21ksoftirqd/321:29:113
5679995821,9cyclictest41-21ksoftirqd/319:19:493
5679995728,3cyclictest41-21ksoftirqd/321:35:153
5679995722,9cyclictest41-21ksoftirqd/300:05:453
5679995722,8cyclictest41-21ksoftirqd/320:25:283
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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