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2026-06-26 - 17:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Fri Jun 26, 2026 12:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591234167,22phc2sys0-21swapper/307:05:093
155622228162,23sleep10-21swapper/107:07:421
156242205172,22sleep00-21swapper/007:08:280
157912202169,22sleep20-21swapper/207:09:512
138491960,1ptp4l7545-21ptp4l11:10:233
280222600,2sleep00-21swapper/010:45:270
1609499555,18cyclictest8050-21seq11:11:040
238432540,1sleep20-21swapper/210:40:122
149992520,2sleep10-21swapper/108:10:241
142512520,1sleep30-21swapper/308:10:183
311492500,2sleep10-21swapper/108:45:131
166232460,1sleep316625-21cut08:15:153
16096994336,3cyclictest3585-21cron12:09:592
16095994315,26cyclictest0-21swapper/109:40:531
1609499438,21cyclictest15470-21seq11:26:240
138491430,0ptp4l401ktimersoftd/310:24:453
16096994237,3cyclictest33-21ksoftirqd/208:00:012
16096994236,3cyclictest33-21ksoftirqd/211:00:012
16096994231,9cyclictest33-21ksoftirqd/208:25:282
1609699421,38cyclictest3434-21cron07:50:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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