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2026-07-15 - 15:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Wed Jul 15, 2026 00:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
107872204170,22sleep30-21swapper/319:07:193
107242202168,22sleep00-21swapper/019:06:270
107252201167,23sleep10-21swapper/119:06:271
106992201169,21sleep20-21swapper/219:06:092
2174821700,7sleep21128999cyclictest23:50:112
138491860,1ptp4l10022-21open_files20:10:233
1099628262,11sleep00-21swapper/019:10:010
138491640,1ptp4l401ktimersoftd/321:50:243
167792560,2sleep30-21swapper/319:20:143
147912520,2sleep0111rcuc/021:25:200
1385915236,9phc2sys0-21swapper/319:10:013
50798480,3rtkit-daemon506-21rtkit-daemon22:17:410
11287994540,3cyclictest3918-21dump-pmu-power22:10:000
138491440,0ptp4l401ktimersoftd/300:18:503
138491430,0ptp4l401ktimersoftd/323:44:443
138491430,0ptp4l401ktimersoftd/321:05:213
138491430,0ptp4l401ktimersoftd/320:03:043
11289994331,4cyclictest33-21ksoftirqd/220:15:002
11289994238,2cyclictest31049-21latency_hist19:50:002
1129099414,8cyclictest121rcu_preempt22:19:593
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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