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2026-08-17 - 21:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Mon Aug 17, 2026 12:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591216169,36phc2sys0-21swapper/307:06:583
32572204170,23sleep10-21swapper/107:05:081
53492203170,22sleep20-21swapper/207:08:302
32562200166,22sleep00-21swapper/007:05:070
547428262,11sleep30-21swapper/307:10:003
246102710,2sleep224609-21ptp4l08:50:232
138491620,8ptp4l0-21swapper/308:55:333
152372610,2sleep10-21swapper/109:35:281
138491600,0ptp4l401ktimersoftd/310:50:473
138491560,1ptp4l401ktimersoftd/308:17:473
42632500,5sleep14267-21kernelversion08:10:201
115132500,2sleep20-21swapper/211:40:172
85432490,2sleep10-21swapper/108:20:141
5769994633,10cyclictest41-21ksoftirqd/308:40:003
5769994613,7cyclictest41-21ksoftirqd/311:30:003
5769994414,7cyclictest41-21ksoftirqd/310:05:003
576999437,8cyclictest41-21ksoftirqd/310:40:003
5769994228,3cyclictest41-21ksoftirqd/311:50:203
5769994215,7cyclictest41-21ksoftirqd/309:10:203
5769994215,6cyclictest41-21ksoftirqd/310:30:293
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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