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2026-06-06 - 00:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Fri Jun 05, 2026 12:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591206173,22phc2sys0-21swapper/307:08:083
45422205172,22sleep20-21swapper/207:06:492
46482200167,22sleep10-21swapper/107:08:121
45402200167,22sleep00-21swapper/007:06:470
1221621630,6sleep3509199cyclictest09:35:003
262621580,3sleep3509199cyclictest11:25:123
5088996130,3cyclictest9-21ksoftirqd/012:35:270
57402600,1sleep10-21swapper/112:35:191
5088995821,8cyclictest9-21ksoftirqd/008:19:520
5088995729,3cyclictest9-21ksoftirqd/010:30:150
138491570,0ptp4l401ktimersoftd/312:25:153
5088995626,4cyclictest9-21ksoftirqd/011:15:130
5088995626,4cyclictest9-21ksoftirqd/007:15:270
5088995522,7cyclictest9-21ksoftirqd/010:50:170
5088995522,4cyclictest9-21ksoftirqd/007:35:190
5088995518,6cyclictest9-21ksoftirqd/012:15:250
5088995428,6cyclictest9-21ksoftirqd/010:20:260
5088995425,3cyclictest9-21ksoftirqd/007:30:200
5088995423,6cyclictest9-21ksoftirqd/011:55:160
5088995423,6cyclictest9-21ksoftirqd/008:05:270
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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