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2026-07-19 - 23:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sun Jul 19, 2026 12:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
28162209175,22sleep00-21swapper/007:08:550
28392207171,24sleep30-21swapper/307:09:143
237022070,33sleep233-21ksoftirqd/207:05:262
27802203169,23sleep10-21swapper/107:08:281
158721770,5sleep0320099cyclictest11:25:160
2614921680,2sleep3320399cyclictest11:10:113
138491630,1ptp4l401ktimersoftd/309:38:353
3200996229,10cyclictest9-21ksoftirqd/009:45:010
3200996130,3cyclictest9-21ksoftirqd/007:50:000
138491610,0ptp4l401ktimersoftd/310:20:463
3200996029,7cyclictest9-21ksoftirqd/009:10:150
3200996029,6cyclictest9-21ksoftirqd/007:25:270
3200996028,6cyclictest9-21ksoftirqd/007:55:180
210002590,2sleep30-21swapper/311:00:013
3200995827,4cyclictest9-21ksoftirqd/011:00:110
3200995827,4cyclictest9-21ksoftirqd/011:00:110
3200995826,8cyclictest9-21ksoftirqd/007:35:270
3200995726,3cyclictest9-21ksoftirqd/010:30:000
3200995725,4cyclictest9-21ksoftirqd/010:05:120
3200995724,7cyclictest9-21ksoftirqd/007:50:190
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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