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2026-02-28 - 16:16
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sat Feb 28, 2026 12:46:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591206172,22phc2sys0-21swapper/307:09:373
138591206172,22phc2sys0-21swapper/307:09:373
55762205171,23sleep10-21swapper/107:08:031
55762205171,23sleep10-21swapper/107:08:031
55252201168,22sleep20-21swapper/207:07:232
55252201168,22sleep20-21swapper/207:07:232
55232199165,22sleep00-21swapper/007:07:210
55232199165,22sleep00-21swapper/007:07:210
385821580,6sleep2602399cyclictest08:10:132
138491890,1ptp4l19609-21ls10:50:243
280972580,7sleep1602299cyclictest07:55:001
138491550,1ptp4l401ktimersoftd/310:09:533
602399522,7cyclictest5921-21grep12:35:112
138491520,1ptp4l401ktimersoftd/311:15:273
138491520,1ptp4l401ktimersoftd/311:15:273
323262510,1sleep00-21swapper/011:15:250
323262510,1sleep00-21swapper/011:15:250
6022994817,4cyclictest25-21ksoftirqd/110:50:011
6022994817,4cyclictest25-21ksoftirqd/110:50:001
602399474,7cyclictest33-21ksoftirqd/208:00:252
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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