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2026-08-30 - 16:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sun Aug 30, 2026 12:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
208182215156,48sleep00-21swapper/007:08:210
138591205171,22phc2sys0-21swapper/307:05:433
207982203169,23sleep20-21swapper/207:08:072
205622202168,22sleep10-21swapper/107:05:451
3123721750,6sleep12124599cyclictest09:40:131
1099821500,6sleep32124799cyclictest11:10:153
2124599670,26cyclictest19064-21sed10:20:181
2124599631,24cyclictest27654-21awk07:20:231
2124599630,24cyclictest23775-21fschecks_count10:30:161
2124599620,25cyclictest17105-21uname09:10:221
2124599620,23cyclictest25263-21timedrift08:20:241
2124599610,23cyclictest24839-21/usr/sbin/munin07:15:211
2124599601,30cyclictest22547-21awk07:10:231
2124599601,24cyclictest19407-21irqrtprio08:10:181
2124599600,25cyclictest15898-21/usr/sbin/munin10:15:121
2124599600,23cyclictest4764-21/usr/sbin/munin09:50:211
2124599600,21cyclictest6050-21/usr/sbin/munin09:55:131
2124599590,23cyclictest8629-21/usr/sbin/munin11:05:141
2124599590,23cyclictest32373-21ps08:35:231
2124599590,20cyclictest14969-21ls10:10:241
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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