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2026-07-31 - 17:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Fri Jul 31, 2026 12:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
163902228167,49sleep10-21swapper/107:08:281
163642204172,21sleep20-21swapper/207:08:092
162802204169,23sleep00-21swapper/007:07:020
162482203168,23sleep30-21swapper/307:06:373
539921900,7sleep01681099cyclictest10:00:200
1451021670,4sleep31681399cyclictest11:25:163
1031021420,6sleep21681299cyclictest11:15:242
16518210280,11sleep10-21swapper/107:10:001
138491900,1ptp4l17132-21cstates07:10:133
54282540,2sleep30-21swapper/307:50:253
132652540,1sleep10-21swapper/110:15:261
1681099530,11cyclictest18226-21ptp4l07:10:250
42082520,3sleep11681199cyclictest10:00:011
184882520,2sleep20-21swapper/208:15:282
184882520,2sleep20-21swapper/208:15:282
154962520,2sleep00-21swapper/011:25:240
138491510,1ptp4l401ktimersoftd/311:55:343
1681099500,17cyclictest1319-21snmpd08:32:120
1681099500,11cyclictest28851-21date10:50:000
1681099500,11cyclictest1535-21cat08:50:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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