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2026-07-31 - 05:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Fri Jul 31, 2026 00:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
141822230163,23sleep30-21swapper/319:09:573
141682203163,28sleep00-21swapper/019:09:460
140722202168,22sleep20-21swapper/219:08:332
140192202169,22sleep10-21swapper/119:07:501
3202521890,7sleep11447899cyclictest21:55:151
1385919066,15phc2sys0-21swapper/319:10:003
1418628363,11sleep20-21swapper/219:10:002
138491700,3ptp4l13350irq/39-mmc120:15:263
14479996832,7cyclictest33-21ksoftirqd/223:15:232
14479996733,9cyclictest33-21ksoftirqd/222:55:002
14479996622,13cyclictest33-21ksoftirqd/200:00:012
14479996531,7cyclictest33-21ksoftirqd/219:55:242
14479996530,5cyclictest33-21ksoftirqd/219:55:002
14479996333,3cyclictest33-21ksoftirqd/220:45:112
14479996330,4cyclictest33-21ksoftirqd/221:20:012
14479996329,6cyclictest33-21ksoftirqd/221:25:172
14479996329,6cyclictest33-21ksoftirqd/200:05:282
1448099620,17cyclictest24001-21latency_hist21:40:013
14479996231,4cyclictest33-21ksoftirqd/220:20:002
14479996230,4cyclictest33-21ksoftirqd/223:05:272
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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