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2026-05-26 - 03:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Tue May 26, 2026 00:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591224162,50phc2sys0-21swapper/319:09:403
99572202169,22sleep20-21swapper/219:07:272
100472202169,22sleep00-21swapper/019:08:380
98662201170,21sleep10-21swapper/119:06:221
1787121520,5sleep31044699cyclictest19:25:123
138491700,1ptp4l391rcuc/321:24:403
60072590,4sleep06012-21irqrtprio23:20:190
138491550,1ptp4l401ktimersoftd/323:54:333
134991480,1getstats0-21swapper/320:05:113
134991480,1getstats0-21swapper/320:05:113
138491460,1ptp4l401ktimersoftd/322:54:073
10446994538,4cyclictest24927-21ls00:00:013
10445994539,3cyclictest22558-21ls19:34:592
138491440,1ptp4l401ktimersoftd/323:47:473
10446994436,4cyclictest41-21ksoftirqd/321:00:003
1044599442,39cyclictest14794-21cron21:30:002
10444994418,25cyclictest2380-21kworker/1:120:03:251
138491430,0ptp4l401ktimersoftd/322:44:163
138491430,0ptp4l401ktimersoftd/300:14:163
10446994335,5cyclictest22524-21cron19:35:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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