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2026-07-07 - 15:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Tue Jul 07, 2026 12:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
286642231167,21sleep10-21swapper/107:09:131
285532205172,21sleep20-21swapper/207:07:532
138591201167,23phc2sys0-21swapper/307:06:583
285062199165,23sleep00-21swapper/007:07:140
138491710,0ptp4l391rcuc/312:15:233
29018996233,4cyclictest33-21ksoftirqd/208:20:152
29018996133,3cyclictest33-21ksoftirqd/211:10:132
29018996131,3cyclictest33-21ksoftirqd/211:20:162
29018996130,3cyclictest33-21ksoftirqd/209:01:162
29019996028,7cyclictest41-21ksoftirqd/308:25:003
29019996027,4cyclictest41-21ksoftirqd/310:20:143
29018996032,3cyclictest33-21ksoftirqd/210:10:142
29018996032,3cyclictest33-21ksoftirqd/209:10:142
29018996032,3cyclictest33-21ksoftirqd/207:10:142
29018996031,4cyclictest33-21ksoftirqd/208:35:122
29018996030,4cyclictest33-21ksoftirqd/207:15:252
29018996030,3cyclictest33-21ksoftirqd/210:30:232
29018996029,4cyclictest33-21ksoftirqd/207:55:002
29018996028,4cyclictest33-21ksoftirqd/210:50:142
29018995927,7cyclictest33-21ksoftirqd/207:25:182
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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