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2026-03-29 - 16:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sun Mar 29, 2026 12:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
165432205172,22sleep10-21swapper/107:07:191
138591204170,22phc2sys0-21swapper/307:07:533
167112201167,22sleep00-21swapper/007:09:230
167182200168,21sleep20-21swapper/207:09:292
1832121690,7sleep21725199cyclictest12:35:172
17250996630,7cyclictest25-21ksoftirqd/112:20:171
17250996530,5cyclictest25-21ksoftirqd/109:55:201
17250996527,4cyclictest25-21ksoftirqd/107:25:001
17250996429,7cyclictest25-21ksoftirqd/110:05:201
17250996331,8cyclictest25-21ksoftirqd/107:45:281
17250996331,4cyclictest25-21ksoftirqd/108:55:001
17250996329,4cyclictest25-21ksoftirqd/110:20:231
17250996232,4cyclictest25-21ksoftirqd/107:10:231
17250996227,7cyclictest25-21ksoftirqd/110:15:211
17250996131,8cyclictest25-21ksoftirqd/109:15:171
17250996130,9cyclictest25-21ksoftirqd/108:20:181
17250996130,8cyclictest25-21ksoftirqd/110:35:171
17250996129,4cyclictest25-21ksoftirqd/107:55:191
17250996128,8cyclictest25-21ksoftirqd/107:15:121
17250996128,7cyclictest25-21ksoftirqd/111:20:221
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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