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2025-11-21 - 12:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Fri Nov 21, 2025 00:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
168232204170,22sleep10-21swapper/119:06:051
427791202167,23phc2sys0-21swapper/319:09:543
168472199166,22sleep00-21swapper/019:06:250
168192198165,21sleep20-21swapper/219:06:022
2937221640,6sleep21758899cyclictest20:35:242
204072580,2sleep30-21swapper/319:15:153
17590995447,4cyclictest10103-21latency_hist19:59:593
427291530,1ptp4l401ktimersoftd/321:31:513
17586995015,8cyclictest9-21ksoftirqd/020:25:200
237192490,1sleep10-21swapper/123:40:141
427291480,0ptp4l401ktimersoftd/320:03:093
17590994841,4cyclictest24853-21cron19:24:593
17588994627,16cyclictest33-21ksoftirqd/200:11:202
17588994513,29cyclictest28283-21kworker/2:223:10:272
1758699453,7cyclictest121rcu_preempt21:24:020
1713524533,5sleep20-21swapper/219:10:002
427291430,0ptp4l401ktimersoftd/321:01:263
17588994337,4cyclictest33-21ksoftirqd/222:05:002
17586994339,2cyclictest9-21ksoftirqd/000:30:000
427291420,0ptp4l401ktimersoftd/321:25:343
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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