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2026-06-19 - 10:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Fri Jun 19, 2026 00:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591204170,22phc2sys0-21swapper/319:05:463
63712203169,22sleep00-21swapper/019:07:480
62892200168,21sleep20-21swapper/219:06:492
62392200168,21sleep10-21swapper/119:06:131
654229661,28sleep00-21swapper/019:10:010
138491680,1ptp4l401ktimersoftd/322:05:143
138491640,1ptp4l401ktimersoftd/321:45:193
218832630,2sleep20-21swapper/219:40:022
6836994632,11cyclictest41-21ksoftirqd/323:40:003
6835994540,3cyclictest1171-21sh22:15:002
683599442,39cyclictest12039-21fschecks_count23:40:172
138491440,1ptp4l401ktimersoftd/320:11:023
138491440,0ptp4l401ktimersoftd/323:41:033
683599438,3cyclictest33-21ksoftirqd/223:35:002
6835994331,9cyclictest33-21ksoftirqd/222:28:162
6835994230,9cyclictest33-21ksoftirqd/223:55:282
138491420,0ptp4l401ktimersoftd/322:45:473
138491420,0ptp4l401ktimersoftd/322:45:473
6835994136,3cyclictest33-21ksoftirqd/220:09:592
6835994126,11cyclictest33-21ksoftirqd/219:50:252
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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