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2026-06-18 - 08:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Thu Jun 18, 2026 00:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591211164,36phc2sys0-21swapper/319:09:593
211722204170,23sleep10-21swapper/119:05:071
232362203169,22sleep00-21swapper/019:07:550
232952201169,21sleep20-21swapper/219:08:422
1429421760,6sleep22369099cyclictest19:55:182
1429421760,6sleep22369099cyclictest19:55:182
2886321620,7sleep02368899cyclictest19:20:140
2666121310,7sleep32369199cyclictest23:35:153
225522620,2sleep10-21swapper/120:10:261
23691996129,7cyclictest41-21ksoftirqd/320:05:123
299632600,7sleep02368899cyclictest23:40:210
23691996032,7cyclictest41-21ksoftirqd/322:00:253
23691996025,5cyclictest41-21ksoftirqd/300:25:173
23691995930,7cyclictest41-21ksoftirqd/320:10:153
23691995929,4cyclictest41-21ksoftirqd/322:20:273
23691995928,9cyclictest41-21ksoftirqd/323:15:153
23691995729,7cyclictest41-21ksoftirqd/321:35:003
23691995715,4cyclictest41-21ksoftirqd/320:43:533
23691995630,6cyclictest41-21ksoftirqd/323:05:223
23691995625,8cyclictest41-21ksoftirqd/319:45:123
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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