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2026-07-18 - 07:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sat Jul 18, 2026 00:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
248492215168,36sleep30-21swapper/319:06:583
249972204170,22sleep20-21swapper/219:08:552
249032203170,22sleep00-21swapper/019:07:410
250542201167,23sleep10-21swapper/119:09:371
928821500,7sleep32537899cyclictest19:40:203
241632600,2sleep10-21swapper/100:30:231
25375995337,13cyclictest9-21ksoftirqd/021:55:000
148202520,2sleep20-21swapper/222:00:282
2537799511,47cyclictest11699-21ptp4l00:05:232
2537799511,47cyclictest11699-21ptp4l00:05:232
2537799470,3cyclictest19246-21ps00:20:232
17082470,2sleep00-21swapper/022:40:210
2537799450,43cyclictest0-21swapper/220:05:232
138491440,0ptp4l401ktimersoftd/319:47:473
25376994337,3cyclictest5142-21cron23:55:001
138491430,0ptp4l401ktimersoftd/323:56:323
2537799420,41cyclictest0-21swapper/222:20:232
138491420,1ptp4l401ktimersoftd/321:47:133
138491420,0ptp4l401ktimersoftd/321:57:093
2537799410,1cyclictest0-21swapper/223:40:232
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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