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2025-06-28 - 23:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sat Jun 28, 2025 12:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
134791228162,21phc2sys0-21swapper/307:08:033
228792209175,23sleep10-21swapper/107:09:521
228802205171,22sleep20-21swapper/207:09:532
226652204169,23sleep00-21swapper/007:07:060
2910821440,7sleep02318299cyclictest11:40:180
134991860,1ptp4l401ktimersoftd/308:50:183
279182670,4sleep327917-21grep09:30:173
90282570,2sleep20-21swapper/208:50:212
134991560,1ptp4l391rcuc/310:40:223
33772550,2sleep30-21swapper/308:40:153
134991550,1ptp4l401ktimersoftd/309:15:193
58052540,3sleep15808-21idleruntime-cro11:59:591
63442520,2sleep10-21swapper/112:00:151
134991470,0ptp4l401ktimersoftd/309:48:253
2318399460,3cyclictest12509-21chrt08:57:391
36998450,7rtkit-daemon0-21swapper/311:34:353
2318399431,3cyclictest0-21swapper/110:58:551
36998420,4rtkit-daemon10437-21apt-get10:00:182
134991420,0ptp4l401ktimersoftd/312:27:403
134991420,0ptp4l401ktimersoftd/310:33:183
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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