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2026-05-23 - 00:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Fri May 22, 2026 12:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591230161,23phc2sys0-21swapper/307:08:313
164612204171,22sleep10-21swapper/107:08:461
162882204170,22sleep20-21swapper/207:06:302
164602199166,22sleep00-21swapper/007:08:450
2108521430,6sleep21685999cyclictest08:22:402
1656428762,16sleep30-21swapper/307:10:013
16858996932,6cyclictest25-21ksoftirqd/108:55:001
16858996729,6cyclictest25-21ksoftirqd/107:55:001
16860996429,8cyclictest41-21ksoftirqd/310:30:193
16858996432,6cyclictest25-21ksoftirqd/109:40:001
16858996329,6cyclictest25-21ksoftirqd/111:20:011
16857996328,4cyclictest9-21ksoftirqd/008:25:240
16860996230,7cyclictest41-21ksoftirqd/309:15:013
16860996228,7cyclictest41-21ksoftirqd/310:55:003
16860996227,5cyclictest41-21ksoftirqd/308:40:243
16860996223,8cyclictest41-21ksoftirqd/311:15:133
16858996229,6cyclictest25-21ksoftirqd/107:20:181
16858996225,6cyclictest25-21ksoftirqd/108:05:011
16857996228,5cyclictest9-21ksoftirqd/009:00:010
16860996126,7cyclictest41-21ksoftirqd/312:35:173
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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