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2026-05-31 - 18:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sun May 31, 2026 12:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
185782226162,52sleep20-21swapper/207:07:052
187332208173,23sleep30-21swapper/307:09:053
186792205172,22sleep10-21swapper/107:08:231
186682204169,23sleep00-21swapper/007:08:150
1939121620,4sleep11910499cyclictest10:25:121
1881228262,10sleep10-21swapper/107:10:001
19104996328,8cyclictest25-21ksoftirqd/107:40:281
58502620,2sleep30-21swapper/311:00:243
56142620,2sleep10-21swapper/111:00:221
19104996231,4cyclictest25-21ksoftirqd/109:05:181
19103996234,4cyclictest9-21ksoftirqd/009:30:200
19103996231,4cyclictest9-21ksoftirqd/007:20:140
19104996131,3cyclictest25-21ksoftirqd/108:10:251
19104996127,3cyclictest25-21ksoftirqd/111:25:231
19103996132,4cyclictest9-21ksoftirqd/010:40:230
19103996125,6cyclictest9-21ksoftirqd/010:55:010
19104996029,4cyclictest25-21ksoftirqd/112:25:001
19103996029,4cyclictest9-21ksoftirqd/011:05:170
19104995929,3cyclictest25-21ksoftirqd/108:45:001
19104995927,4cyclictest25-21ksoftirqd/111:10:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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