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2025-11-15 - 23:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sat Nov 15, 2025 12:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
427791208173,23phc2sys0-21swapper/307:09:243
3028721990,5sleep00-21swapper/007:08:240
299722199167,21sleep20-21swapper/207:06:112
299702199166,22sleep10-21swapper/107:06:111
1195121770,6sleep33075199cyclictest07:21:523
928021460,5sleep13074999cyclictest07:30:381
104062850,4sleep3391rcuc/307:27:173
230362780,2sleep223034-21grep07:25:282
309452770,5sleep330968-21rm07:30:243
211992660,4sleep121165-21sh07:27:561
20302620,3sleep02025-21sort07:26:380
113482600,3sleep211367-21spawn07:22:122
186852580,7sleep03074899cyclictest07:22:260
427291570,1ptp4l401ktimersoftd/311:41:403
240882570,2sleep00-21swapper/009:10:200
427291560,1ptp4l401ktimersoftd/311:56:083
427291550,1ptp4l391rcuc/310:03:423
207532550,7sleep2321ktimersoftd/210:10:002
3074999532,48cyclictest16163-21ls12:10:011
95032500,1sleep00-21swapper/009:45:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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