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2026-04-20 - 18:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Mon Apr 20, 2026 12:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
51842205167,26sleep20-21swapper/207:08:562
138591203169,23phc2sys0-21swapper/307:08:293
49522201172,19sleep00-21swapper/007:05:560
49042201168,22sleep10-21swapper/107:05:281
1570321560,6sleep2556999cyclictest10:45:132
1570321560,6sleep2556999cyclictest10:45:132
1882821380,5sleep3557099cyclictest10:50:193
78302670,1sleep20-21swapper/210:30:012
5570996230,8cyclictest41-21ksoftirqd/311:20:253
5570996230,8cyclictest41-21ksoftirqd/309:55:153
5570995830,8cyclictest41-21ksoftirqd/307:55:163
5570995827,4cyclictest41-21ksoftirqd/311:35:213
5570995728,9cyclictest41-21ksoftirqd/309:35:263
5570995725,4cyclictest41-21ksoftirqd/309:30:173
5570995627,8cyclictest41-21ksoftirqd/307:45:233
5570995627,4cyclictest41-21ksoftirqd/312:00:193
5570995627,3cyclictest41-21ksoftirqd/312:40:013
5570995626,8cyclictest41-21ksoftirqd/312:20:253
5570995626,4cyclictest41-21ksoftirqd/309:25:253
5570995626,3cyclictest41-21ksoftirqd/311:10:253
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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