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2025-11-08 - 21:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sat Nov 08, 2025 12:45:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
133122230,5sleep01369-21multi.sh07:09:430
133122230,5sleep01369-21multi.sh07:09:430
961322100,5sleep29593-21sh07:08:442
961322100,5sleep29593-21sh07:08:442
629422050,7sleep341-21ksoftirqd/307:08:403
629422050,7sleep341-21ksoftirqd/307:08:403
1902921880,4sleep10-21swapper/107:07:141
1902921880,4sleep10-21swapper/107:07:141
2594521530,3sleep00-21swapper/010:25:000
1752721460,6sleep11226299cyclictest11:10:261
137121280,3sleep31226499cyclictest07:12:093
12264996634,7cyclictest41-21ksoftirqd/308:00:003
294842640,6sleep129458-21sh07:10:271
12264995928,7cyclictest41-21ksoftirqd/308:20:003
12261995822,5cyclictest9-21ksoftirqd/007:20:170
12261995821,5cyclictest9-21ksoftirqd/010:00:240
134991570,1ptp4l401ktimersoftd/312:03:413
12264995728,3cyclictest41-21ksoftirqd/312:05:163
134991550,1ptp4l401ktimersoftd/312:11:243
134991550,1ptp4l401ktimersoftd/311:55:133
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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