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2026-08-23 - 06:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sun Aug 23, 2026 00:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
106052205172,22sleep10-21swapper/119:06:041
106092202168,22sleep00-21swapper/019:06:080
138591201167,23phc2sys0-21swapper/319:05:333
106382198167,19sleep20-21swapper/219:06:302
220172640,4sleep322020-21cpuspeed_turbos23:50:123
36302570,1sleep30-21swapper/322:10:003
185092570,4sleep118513-21unixbench_singl20:25:271
246352560,2sleep00-21swapper/023:55:120
138491560,1ptp4l401ktimersoftd/320:41:453
265012520,4sleep326503-21cpuspeed22:55:133
68622510,1sleep06860-21entropy20:05:160
197732510,3sleep219776-21irqrtprio19:25:192
11362994830,15cyclictest25-21ksoftirqd/119:59:591
11362994612,32cyclictest18373-21kworker/1:120:39:041
11362994523,4cyclictest25-21ksoftirqd/119:25:581
1136299450,43cyclictest0-21swapper/100:06:041
138491440,0ptp4l401ktimersoftd/320:15:123
138491440,0ptp4l401ktimersoftd/319:58:473
11362994425,17cyclictest25-21ksoftirqd/119:21:581
11362994415,27cyclictest0-21swapper/121:25:331
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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