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2026-03-24 - 15:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Tue Mar 24, 2026 00:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591229167,50phc2sys0-21swapper/319:06:173
167922201168,21sleep20-21swapper/219:08:332
165542200167,22sleep00-21swapper/019:05:340
146882199167,21sleep10-21swapper/119:05:121
2831221610,6sleep21719699cyclictest20:35:232
183802620,4sleep31719799cyclictest00:35:203
138491510,1ptp4l401ktimersoftd/323:27:283
15662500,2sleep10-21swapper/120:45:281
138491440,1ptp4l401ktimersoftd/321:31:143
17197994338,3cyclictest14601-21turbostat.cron00:30:003
17197994035,3cyclictest19395-21sh23:35:003
17197993934,3cyclictest41-21ksoftirqd/320:30:013
17197993933,3cyclictest41-21ksoftirqd/323:00:003
17196993927,10cyclictest33-21ksoftirqd/222:49:332
138491390,0ptp4l401ktimersoftd/300:34:303
17197993832,3cyclictest41-21ksoftirqd/323:55:003
17194993830,5cyclictest24320-21cron23:45:010
138491380,1ptp4l401ktimersoftd/321:21:233
135191380,1getstats0-21swapper/321:02:553
50798370,4rtkit-daemon0-21swapper/300:07:073
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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