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2026-01-16 - 09:07
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Fri Jan 16, 2026 00:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
234212203171,21sleep20-21swapper/219:06:152
138591203169,23phc2sys0-21swapper/319:08:283
233622202167,23sleep10-21swapper/119:05:301
233482202168,22sleep00-21swapper/019:05:280
1075521520,6sleep12401099cyclictest23:00:251
3219521510,6sleep32401299cyclictest23:45:163
12472620,7sleep32401299cyclictest21:40:013
138491560,1ptp4l401ktimersoftd/323:01:013
113002560,4sleep111294-21latency_hist22:00:001
289542550,1sleep30-21swapper/322:35:003
24011995518,4cyclictest33-21ksoftirqd/200:20:002
292582540,1sleep20-21swapper/220:25:132
24011995421,6cyclictest33-21ksoftirqd/222:40:012
24011995411,6cyclictest33-21ksoftirqd/222:20:232
24011995319,8cyclictest33-21ksoftirqd/220:25:002
24011995218,9cyclictest33-21ksoftirqd/221:45:002
24011995218,9cyclictest33-21ksoftirqd/221:45:002
24011995218,6cyclictest33-21ksoftirqd/222:00:012
24011995216,4cyclictest33-21ksoftirqd/200:40:002
24010995245,4cyclictest11235-21sh19:50:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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