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2026-06-15 - 19:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Mon Jun 15, 2026 00:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591204170,23phc2sys0-21swapper/319:09:223
243022201166,23sleep00-21swapper/019:06:340
242462200167,22sleep10-21swapper/119:05:511
242822199167,21sleep20-21swapper/219:06:202
142721620,6sleep12486599cyclictest23:45:241
285012650,6sleep32486799cyclictest22:30:213
138491600,1ptp4l401ktimersoftd/320:50:233
288842560,2sleep00-21swapper/019:15:250
138491560,1ptp4l401ktimersoftd/322:05:163
138491560,1ptp4l401ktimersoftd/319:54:293
138491550,1ptp4l401ktimersoftd/319:15:253
289922540,2sleep10-21swapper/119:15:261
317312530,6sleep341-21ksoftirqd/320:27:093
263922510,2sleep00-21swapper/019:10:240
138491470,1ptp4l401ktimersoftd/322:55:243
24866994539,3cyclictest33-21ksoftirqd/220:10:002
2486699431,11cyclictest0-21swapper/220:05:002
138491430,0ptp4l401ktimersoftd/323:24:123
138491430,0ptp4l401ktimersoftd/321:25:133
138491420,0ptp4l401ktimersoftd/300:15:313
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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