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2026-06-01 - 19:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Mon Jun 01, 2026 12:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120452205173,21sleep10-21swapper/107:07:051
120452205173,21sleep10-21swapper/107:07:051
121862204170,22sleep30-21swapper/307:08:563
121862204170,22sleep30-21swapper/307:08:563
122692202166,24sleep00-21swapper/007:09:580
122692202166,24sleep00-21swapper/007:09:580
119642197165,21sleep20-21swapper/207:06:022
119642197165,21sleep20-21swapper/207:06:022
268592640,5sleep3391rcuc/312:00:003
1385916137,16phc2sys0-21swapper/307:10:013
1257099607,10cyclictest3957-21ls10:05:240
138491590,0ptp4l401ktimersoftd/311:00:233
1257099595,16cyclictest10914-21irqrtprio09:15:180
1257099585,16cyclictest31928-21latency_hist10:00:000
151962570,2sleep00-21swapper/008:20:130
138491570,1ptp4l391rcuc/307:55:423
1257099574,18cyclictest27722-21df_abs08:45:160
1257099574,16cyclictest5036-21cstates12:20:130
1257099565,16cyclictest31028-21expr11:00:220
59282550,3sleep30-21swapper/308:00:183
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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