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2026-06-13 - 01:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Fri Jun 12, 2026 12:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591236168,23phc2sys0-21swapper/307:09:493
125072199167,21sleep20-21swapper/207:09:172
124162197164,22sleep10-21swapper/107:08:101
124472194161,21sleep00-21swapper/007:08:340
1256625839,10sleep20-21swapper/207:10:012
290482570,3sleep30-21swapper/307:40:253
138491570,1ptp4l401ktimersoftd/310:57:473
138491560,1ptp4l401ktimersoftd/310:17:263
165882520,2sleep30-21swapper/309:25:243
20742510,2sleep30-21swapper/307:50:283
138491480,24ptp4l35792irq/125-enp1s0-11:30:233
12859994716,29cyclictest0-21swapper/209:30:332
1285999450,44cyclictest0-21swapper/212:36:242
1285899430,42cyclictest0-21swapper/111:33:421
138491420,0ptp4l401ktimersoftd/308:45:303
12859994214,26cyclictest0-21swapper/209:55:232
12857994236,3cyclictest14884-21grep10:30:010
50798410,4rtkit-daemon5612-21if_enp1s011:15:152
12859994113,27cyclictest0-21swapper/207:53:442
12857994136,3cyclictest15093-21cron07:15:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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