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2026-08-28 - 01:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Thu Aug 27, 2026 12:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
253792205170,23sleep00-21swapper/007:05:490
254672204170,23sleep10-21swapper/107:06:571
138591204170,22phc2sys0-21swapper/307:07:023
253862199167,21sleep20-21swapper/207:05:542
416621430,6sleep22622499cyclictest07:30:142
26222996119,5cyclictest25-21ksoftirqd/112:05:171
26222995825,4cyclictest25-21ksoftirqd/108:20:011
26222995527,3cyclictest25-21ksoftirqd/108:00:001
26222995426,7cyclictest25-21ksoftirqd/108:15:001
26222995322,6cyclictest25-21ksoftirqd/110:10:001
26222995222,4cyclictest25-21ksoftirqd/111:50:191
36072510,3sleep30-21swapper/310:45:153
26222995014,4cyclictest25-21ksoftirqd/107:50:271
2622299498,7cyclictest25-21ksoftirqd/111:40:251
26222994921,4cyclictest25-21ksoftirqd/111:45:141
26222994918,3cyclictest25-21ksoftirqd/112:30:231
26222994918,3cyclictest25-21ksoftirqd/108:05:181
26222994917,4cyclictest25-21ksoftirqd/111:35:151
26222994917,4cyclictest25-21ksoftirqd/110:15:131
26222994915,3cyclictest25-21ksoftirqd/112:20:221
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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