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2026-08-22 - 17:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sat Aug 22, 2026 12:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591220152,23phc2sys0-21swapper/307:07:523
254352203169,23sleep10-21swapper/107:07:041
254362201167,22sleep20-21swapper/207:07:042
253152201168,21sleep00-21swapper/007:05:290
1535821380,2sleep22596799cyclictest12:10:242
910221260,6sleep12596699cyclictest07:40:161
2567128262,11sleep20-21swapper/207:10:012
138491580,1ptp4l401ktimersoftd/311:42:363
138491570,1ptp4l401ktimersoftd/307:33:593
138491570,1ptp4l401ktimersoftd/307:33:583
25965995045,3cyclictest18563-21latency_hist10:10:000
50798460,35rtkit-daemon9-21ksoftirqd/012:38:230
2596799452,7cyclictest33-21ksoftirqd/210:03:572
25967994337,4cyclictest33-21ksoftirqd/210:00:002
25965994336,4cyclictest13648-21wc10:00:000
138491430,0ptp4l401ktimersoftd/312:21:263
138491430,0ptp4l401ktimersoftd/308:35:183
2596899420,2cyclictest121rcu_preempt11:25:243
2596899420,2cyclictest121rcu_preempt08:45:253
138491420,0ptp4l401ktimersoftd/310:45:213
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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