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2026-03-26 - 16:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Thu Mar 26, 2026 12:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
194312231166,21sleep00-21swapper/007:08:420
193752220193,18sleep10-21swapper/107:07:591
194092206172,23sleep30-21swapper/307:08:253
192672205171,23sleep20-21swapper/207:06:352
880321670,7sleep11983099cyclictest08:55:251
214921380,6sleep21983199cyclictest07:40:002
2963021340,6sleep21983199cyclictest08:35:012
799421320,5sleep11983099cyclictest11:05:271
2596121280,2sleep21983199cyclictest09:30:242
1983099669,17cyclictest4638-21/usr/sbin/munin09:55:111
19830996211,10cyclictest1433-21sed08:40:251
19830996210,17cyclictest5933-21ls11:00:251
19830996111,10cyclictest30887-21cat10:45:261
19830996110,18cyclictest12328-21df_abs11:15:141
1983099609,10cyclictest2139-21cpuspeed_turbos12:00:131
1983099607,16cyclictest0-21swapper/111:35:201
19830996011,10cyclictest15076-21expr09:10:121
1983099599,12cyclictest18503-21ls11:25:261
1983099599,10cyclictest24554-21date09:30:001
19830995912,9cyclictest5045-21expr07:45:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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