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2026-03-07 - 04:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Fri Mar 06, 2026 12:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591208149,47phc2sys0-21swapper/307:05:073
137662203171,21sleep20-21swapper/207:09:552
135442199166,22sleep00-21swapper/007:07:070
134302199167,21sleep10-21swapper/107:05:401
134991710,1getstats6296-1kworker/3:2H10:38:553
1421599679,17cyclictest23709-21lockfile-remove09:40:000
1421599646,15cyclictest23725-21cat08:35:000
14218996327,12cyclictest41-21ksoftirqd/309:55:263
14218996226,8cyclictest41-21ksoftirqd/312:30:013
14218996129,3cyclictest41-21ksoftirqd/309:00:013
1421599616,15cyclictest30810-21cat12:00:270
14218996030,9cyclictest41-21ksoftirqd/310:15:003
14218996025,8cyclictest41-21ksoftirqd/312:05:193
14218996022,7cyclictest41-21ksoftirqd/307:55:123
1421599605,11cyclictest1450-21sed07:50:000
1421599605,11cyclictest13134-21cut10:20:230
1421599605,11cyclictest13134-21cut10:20:230
14218995929,7cyclictest41-21ksoftirqd/310:00:153
14218995923,7cyclictest41-21ksoftirqd/308:50:113
14218995923,7cyclictest41-21ksoftirqd/308:50:113
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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