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2025-12-25 - 05:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Thu Dec 25, 2025 00:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
170582201167,23sleep10-21swapper/119:08:201
170282201168,22sleep30-21swapper/319:07:583
170872198165,22sleep00-21swapper/019:08:430
170592198166,21sleep20-21swapper/219:08:212
2302821470,6sleep31748299cyclictest21:30:173
1718828459,16sleep10-21swapper/119:10:011
1718828459,16sleep10-21swapper/119:10:011
17481996632,3cyclictest33-21ksoftirqd/221:35:222
17480996511,18cyclictest13315-21cut20:05:191
17479996329,4cyclictest9-21ksoftirqd/021:05:010
17479996126,10cyclictest9-21ksoftirqd/000:15:000
17479996026,10cyclictest9-21ksoftirqd/019:40:190
17479995925,8cyclictest9-21ksoftirqd/022:25:180
17481995828,7cyclictest33-21ksoftirqd/222:00:002
17480995710,19cyclictest19580-21seq20:19:151
1747999577,8cyclictest9-21ksoftirqd/020:55:130
17479995727,4cyclictest9-21ksoftirqd/022:50:160
17479995723,9cyclictest9-21ksoftirqd/022:05:180
17479995721,3cyclictest9-21ksoftirqd/020:45:250
17479995622,9cyclictest9-21ksoftirqd/020:30:170
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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