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2026-08-18 - 09:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Tue Aug 18, 2026 00:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591206173,22phc2sys0-21swapper/319:09:443
138591206173,22phc2sys0-21swapper/319:09:433
291172205173,22sleep10-21swapper/119:08:351
291172205173,22sleep10-21swapper/119:08:351
290262200167,22sleep20-21swapper/219:07:232
290262200167,22sleep20-21swapper/219:07:232
290562199166,22sleep00-21swapper/019:07:450
290562199166,22sleep00-21swapper/019:07:450
2371321650,7sleep22952299cyclictest23:20:012
138491790,1ptp4l11043-21switchtime19:35:243
76482610,6sleep32952399cyclictest22:45:193
2952299590,22cyclictest2539-21cat20:25:192
2952299590,20cyclictest32394-21df_abs19:15:142
2952299550,29cyclictest25630-21awk23:20:262
138491530,1ptp4l401ktimersoftd/300:15:183
29523995233,16cyclictest41-21ksoftirqd/319:20:003
2952299512,19cyclictest9126-21cat23:55:012
195522510,3sleep20-21swapper/200:15:132
50798470,1rtkit-daemon0-21swapper/021:42:530
138491470,0ptp4l401ktimersoftd/323:32:403
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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