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2026-05-01 - 02:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Thu Apr 30, 2026 12:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591223162,49phc2sys0-21swapper/307:07:313
179262208147,50sleep10-21swapper/107:05:261
182302201167,22sleep00-21swapper/007:09:220
181652200168,21sleep20-21swapper/207:08:322
3167921680,5sleep31858399cyclictest10:50:163
18580996911,16cyclictest654-21polkitd10:09:070
138491690,1ptp4l14912-21tune2fs09:15:153
18582996828,6cyclictest33-21ksoftirqd/210:09:222
49452650,2sleep10-21swapper/111:00:251
1858099659,12cyclictest16667-21cut08:10:150
1858099659,11cyclictest2586-21threads10:55:260
1385916346,9phc2sys0-21swapper/307:10:013
18582996226,6cyclictest33-21ksoftirqd/207:55:232
18582996223,7cyclictest33-21ksoftirqd/210:30:192
1858099629,11cyclictest25037-21awk11:40:240
1858099625,17cyclictest0-21swapper/011:20:180
18582996128,7cyclictest33-21ksoftirqd/211:25:132
18582996127,6cyclictest33-21ksoftirqd/207:15:122
18582996031,3cyclictest33-21ksoftirqd/211:35:242
18582996028,6cyclictest33-21ksoftirqd/211:10:162
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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