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2026-07-09 - 17:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Thu Jul 09, 2026 12:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
38602226165,50sleep20-21swapper/207:07:192
38592204171,22sleep10-21swapper/107:07:191
138591204170,23phc2sys0-21swapper/307:05:073
37982199165,22sleep00-21swapper/007:06:280
138491690,1ptp4l401ktimersoftd/308:15:043
138491660,1ptp4l401ktimersoftd/309:51:433
138491620,1ptp4l401ktimersoftd/309:24:063
74432580,3sleep00-21swapper/011:35:200
123702580,7sleep3436999cyclictest07:25:133
436899573,6cyclictest26532-21sed08:59:592
138491570,1ptp4l401ktimersoftd/309:55:153
138491570,1ptp4l401ktimersoftd/309:46:103
4368995628,4cyclictest33-21ksoftirqd/208:50:152
4368995529,10cyclictest33-21ksoftirqd/211:15:192
138491550,1ptp4l401ktimersoftd/310:51:033
138491550,1ptp4l401ktimersoftd/308:30:233
169482540,3sleep30-21swapper/307:35:113
4368995327,9cyclictest33-21ksoftirqd/207:30:262
436899523,6cyclictest321ktimersoftd/209:09:592
158832510,2sleep20-21swapper/208:35:242
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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