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2026-08-21 - 02:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Thu Aug 20, 2026 12:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591204170,23phc2sys0-21swapper/307:09:553
240402202169,21sleep20-21swapper/207:09:272
237732201167,23sleep10-21swapper/107:05:561
237452200166,22sleep00-21swapper/007:05:350
2527721450,5sleep12438099cyclictest09:20:181
24382996425,7cyclictest41-21ksoftirqd/310:45:013
24380996328,8cyclictest25-21ksoftirqd/112:00:001
24382996229,8cyclictest41-21ksoftirqd/312:15:003
76482610,6sleep32438299cyclictest07:40:163
24382996128,7cyclictest41-21ksoftirqd/312:00:003
24382996126,4cyclictest41-21ksoftirqd/308:50:013
24380996128,4cyclictest25-21ksoftirqd/110:00:011
24382996026,3cyclictest41-21ksoftirqd/311:45:003
24382996025,8cyclictest41-21ksoftirqd/308:25:233
24382996025,8cyclictest41-21ksoftirqd/308:25:233
24382995923,8cyclictest41-21ksoftirqd/308:05:233
24382995826,8cyclictest41-21ksoftirqd/311:25:003
24382995824,8cyclictest41-21ksoftirqd/312:35:003
24380995830,6cyclictest25-21ksoftirqd/108:30:001
24380995830,6cyclictest25-21ksoftirqd/108:30:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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