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2026-04-30 - 11:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Thu Apr 30, 2026 00:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
211552204175,19sleep10-21swapper/119:09:361
211552204175,19sleep10-21swapper/119:09:351
138591204169,24phc2sys0-21swapper/319:06:493
138591204169,24phc2sys0-21swapper/319:06:493
208822201167,22sleep00-21swapper/019:06:000
208822201167,22sleep00-21swapper/019:06:000
209722200167,21sleep20-21swapper/219:07:112
209722200167,21sleep20-21swapper/219:07:112
18222770,2sleep20-21swapper/220:40:142
192892680,2sleep219142-21cstates00:20:142
2149199621,28cyclictest12529-21/usr/sbin/munin00:00:283
21489996128,4cyclictest25-21ksoftirqd/123:15:011
2148899607,42cyclictest7251-21grep22:00:130
2148899607,42cyclictest7251-21grep22:00:130
2148899602,16cyclictest25500-21awk20:20:250
2148899597,6cyclictest31171-21latency_hist19:29:590
253582570,5sleep233-21ksoftirqd/220:20:242
21489995725,4cyclictest25-21ksoftirqd/119:50:001
21489995724,4cyclictest25-21ksoftirqd/121:45:281
2149199560,23cyclictest276502sleep323:02:043
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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