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2026-07-25 - 14:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sat Jul 25, 2026 00:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591203169,23phc2sys0-21swapper/319:06:113
26732202168,22sleep20-21swapper/219:06:122
27992200168,21sleep10-21swapper/119:07:431
27662198164,23sleep00-21swapper/019:07:180
1385918363,10phc2sys0-21swapper/319:10:013
138491650,1ptp4l401ktimersoftd/322:49:233
138491650,1ptp4l401ktimersoftd/320:29:313
3268996222,7cyclictest25-21ksoftirqd/122:35:151
3268996123,7cyclictest25-21ksoftirqd/100:35:241
3268996030,4cyclictest25-21ksoftirqd/122:40:191
3268996021,7cyclictest25-21ksoftirqd/119:25:171
3268995623,10cyclictest25-21ksoftirqd/123:10:261
138491560,1ptp4l401ktimersoftd/320:06:313
138491540,1ptp4l401ktimersoftd/323:45:553
17192530,3sleep20-21swapper/221:15:202
17192530,3sleep20-21swapper/221:15:202
138491530,1ptp4l401ktimersoftd/320:42:253
3268995221,4cyclictest25-21ksoftirqd/121:35:171
138491520,1ptp4l401ktimersoftd/321:48:093
3268995019,7cyclictest25-21ksoftirqd/123:35:201
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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