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2026-03-10 - 07:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Tue Mar 10, 2026 00:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591208140,23phc2sys0-21swapper/319:06:583
237682203170,21sleep10-21swapper/119:09:041
235372203170,22sleep20-21swapper/219:06:122
237992201167,22sleep00-21swapper/019:09:280
1094221220,2sleep22413499cyclictest19:45:272
2384128562,15sleep10-21swapper/119:10:001
138491570,1ptp4l401ktimersoftd/322:41:103
24135995629,3cyclictest41-21ksoftirqd/322:25:243
138491560,1ptp4l401ktimersoftd/319:55:173
113352540,1sleep30-21swapper/320:55:003
24135995233,10cyclictest41-21ksoftirqd/322:30:243
247442510,2sleep00-21swapper/022:25:190
24134994931,3cyclictest33-21ksoftirqd/223:10:322
24135994817,4cyclictest41-21ksoftirqd/300:05:003
24135994812,9cyclictest41-21ksoftirqd/320:05:183
24135994716,7cyclictest41-21ksoftirqd/300:30:253
107242470,2sleep00-21swapper/021:55:260
2413599452,2cyclictest121rcu_preempt00:25:003
2413599447,8cyclictest41-21ksoftirqd/319:50:003
24135994431,10cyclictest41-21ksoftirqd/321:15:253
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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