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2026-08-27 - 00:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Wed Aug 26, 2026 12:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591205171,23phc2sys0-21swapper/307:05:103
12252205171,22sleep10-21swapper/107:09:011
9592204169,23sleep00-21swapper/007:05:400
10442201168,21sleep20-21swapper/207:06:462
138591161122,14phc2sys0-21swapper/307:10:013
3004521190,2sleep2161799cyclictest08:05:182
161699670,26cyclictest16152-21cron08:45:001
161699657,22cyclictest20791-21date09:55:261
161699650,24cyclictest22605-21/usr/sbin/munin07:50:191
161699610,24cyclictest25850-21/usr/sbin/munin07:55:261
161699600,23cyclictest30862-21chrt12:26:101
161699590,22cyclictest15949-21chrt11:57:531
161699590,22cyclictest15949-21chrt11:57:531
161699580,23cyclictest9673-21/usr/sbin/munin07:25:151
161699580,23cyclictest4748-21/usr/sbin/munin09:25:191
161699570,23cyclictest4755-21/usr/sbin/munin08:20:161
161699570,21cyclictest27013-21/usr/sbin/munin08:00:141
56032560,2sleep2311rcuc/207:15:232
161699561,22cyclictest11386-21turbostat.cron09:44:551
161699560,22cyclictest20348-21/usr/sbin/munin12:05:241
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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