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2026-09-01 - 18:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Tue Sep 01, 2026 12:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
70372204170,22sleep30-21swapper/307:07:073
71552203169,22sleep10-21swapper/107:08:381
71192201167,22sleep20-21swapper/207:08:112
71442200167,22sleep00-21swapper/007:08:290
1980921480,2sleep20-21swapper/209:45:122
2035121390,5sleep0756099cyclictest11:55:120
138491620,1ptp4l401ktimersoftd/312:30:253
138491620,1ptp4l401ktimersoftd/312:30:253
138491600,1ptp4l401ktimersoftd/308:40:273
206612590,2sleep10-21swapper/111:55:121
176082540,1sleep317561-21cstates09:40:123
756299529,25cyclictest4642-21awk11:20:262
314552510,2sleep20-21swapper/210:05:262
236942500,1sleep10-21swapper/110:55:201
7562994918,29cyclictest0-21swapper/210:50:232
135191480,6getstats756399cyclictest07:52:063
7562994226,13cyclictest33-21ksoftirqd/208:11:402
138491410,0ptp4l401ktimersoftd/311:01:533
138491410,0ptp4l401ktimersoftd/310:00:143
7563994035,3cyclictest1141-21fschecks_count12:20:143
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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