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2026-05-27 - 04:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Wed May 27, 2026 00:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
142462230169,49sleep10-21swapper/119:07:421
138591230168,50phc2sys0-21swapper/319:07:193
143862203169,22sleep20-21swapper/219:09:322
140772202167,24sleep00-21swapper/019:05:360
682421770,7sleep11471799cyclictest19:55:241
41421300,6sleep21471899cyclictest21:55:152
7412760,7sleep11471799cyclictest20:50:191
7412760,7sleep11471799cyclictest20:50:191
1471899585,11cyclictest24410-21chrt20:31:032
1471699583,10cyclictest23561-21cat23:45:180
1471899565,18cyclictest24025-21chrt22:40:322
1471899564,11cyclictest8647-21needreboot21:05:222
135191560,7getstats1471999cyclictest19:38:233
1471899554,11cyclictest318392sleep220:45:512
1471899554,11cyclictest318392sleep220:45:512
14718995511,14cyclictest30029-21grep22:55:122
1471699558,9cyclictest1303-21runrttasks22:15:110
138491550,0ptp4l391rcuc/321:55:243
1471899546,11cyclictest19676-21taskset22:35:052
1471899544,15cyclictest1319-21snmpd19:14:522
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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