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2026-03-11 - 07:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Wed Mar 11, 2026 00:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591205171,23phc2sys0-21swapper/319:08:343
250992201168,22sleep10-21swapper/119:08:481
251302199165,22sleep20-21swapper/219:09:132
249292199166,22sleep00-21swapper/019:06:340
397321650,6sleep12563299cyclictest23:50:121
1927821440,5sleep02563199cyclictest21:05:240
138491700,0ptp4l401ktimersoftd/322:10:123
25633996632,7cyclictest33-21ksoftirqd/200:26:452
323552610,2sleep30-21swapper/322:35:263
25633996126,6cyclictest33-21ksoftirqd/220:50:252
2563299615,16cyclictest15275-21latency_hist21:00:001
2563299605,16cyclictest23645-21/usr/sbin/munin20:10:161
138491600,1ptp4l401ktimersoftd/323:15:263
25633995927,6cyclictest33-21ksoftirqd/200:10:022
25633995926,9cyclictest33-21ksoftirqd/219:45:002
25633995923,6cyclictest33-21ksoftirqd/221:20:212
25633995829,10cyclictest33-21ksoftirqd/200:15:142
25633995828,4cyclictest33-21ksoftirqd/221:35:012
25633995824,4cyclictest33-21ksoftirqd/223:10:132
25633995728,4cyclictest33-21ksoftirqd/200:35:142
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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