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2026-02-26 - 16:30
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Thu Feb 26, 2026 12:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
144982204172,21sleep20-21swapper/207:07:342
144392203169,22sleep00-21swapper/007:06:480
145282202168,23sleep10-21swapper/107:07:561
138591202168,23phc2sys0-21swapper/307:05:043
239521830,5sleep21498999cyclictest08:55:002
147022162122,14sleep00-21swapper/007:10:010
147022162122,14sleep00-21swapper/007:10:010
1974221600,4sleep21498999cyclictest10:35:142
2032321400,7sleep11498899cyclictest07:20:121
14990997310,23cyclictest20606-21cut08:25:183
99592610,2sleep30-21swapper/309:10:143
186492570,5sleep11498899cyclictest08:20:211
138491550,1ptp4l391rcuc/307:35:263
271642540,2sleep027168-21cpuspeed09:45:130
14989995322,6cyclictest33-21ksoftirqd/211:59:592
300702520,1sleep00-21swapper/007:40:130
22812510,1sleep30-21swapper/310:00:133
138491480,1ptp4l391rcuc/307:30:383
1499099476,26cyclictest25154-21sort09:40:153
14989994510,6cyclictest33-21ksoftirqd/207:20:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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