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2026-07-22 - 20:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Wed Jul 22, 2026 12:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
117652204170,23sleep10-21swapper/107:06:441
138591202169,22phc2sys0-21swapper/307:06:463
117142199166,22sleep20-21swapper/207:06:032
117022195161,23sleep00-21swapper/007:05:530
3269721720,6sleep21232199cyclictest08:55:162
2361021690,8sleep11232099cyclictest07:30:181
614621610,2sleep01231999cyclictest11:15:220
1385918764,12phc2sys0-21swapper/307:10:013
12321996428,4cyclictest33-21ksoftirqd/207:15:202
12320996411,13cyclictest5113-21cut10:10:121
12322996327,4cyclictest41-21ksoftirqd/307:35:193
12321996331,8cyclictest33-21ksoftirqd/212:35:162
12320996312,12cyclictest204822chrt11:45:151
12321996230,5cyclictest33-21ksoftirqd/209:15:152
12321996128,4cyclictest33-21ksoftirqd/208:25:202
12321996126,4cyclictest33-21ksoftirqd/210:15:132
12322996029,7cyclictest41-21ksoftirqd/311:40:003
12322996026,10cyclictest41-21ksoftirqd/308:05:013
12322996021,4cyclictest41-21ksoftirqd/312:00:193
12321996026,4cyclictest33-21ksoftirqd/207:55:282
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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