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2026-08-29 - 13:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sat Aug 29, 2026 00:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
63892206173,22sleep00-21swapper/019:06:260
65962205172,22sleep10-21swapper/119:09:071
138591205171,23phc2sys0-21swapper/319:08:383
64532201167,23sleep20-21swapper/219:07:162
43821360,1sleep10-21swapper/120:00:181
144272620,3sleep30-21swapper/321:30:273
308372570,2sleep10-21swapper/100:15:171
138491570,1ptp4l401ktimersoftd/323:16:023
190472560,6sleep2710299cyclictest23:50:242
123132500,2sleep20-21swapper/223:40:002
7100994628,16cyclictest9-21ksoftirqd/021:00:570
279142450,2sleep00-21swapper/019:50:190
138491450,1ptp4l401ktimersoftd/320:02:203
710399442,39cyclictest22170-21cron22:55:003
7103994237,3cyclictest30285-21fschecks_count23:10:143
138491410,1ptp4l401ktimersoftd/319:14:523
138491400,0ptp4l401ktimersoftd/321:58:163
7101993934,3cyclictest25-21ksoftirqd/122:40:001
7101993934,3cyclictest25-21ksoftirqd/122:29:591
7101993934,3cyclictest25-21ksoftirqd/120:24:591
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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