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2026-08-08 - 04:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sat Aug 08, 2026 00:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
207742233167,22sleep30-21swapper/319:05:083
227032203169,22sleep00-21swapper/019:06:220
207682200168,21sleep20-21swapper/219:05:032
207672200167,22sleep10-21swapper/119:05:021
270262610,2sleep30-21swapper/321:25:253
270262610,2sleep30-21swapper/321:25:243
138491600,0ptp4l401ktimersoftd/323:40:253
138491580,49ptp4l0-21swapper/319:10:003
138491560,1ptp4l401ktimersoftd/320:24:033
151372550,2sleep20-21swapper/223:15:002
50798500,22rtkit-daemon8881-21iostat_ios20:50:170
189402460,3sleep318941-21irqrtprio00:25:173
23286994539,3cyclictest12690-21latency_hist23:10:002
138491430,1ptp4l401ktimersoftd/321:42:433
138491420,0ptp4l401ktimersoftd/323:45:223
138491410,0ptp4l401ktimersoftd/320:05:143
23287994028,10cyclictest41-21ksoftirqd/320:25:113
23286993933,3cyclictest12820-21sh21:00:002
23286993911,27cyclictest0-21swapper/200:20:242
138491390,1ptp4l401ktimersoftd/322:18:523
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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