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2026-03-15 - 08:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sun Mar 15, 2026 00:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591224162,51phc2sys0-21swapper/319:06:013
139312205171,22sleep20-21swapper/219:09:272
137932205170,23sleep10-21swapper/119:07:371
138792200166,22sleep00-21swapper/019:08:440
1667021710,2sleep316675-21cpuspeed_turbos20:20:123
275712760,3sleep027575-21irqrtprio20:40:180
1427099596,16cyclictest18928-21latency_hist20:25:012
1427099574,16cyclictest900-21cat21:55:272
1427099574,16cyclictest29848-21df_abs00:00:162
1427099562,16cyclictest0-21swapper/223:30:162
138491560,1ptp4l401ktimersoftd/323:05:143
117422560,4sleep31427199cyclictest20:10:123
1427099555,17cyclictest10951-21systemctl23:20:222
1427099552,15cyclictest0-21swapper/200:06:392
1427099541,14cyclictest0-21swapper/221:20:212
1427099524,6cyclictest20845-21grep22:35:252
1427099523,9cyclictest1319-21snmpd00:15:412
1427099521,17cyclictest0-21swapper/220:45:032
138491520,1ptp4l401ktimersoftd/319:48:193
1427099515,8cyclictest2852-21cut23:05:182
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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