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2026-06-20 - 10:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sat Jun 20, 2026 00:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591235167,23phc2sys0-21swapper/319:09:363
103682203170,22sleep20-21swapper/219:07:082
103672202169,22sleep10-21swapper/119:07:071
102892200166,22sleep00-21swapper/019:06:060
2428021690,6sleep11088199cyclictest21:45:211
1385918361,14phc2sys0-21swapper/319:10:013
138491640,1ptp4l401ktimersoftd/319:41:123
10881996219,9cyclictest25-21ksoftirqd/119:40:261
80322610,2sleep00-21swapper/023:25:140
10881996015,10cyclictest25-21ksoftirqd/121:55:271
301522560,6sleep11088199cyclictest19:45:261
134991550,2getstats0-21swapper/320:30:253
10881995520,4cyclictest25-21ksoftirqd/120:05:181
10881995517,4cyclictest25-21ksoftirqd/122:00:231
138491540,0ptp4l401ktimersoftd/323:55:043
10881995423,9cyclictest25-21ksoftirqd/120:10:181
10881995415,9cyclictest25-21ksoftirqd/121:40:171
10881995412,6cyclictest25-21ksoftirqd/121:15:141
1088199538,8cyclictest25-21ksoftirqd/100:10:251
10881995320,6cyclictest25-21ksoftirqd/123:30:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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