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2026-04-04 - 00:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Fri Apr 03, 2026 12:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
40002205170,23sleep10-21swapper/107:09:141
138591205171,23phc2sys0-21swapper/307:05:103
39032201168,22sleep20-21swapper/207:08:062
17752201166,24sleep00-21swapper/007:05:030
138491740,1ptp4l391rcuc/309:30:223
4351995930,7cyclictest9-21ksoftirqd/008:59:590
88672580,2sleep30-21swapper/310:30:243
288882580,3sleep20-21swapper/212:15:262
10722560,2sleep11075-21sendmail_mailqu09:10:241
4351995424,6cyclictest9-21ksoftirqd/009:10:150
4354995326,8cyclictest41-21ksoftirqd/311:30:133
4354995223,7cyclictest41-21ksoftirqd/311:45:003
4354995219,7cyclictest41-21ksoftirqd/309:25:013
4353995232,18cyclictest33-21ksoftirqd/207:17:212
4351995222,7cyclictest9-21ksoftirqd/012:05:150
4351995125,3cyclictest9-21ksoftirqd/011:35:160
4351995123,3cyclictest9-21ksoftirqd/007:30:110
4351995117,6cyclictest9-21ksoftirqd/008:40:010
145332510,2sleep30-21swapper/310:45:143
138491510,0ptp4l391rcuc/307:10:373
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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