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2026-03-02 - 01:07
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sun Mar 01, 2026 12:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591233166,23phc2sys0-21swapper/307:09:573
111102202169,22sleep20-21swapper/207:09:542
108322201167,23sleep10-21swapper/107:06:221
108012199166,22sleep00-21swapper/007:05:580
2635921700,7sleep31141499cyclictest12:00:133
1615821390,6sleep01141199cyclictest08:25:010
1385918262,11phc2sys0-21swapper/307:10:003
260412620,2sleep30-21swapper/308:45:003
138491610,1ptp4l401ktimersoftd/307:30:153
138491570,1ptp4l401ktimersoftd/309:05:433
138491560,1ptp4l401ktimersoftd/310:15:133
95142530,4sleep29518-21irqrtprio12:30:172
242952520,3sleep324298-21irqrtprio09:45:183
138491520,0ptp4l401ktimersoftd/308:27:333
113752520,2sleep10-21swapper/111:30:101
11411994943,3cyclictest20669-21sh09:40:000
138491420,1ptp4l401ktimersoftd/308:09:193
138491410,20ptp4l4273-21sort08:00:143
138491410,0ptp4l401ktimersoftd/311:17:223
138491400,0ptp4l401ktimersoftd/310:45:253
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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