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2026-05-07 - 09:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Thu May 07, 2026 00:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
207222205170,23sleep30-21swapper/319:06:383
207242204170,22sleep00-21swapper/019:06:390
208752202167,23sleep20-21swapper/219:08:382
209062201167,23sleep10-21swapper/119:09:011
21278996228,4cyclictest41-21ksoftirqd/322:45:183
21278996228,4cyclictest41-21ksoftirqd/322:45:183
21278996028,7cyclictest41-21ksoftirqd/320:30:203
21278996028,7cyclictest41-21ksoftirqd/319:40:133
21278996027,7cyclictest41-21ksoftirqd/320:10:173
21278996026,7cyclictest41-21ksoftirqd/323:55:243
21278996026,7cyclictest41-21ksoftirqd/323:55:243
21278995931,4cyclictest41-21ksoftirqd/319:10:253
21278995926,7cyclictest41-21ksoftirqd/323:15:233
21278995925,4cyclictest41-21ksoftirqd/300:05:233
21278995828,4cyclictest41-21ksoftirqd/321:50:183
21278995828,4cyclictest41-21ksoftirqd/321:50:183
21278995822,4cyclictest41-21ksoftirqd/320:50:183
21278995726,7cyclictest41-21ksoftirqd/323:50:193
21278995627,4cyclictest41-21ksoftirqd/300:30:243
21278995624,4cyclictest41-21ksoftirqd/323:20:153
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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