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2026-08-06 - 16:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Thu Aug 06, 2026 12:45:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
307672204171,22sleep30-21swapper/307:06:593
308782201169,21sleep20-21swapper/207:08:272
307272199166,22sleep00-21swapper/007:06:280
287832199166,22sleep10-21swapper/107:05:041
1902921360,6sleep13130399cyclictest08:55:011
3130399680,25cyclictest30912-21latency_hist12:35:001
3130399671,25cyclictest26381-21date11:20:001
3130399660,25cyclictest8831-21latency_hist07:30:001
3130399660,25cyclictest13800-21date12:00:011
3130399660,23cyclictest7761-21cut10:40:181
3130399660,23cyclictest5060-21cut10:35:181
3130399651,24cyclictest1435-21latency_hist09:25:011
3130399650,32cyclictest16308-21date07:45:001
3130399650,24cyclictest22427-21cut11:10:191
3130399640,24cyclictest7694-21irqrtprio08:30:181
3130399640,24cyclictest29170-21date08:10:011
3130399631,21cyclictest23981-21latency_hist09:05:001
3130399630,24cyclictest563-21cat10:25:271
3130399630,24cyclictest12090-21sed07:35:131
3130399630,23cyclictest1485-21grep07:15:121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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