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2026-02-03 - 17:38
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Tue Feb 03, 2026 12:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
255952207172,23sleep10-21swapper/107:08:551
138591206172,23phc2sys0-21swapper/307:08:073
253662203170,22sleep20-21swapper/207:06:022
254572200166,22sleep00-21swapper/007:07:130
252162710,5sleep00-21swapper/011:30:170
18792630,2sleep20-21swapper/208:35:002
138491560,1ptp4l401ktimersoftd/311:15:133
232142530,3sleep023217-21proc_pri10:20:240
2597299461,9cyclictest25-21ksoftirqd/108:50:001
2597299461,9cyclictest25-21ksoftirqd/108:49:591
2597199460,9cyclictest9-21ksoftirqd/007:25:230
2597399445,9cyclictest33-21ksoftirqd/212:20:212
2597199440,7cyclictest9-21ksoftirqd/010:55:170
2597199430,6cyclictest9-21ksoftirqd/012:40:000
25973994223,9cyclictest33-21ksoftirqd/207:40:002
2597199422,38cyclictest19394-21latency_hist09:09:590
25974994124,15cyclictest41-21ksoftirqd/308:43:063
25973994028,10cyclictest33-21ksoftirqd/211:17:342
25973994024,5cyclictest33-21ksoftirqd/210:05:202
25973994023,5cyclictest33-21ksoftirqd/211:09:592
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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