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2026-02-06 - 19:35
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Fri Feb 06, 2026 12:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2096422460,8sleep233-21ksoftirqd/207:05:232
138591202168,23phc2sys0-21swapper/307:07:483
216382201168,22sleep10-21swapper/107:07:171
216422198165,22sleep00-21swapper/007:07:190
138491790,1ptp4l391rcuc/310:30:243
2214899638,19cyclictest25812-21needreboot09:25:233
2214899638,12cyclictest1070-21ystemctl11:48:173
2214899588,17cyclictest27120-21date11:40:013
30242570,2sleep03028-21irqrtprio07:35:190
2214899567,18cyclictest30062-21sed10:40:133
2214899567,18cyclictest30062-21sed10:40:133
99612550,2sleep20-21swapper/207:50:132
2214899558,11cyclictest7721-21sed09:55:153
2214899546,15cyclictest27109-21/usr/sbin/munin07:20:193
138491540,1ptp4l391rcuc/310:05:263
2214899506,15cyclictest6268-21switchtime11:55:253
2214899446,10cyclictest0-21swapper/309:45:263
138491440,1ptp4l391rcuc/310:45:213
138491440,0ptp4l401ktimersoftd/309:21:033
22148994338,3cyclictest11993-21cron10:05:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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