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2026-06-22 - 03:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Mon Jun 22, 2026 00:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591236169,23phc2sys0-21swapper/319:06:463
148092203168,23sleep00-21swapper/019:06:340
147612202169,21sleep20-21swapper/219:06:042
147652201167,23sleep10-21swapper/119:06:061
1606121610,5sleep11536599cyclictest00:35:181
1507328363,11sleep10-21swapper/119:10:001
187622620,5sleep318768-21irqrtprio19:15:183
15365996056,2cyclictest231rcuc/122:03:471
15365995956,2cyclictest231rcuc/122:31:271
15365995854,2cyclictest231rcuc/121:49:111
173182560,2sleep20-21swapper/220:17:242
138491550,1ptp4l401ktimersoftd/320:51:293
43132530,1sleep00-21swapper/022:00:240
1536599536,16cyclictest5796-21sed00:15:131
50798480,1rtkit-daemon506-21rtkit-daemon20:42:340
1536799483,42cyclictest12407-21grep23:25:013
1536799471,42cyclictest29833-21dump-pmu-power21:50:003
15365994717,3cyclictest25-21ksoftirqd/122:47:091
15365994717,3cyclictest25-21ksoftirqd/121:39:411
1536599471,43cyclictest5214-21dump-pmu-power19:55:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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