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2026-02-27 - 15:21
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Fri Feb 27, 2026 12:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
179702204169,23sleep30-21swapper/307:06:173
181522199166,22sleep00-21swapper/007:08:320
179632199165,23sleep10-21swapper/107:06:111
179642192159,22sleep20-21swapper/207:06:132
1419021560,7sleep21855999cyclictest09:10:152
1385918363,11phc2sys0-21swapper/307:10:003
1855999710,29cyclictest8092-21sshd07:50:302
18560996913,23cyclictest1008-21sed07:40:023
1855999699,22cyclictest31373-21expr10:50:132
18558996124,6cyclictest25-21ksoftirqd/109:10:191
18558995725,6cyclictest25-21ksoftirqd/111:50:231
18558995720,4cyclictest25-21ksoftirqd/107:10:201
18558995719,8cyclictest25-21ksoftirqd/109:25:011
18558995617,9cyclictest25-21ksoftirqd/108:00:151
18558995316,8cyclictest25-21ksoftirqd/111:35:191
18558995223,10cyclictest25-21ksoftirqd/108:40:001
18558995216,4cyclictest25-21ksoftirqd/108:17:461
18558995215,4cyclictest25-21ksoftirqd/111:00:041
18558995214,7cyclictest25-21ksoftirqd/107:53:511
18558995212,7cyclictest25-21ksoftirqd/112:02:061
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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