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2026-09-04 - 23:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Fri Sep 04, 2026 12:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
202142206167,21sleep10-21swapper/107:06:141
203552205170,23sleep30-21swapper/307:08:053
203822204171,22sleep00-21swapper/007:08:260
202052200167,22sleep20-21swapper/207:06:072
121972870,5sleep012196-21ptp4l-jitter09:00:220
2080799621,19cyclictest17093-21irqstats10:15:202
36272550,2sleep30-21swapper/312:00:133
2080799550,21cyclictest24663-21awk09:25:232
138491550,1ptp4l401ktimersoftd/308:13:363
138491540,1ptp4l401ktimersoftd/311:27:013
118382520,2sleep00-21swapper/012:15:180
138491510,1ptp4l401ktimersoftd/310:39:303
166662490,2sleep30-21swapper/311:20:183
20808994843,3cyclictest13272-21cron11:15:003
138491440,0ptp4l401ktimersoftd/310:08:383
20808994325,16cyclictest32742-21cron09:45:013
20805994338,3cyclictest17961-21turbostat.cron12:30:000
20805994328,13cyclictest9-21ksoftirqd/011:25:010
138491430,0ptp4l401ktimersoftd/312:25:503
138491430,0ptp4l401ktimersoftd/311:15:163
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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