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2026-09-06 - 15:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sun Sep 06, 2026 12:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
61022204170,22sleep00-21swapper/007:06:070
138591204171,22phc2sys0-21swapper/307:08:333
60532202170,21sleep20-21swapper/207:05:302
62032201168,22sleep10-21swapper/107:07:251
138591135110,14phc2sys0-21swapper/307:10:003
138491720,1ptp4l401ktimersoftd/310:25:233
135191610,5getstats670699cyclictest10:13:203
138491580,1ptp4l391rcuc/308:00:263
138491560,1ptp4l401ktimersoftd/308:27:263
40662550,7sleep1241ktimersoftd/111:25:121
226052540,5sleep222609-21irqrtprio07:40:192
138491510,1ptp4l401ktimersoftd/312:38:443
75792500,2sleep30-21swapper/308:15:183
6703994942,4cyclictest28333-21sh12:15:010
6704994841,4cyclictest16049-21cat11:49:591
138491440,0ptp4l401ktimersoftd/311:22:383
138491430,0ptp4l401ktimersoftd/310:55:083
138491420,0ptp4l401ktimersoftd/312:15:183
138491410,0ptp4l401ktimersoftd/311:26:483
138491410,0ptp4l401ktimersoftd/310:31:313
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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