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2026-07-01 - 19:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Wed Jul 01, 2026 12:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591207172,23phc2sys0-21swapper/307:06:363
307992205170,23sleep00-21swapper/007:08:150
287202202169,22sleep10-21swapper/107:05:101
306242201168,21sleep20-21swapper/207:06:042
1392021440,2sleep30-21swapper/309:50:013
1385918262,10phc2sys0-21swapper/307:10:013
287852630,3sleep028789-21cpuspeed_turbos12:30:130
31369995828,10cyclictest9-21ksoftirqd/010:25:270
3136999525,10cyclictest9-21ksoftirqd/009:40:240
31369995219,4cyclictest9-21ksoftirqd/010:12:060
3136999507,5cyclictest9-21ksoftirqd/009:55:240
3136999505,9cyclictest9-21ksoftirqd/012:15:150
3136999493,6cyclictest9-21ksoftirqd/011:45:210
3136999492,6cyclictest9-21ksoftirqd/008:25:000
3136999492,5cyclictest9-21ksoftirqd/011:20:180
3136999491,6cyclictest9-21ksoftirqd/012:25:120
3136999491,6cyclictest9-21ksoftirqd/011:15:180
3136999491,5cyclictest9-21ksoftirqd/012:05:130
134991490,4getstats3137299cyclictest08:00:003
3136999484,7cyclictest9-21ksoftirqd/010:40:170
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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