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2026-08-19 - 23:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Wed Aug 19, 2026 12:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591212167,33phc2sys0-21swapper/307:06:213
217642202169,22sleep00-21swapper/007:06:080
220382201168,22sleep20-21swapper/207:09:352
217602201167,22sleep10-21swapper/107:06:061
3112321660,7sleep02236499cyclictest10:40:220
138491690,1ptp4l401ktimersoftd/312:35:233
138491680,1ptp4l401ktimersoftd/311:43:523
22365996331,3cyclictest25-21ksoftirqd/110:15:001
22366996224,4cyclictest33-21ksoftirqd/210:15:182
22366996127,6cyclictest33-21ksoftirqd/208:30:232
22366996123,8cyclictest33-21ksoftirqd/207:40:242
22366996029,12cyclictest33-21ksoftirqd/212:15:272
22366996028,5cyclictest33-21ksoftirqd/207:50:002
22366996025,10cyclictest33-21ksoftirqd/211:55:142
22366995930,6cyclictest33-21ksoftirqd/209:45:232
22366995928,5cyclictest33-21ksoftirqd/209:40:262
22366995921,4cyclictest33-21ksoftirqd/210:20:182
22366995921,4cyclictest33-21ksoftirqd/210:20:182
22365995925,8cyclictest25-21ksoftirqd/107:35:001
22366995830,4cyclictest33-21ksoftirqd/210:10:222
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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