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2026-08-31 - 18:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Mon Aug 31, 2026 12:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591206171,23phc2sys0-21swapper/307:07:363
108672204171,22sleep10-21swapper/107:06:171
110972203168,23sleep00-21swapper/007:09:170
110742201169,21sleep20-21swapper/207:08:592
988421570,7sleep01145399cyclictest08:10:190
138491680,1ptp4l401ktimersoftd/309:20:153
249592560,1sleep30-21swapper/311:55:193
138491560,1ptp4l401ktimersoftd/310:41:223
213872550,3sleep20-21swapper/211:50:012
106882530,2sleep10-21swapper/109:15:261
105072500,2sleep00-21swapper/009:15:260
138491480,40ptp4l0-21swapper/307:10:013
11454994615,29cyclictest8400-21kworker/1:207:15:441
138491450,0ptp4l401ktimersoftd/312:30:163
11454994531,12cyclictest25-21ksoftirqd/109:31:511
11454994531,12cyclictest25-21ksoftirqd/109:31:511
138491440,0ptp4l401ktimersoftd/308:13:163
138491430,1ptp4l401ktimersoftd/311:05:033
138491430,0ptp4l401ktimersoftd/310:05:163
11456994324,16cyclictest6373-21cron12:25:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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