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2025-11-20 - 00:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Wed Nov 19, 2025 12:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11062204169,23sleep30-21swapper/307:07:473
11062204169,23sleep30-21swapper/307:07:463
9442203170,22sleep20-21swapper/207:05:522
9442203170,22sleep20-21swapper/207:05:522
10602203169,23sleep00-21swapper/007:07:110
10602203169,23sleep00-21swapper/007:07:110
314162201167,22sleep10-21swapper/107:05:031
314162201167,22sleep10-21swapper/107:05:031
4272911350,1ptp4l1226-21dump-pmu-power12:30:013
129928161,11sleep00-21swapper/007:10:000
427291610,1ptp4l401ktimersoftd/312:03:323
427291600,1ptp4l401ktimersoftd/311:25:413
307042600,3sleep10-21swapper/110:15:151
427291590,1ptp4l401ktimersoftd/308:28:003
427291580,1ptp4l401ktimersoftd/311:35:183
427291580,0ptp4l401ktimersoftd/312:07:393
189832580,7sleep2164999cyclictest12:00:152
427291540,1ptp4l401ktimersoftd/308:58:583
201332530,2sleep10-21swapper/112:00:261
1650995333,18cyclictest41-21ksoftirqd/310:13:193
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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