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2026-07-23 - 19:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Thu Jul 23, 2026 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591230162,23phc2sys0-21swapper/307:08:103
19662201167,22sleep20-21swapper/207:05:492
21472199165,23sleep10-21swapper/107:08:081
21162197165,22sleep00-21swapper/007:07:430
264299730,31cyclictest7332-21latency_hist08:25:013
264299680,22cyclictest635-21cut12:30:163
264299680,20cyclictest13428-21cut10:45:183
264299670,23cyclictest5528-21awk11:35:183
264299670,22cyclictest8055-21perl09:30:163
264299670,22cyclictest29565-21latency_hist11:20:013
264299661,22cyclictest10547-21sed07:25:143
264299661,22cyclictest10547-21sed07:25:143
264299660,23cyclictest31383-21timerandwakeup09:10:263
264299651,21cyclictest22367-21cstates12:10:153
264299650,23cyclictest17989-21cut10:55:153
264299640,29cyclictest20683-21cat12:05:203
264299640,26cyclictest11837-21grep08:30:273
264299640,24cyclictest16530-21sed10:50:243
264299640,21cyclictest14847-21date08:40:003
264299631,23cyclictest30932-21missed_timers11:20:213
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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