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2026-04-20 - 06:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Mon Apr 20, 2026 00:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
180232225197,18sleep10-21swapper/119:09:591
177662205170,23sleep00-21swapper/019:06:400
178502204171,22sleep20-21swapper/219:07:472
178512202167,23sleep30-21swapper/319:07:483
1478121720,5sleep01831799cyclictest23:20:210
699521270,6sleep21831999cyclictest00:10:172
1802528262,11sleep30-21swapper/319:10:013
1831999750,2cyclictest6292chrt21:48:292
138491650,1ptp4l401ktimersoftd/321:16:053
1831799578,10cyclictest18795-21sed19:10:140
1831999561,3cyclictest0-21swapper/220:01:172
138491550,1ptp4l401ktimersoftd/300:28:593
266612540,4sleep09-21ksoftirqd/020:30:200
18318994640,3cyclictest30740-21dump-pmu-power21:45:011
1831799454,8cyclictest22383-21sed22:30:260
50798440,2rtkit-daemon0-21swapper/122:45:061
18317994321,8cyclictest9-21ksoftirqd/019:44:500
138491430,1ptp4l401ktimersoftd/322:17:363
18320994136,2cyclictest41-21ksoftirqd/322:40:003
18317994121,9cyclictest9-21ksoftirqd/022:03:050
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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