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2025-12-18 - 12:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Thu Dec 18, 2025 00:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
156142205171,22sleep20-21swapper/219:07:312
155812204171,22sleep10-21swapper/119:07:071
138591204170,23phc2sys0-21swapper/319:07:003
155802195161,22sleep00-21swapper/019:07:050
1385918262,11phc2sys0-21swapper/319:10:013
224492720,10sleep11609699cyclictest22:35:261
219112670,5sleep01609599cyclictest23:40:200
79472610,3sleep20-21swapper/221:00:282
138491580,1ptp4l401ktimersoftd/320:15:253
138491570,1ptp4l401ktimersoftd/300:38:253
138491550,1ptp4l401ktimersoftd/321:15:473
84732510,1sleep10-21swapper/123:15:141
77222500,2sleep20-21swapper/222:05:262
258892490,2sleep00-21swapper/023:50:110
134991460,7getstats1609899cyclictest22:00:193
10002450,3sleep00-21swapper/019:45:000
16097994430,12cyclictest33-21ksoftirqd/222:40:102
16098994227,12cyclictest41-21ksoftirqd/321:40:003
16098994129,9cyclictest41-21ksoftirqd/319:15:123
16098994034,3cyclictest41-21ksoftirqd/319:35:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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