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2026-08-17 - 09:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Mon Aug 17, 2026 00:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591212150,50phc2sys0-21swapper/319:09:443
289132204172,21sleep10-21swapper/119:09:051
289142202170,21sleep20-21swapper/219:09:052
286942201166,23sleep00-21swapper/019:06:140
2172821460,2sleep10-21swapper/122:10:121
1234221380,3sleep12927999cyclictest21:50:191
2928199701,11cyclictest15789-21apache200:07:093
239682690,4sleep10-21swapper/100:25:121
2928099654,23cyclictest12043-21fschecks_count22:55:172
2928099651,29cyclictest26048-21users21:10:292
2928099651,29cyclictest26048-21users21:10:282
2928099651,24cyclictest19182-21cut00:15:132
2928099641,24cyclictest8911-21cron21:45:012
2928099641,24cyclictest8911-21cron21:45:002
2928099640,30cyclictest15482-21mailstats23:00:262
2928099630,27cyclictest2942-21cut20:25:202
2928099621,23cyclictest17132-21expr20:55:152
2928099620,24cyclictest19108-21sort22:05:132
2928099610,23cyclictest11061-21awk19:35:252
2928099600,26cyclictest6011-21vmstat22:40:272
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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