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2026-11-01 - 02:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sat Oct 31, 2026 12:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
69752204169,23sleep00-21swapper/007:09:260
69012204170,23sleep30-21swapper/307:08:283
67402201168,22sleep20-21swapper/207:06:232
68072199167,21sleep10-21swapper/107:07:131
70242162122,14sleep30-21swapper/307:10:013
70242162122,14sleep30-21swapper/307:10:013
2968821440,5sleep0731799cyclictest08:57:520
74932760,5sleep27496-21latency_hist10:25:012
102472750,2sleep20-21swapper/211:35:132
7319996128,9cyclictest33-21ksoftirqd/211:00:012
7319996128,10cyclictest33-21ksoftirqd/212:35:192
7319996118,4cyclictest33-21ksoftirqd/207:35:252
7319995927,10cyclictest33-21ksoftirqd/208:05:252
7319995830,3cyclictest33-21ksoftirqd/207:25:162
7319995828,4cyclictest33-21ksoftirqd/211:45:222
251782570,1sleep10-21swapper/112:05:131
7319995628,3cyclictest33-21ksoftirqd/209:55:262
731999555,9cyclictest25079-1kworker/2:1H11:05:002
731999552,10cyclictest33-21ksoftirqd/210:05:252
217452550,2sleep30-21swapper/310:50:253
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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