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2026-06-30 - 17:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Tue Jun 30, 2026 12:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
249962226162,21sleep20-21swapper/207:07:432
251592205171,22sleep30-21swapper/307:09:453
249232204170,22sleep10-21swapper/107:06:451
248642201167,23sleep00-21swapper/007:06:010
1385918561,15phc2sys0-21swapper/307:10:013
138491620,0ptp4l401ktimersoftd/310:17:413
159102600,2sleep20-21swapper/207:55:132
191282570,3sleep2321ktimersoftd/209:05:212
31702550,2sleep20-21swapper/207:30:022
138491530,1ptp4l401ktimersoftd/308:46:593
107742500,2sleep20-21swapper/209:55:152
263132490,4sleep326320-21irqrtprio09:20:183
25475994943,4cyclictest30156-21dump-pmu-power11:40:003
90472480,3sleep00-21swapper/009:50:200
25475994639,4cyclictest3614-21fschecks_count09:40:163
228932430,2sleep2311rcuc/212:30:012
138491430,1ptp4l401ktimersoftd/310:14:183
138491430,0ptp4l401ktimersoftd/309:47:033
138491430,0ptp4l401ktimersoftd/308:55:213
25475994212,4cyclictest41-21ksoftirqd/308:50:223
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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