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2026-04-21 - 19:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Tue Apr 21, 2026 12:46:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
211542231164,23sleep30-21swapper/307:09:133
211542231164,23sleep30-21swapper/307:09:123
209962203170,22sleep10-21swapper/107:07:111
209962203170,22sleep10-21swapper/107:07:101
211042201167,22sleep00-21swapper/007:08:330
211042201167,22sleep00-21swapper/007:08:330
210542200166,23sleep20-21swapper/207:07:552
210542200166,23sleep20-21swapper/207:07:552
1845021390,6sleep32151799cyclictest09:10:283
50798940,76rtkit-daemon0-21swapper/007:10:000
2151599670,23cyclictest7232-21sed08:50:141
2151599660,23cyclictest26411-21sed09:30:001
2151599640,22cyclictest5485-21tr10:55:261
138491600,1ptp4l401ktimersoftd/311:44:013
138491590,1ptp4l401ktimersoftd/311:45:203
2151599571,23cyclictest15609-21mailstats10:10:231
2151599571,23cyclictest15609-21mailstats10:10:231
138491560,1ptp4l401ktimersoftd/310:48:003
320372550,2sleep10-21swapper/111:50:201
320372550,2sleep10-21swapper/111:50:201
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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