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2026-08-24 - 22:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Mon Aug 24, 2026 12:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591214167,36phc2sys0-21swapper/307:05:583
52892207173,22sleep10-21swapper/107:05:041
73822204172,21sleep20-21swapper/207:07:432
72152200167,21sleep00-21swapper/007:05:320
756628561,16sleep30-21swapper/307:10:013
317842620,7sleep2786099cyclictest09:00:202
317842620,7sleep2786099cyclictest09:00:192
106182570,5sleep310623-21cpuspeed_turbos08:20:133
252812540,2sleep30-21swapper/309:50:273
42962530,6sleep0785899cyclictest11:20:180
138491530,1ptp4l391rcuc/308:25:473
135191530,3getstats0-21swapper/311:30:113
62582520,2sleep16264-21irqrtprio08:10:191
135191510,7getstats786199cyclictest12:10:113
324442480,3sleep20-21swapper/211:10:252
134991470,6getstats786199cyclictest08:05:473
785899463,40cyclictest3198-21dump-pmu-power09:10:000
50798450,9rtkit-daemon0-21swapper/011:33:560
7861994338,3cyclictest41-21ksoftirqd/310:00:013
7861994338,3cyclictest41-21ksoftirqd/310:00:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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