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2026-04-28 - 22:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Tue Apr 28, 2026 12:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
268842203169,22sleep00-21swapper/007:09:060
264032203169,22sleep30-21swapper/307:06:203
268012202168,22sleep20-21swapper/207:08:082
268302201168,22sleep10-21swapper/107:08:311
27437996325,7cyclictest25-21ksoftirqd/109:20:231
27436996322,4cyclictest9-21ksoftirqd/007:58:420
27439996231,9cyclictest33-21ksoftirqd/211:10:132
27439996231,4cyclictest33-21ksoftirqd/207:10:182
27439996230,5cyclictest33-21ksoftirqd/209:50:012
27439996125,8cyclictest33-21ksoftirqd/209:35:192
27437996126,6cyclictest25-21ksoftirqd/110:05:171
27436996124,4cyclictest9-21ksoftirqd/009:55:200
27439996028,9cyclictest33-21ksoftirqd/207:35:132
27439996028,6cyclictest33-21ksoftirqd/208:35:182
27439996026,6cyclictest33-21ksoftirqd/209:50:132
27439996025,4cyclictest33-21ksoftirqd/207:55:132
27439996022,6cyclictest33-21ksoftirqd/207:15:202
27437996012,5cyclictest25-21ksoftirqd/110:55:001
27439995932,6cyclictest33-21ksoftirqd/209:05:152
27439995928,9cyclictest33-21ksoftirqd/209:20:182
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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