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2026-04-29 - 11:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Wed Apr 29, 2026 00:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
205182205172,21sleep20-21swapper/219:07:482
138591205171,22phc2sys0-21swapper/319:06:553
205462202169,21sleep00-21swapper/019:08:100
203412201168,22sleep10-21swapper/119:05:301
107621500,6sleep12098099cyclictest22:45:141
1450121450,6sleep02097999cyclictest22:05:240
20981999137,10cyclictest33-21ksoftirqd/219:20:302
1385918463,12phc2sys0-21swapper/319:10:003
20981997537,4cyclictest33-21ksoftirqd/219:20:012
20981997136,2cyclictest33-21ksoftirqd/222:55:132
138491710,1ptp4l401ktimersoftd/320:47:433
20981996231,4cyclictest33-21ksoftirqd/220:39:592
20981996228,4cyclictest33-21ksoftirqd/200:40:002
20981996131,4cyclictest33-21ksoftirqd/219:30:262
138491600,1ptp4l401ktimersoftd/322:27:403
20981995930,5cyclictest33-21ksoftirqd/223:40:242
138491580,1ptp4l401ktimersoftd/322:48:463
20981995731,7cyclictest33-21ksoftirqd/200:00:272
20981995729,7cyclictest33-21ksoftirqd/221:30:012
20981995726,5cyclictest33-21ksoftirqd/200:15:192
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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