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2026-03-09 - 22:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Mon Mar 09, 2026 12:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591211167,33phc2sys0-21swapper/307:05:043
267532205171,22sleep00-21swapper/007:09:400
267492203169,22sleep10-21swapper/107:09:371
265812203169,23sleep20-21swapper/207:07:252
325921500,5sleep02707399cyclictest07:25:190
325921500,5sleep02707399cyclictest07:25:190
2678229662,10sleep10-21swapper/107:10:021
138491760,0ptp4l391rcuc/310:10:203
78572660,2sleep10-21swapper/107:35:151
253242660,3sleep02707399cyclictest09:15:150
27076996428,7cyclictest41-21ksoftirqd/309:05:003
27076996328,7cyclictest41-21ksoftirqd/312:00:143
27076996328,10cyclictest41-21ksoftirqd/312:15:003
27076996226,7cyclictest41-21ksoftirqd/307:55:123
27076996226,7cyclictest41-21ksoftirqd/307:55:123
27076996223,8cyclictest41-21ksoftirqd/311:35:003
27076996127,4cyclictest41-21ksoftirqd/307:30:183
27076996125,4cyclictest41-21ksoftirqd/310:10:013
27076996121,7cyclictest41-21ksoftirqd/308:05:203
27076996030,4cyclictest41-21ksoftirqd/309:30:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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