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2026-08-11 - 10:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Tue Aug 11, 2026 00:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
5032207174,22sleep10-21swapper/119:07:171
138591207173,23phc2sys0-21swapper/319:05:033
3912204171,22sleep00-21swapper/019:06:060
4992201169,21sleep20-21swapper/219:07:132
1141421760,4sleep2103299cyclictest19:30:162
1179221720,6sleep0103099cyclictest21:40:160
15622640,1sleep10-21swapper/122:25:141
138652600,3sleep113867-21df_abs19:35:121
103212600,1sleep20-21swapper/220:30:252
138491580,1ptp4l401ktimersoftd/323:46:273
244882560,1sleep00-21swapper/022:05:190
138491560,1ptp4l401ktimersoftd/323:15:423
214502550,4sleep2321ktimersoftd/219:50:132
74942510,2sleep20-21swapper/219:20:252
138491440,0ptp4l401ktimersoftd/321:34:583
138491440,0ptp4l401ktimersoftd/300:10:173
138491430,0ptp4l401ktimersoftd/322:40:333
1032994338,3cyclictest33-21ksoftirqd/200:40:002
50798400,8rtkit-daemon0-21swapper/020:48:580
50798390,6rtkit-daemon0-21swapper/123:44:291
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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