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2026-09-03 - 22:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Thu Sep 03, 2026 12:45:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
59482204171,22sleep10-21swapper/107:06:551
138591203170,22phc2sys0-21swapper/307:09:383
59772199166,21sleep00-21swapper/007:07:180
59492199167,22sleep20-21swapper/207:06:562
30662510,2sleep30-21swapper/310:15:203
619225035,8sleep10-21swapper/107:10:001
6635994729,16cyclictest41-21ksoftirqd/311:00:013
6632994640,3cyclictest1303-21runrttasks09:54:070
138491450,24ptp4l663599cyclictest07:35:153
6632994436,4cyclictest16923-21cron11:50:010
138491430,0ptp4l401ktimersoftd/308:40:193
138491430,0ptp4l401ktimersoftd/307:14:083
6632994237,3cyclictest9-21ksoftirqd/008:37:560
138491420,0ptp4l401ktimersoftd/311:27:013
138491420,0ptp4l401ktimersoftd/308:19:243
663499411,37cyclictest24254-21dump-pmu-power09:55:002
6634993933,4cyclictest33-21ksoftirqd/207:12:352
6632993934,3cyclictest9-21ksoftirqd/012:30:000
663599381,34cyclictest31577-21latency_hist08:00:003
6634993819,17cyclictest33-21ksoftirqd/210:06:202
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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