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2026-07-17 - 19:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Fri Jul 17, 2026 12:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
224762232165,22sleep00-21swapper/007:07:030
138591204170,22phc2sys0-21swapper/307:08:433
223902203170,22sleep10-21swapper/107:05:551
204882202167,23sleep20-21swapper/207:05:042
1885521380,5sleep12300699cyclictest12:25:201
23006996725,7cyclictest25-21ksoftirqd/109:15:001
23006996633,3cyclictest25-21ksoftirqd/110:29:591
138491660,1ptp4l401ktimersoftd/312:21:373
23006996329,4cyclictest25-21ksoftirqd/108:10:141
23005996232,3cyclictest9-21ksoftirqd/008:45:130
138491610,1ptp4l401ktimersoftd/308:20:073
23006996030,4cyclictest25-21ksoftirqd/107:50:201
23006996029,4cyclictest25-21ksoftirqd/109:50:011
23006996029,4cyclictest25-21ksoftirqd/108:45:181
23005996031,3cyclictest9-21ksoftirqd/010:25:140
23005996030,3cyclictest9-21ksoftirqd/008:50:150
23005996027,4cyclictest9-21ksoftirqd/010:15:210
23006995931,3cyclictest25-21ksoftirqd/109:25:211
23006995927,7cyclictest25-21ksoftirqd/111:15:261
23006995927,4cyclictest25-21ksoftirqd/109:15:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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