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2025-11-20 - 13:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Thu Nov 20, 2025 00:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
242702210128,72sleep10-21swapper/119:05:141
427791197162,23phc2sys0-21swapper/319:09:593
264632186153,22sleep20-21swapper/219:09:452
264162182115,22sleep00-21swapper/019:09:060
657221800,5sleep22677999cyclictest22:15:142
1781821630,2sleep22677999cyclictest21:30:252
115512950,2sleep10-21swapper/122:25:121
427291630,1ptp4l401ktimersoftd/320:57:513
427591550,4getstats19827-21cat22:40:223
427291550,1ptp4l401ktimersoftd/320:20:253
298742540,2sleep229875-21kernelversion23:00:192
26778995321,3cyclictest25-21ksoftirqd/121:58:381
427591520,6getstats2678099cyclictest00:35:243
427291520,1ptp4l401ktimersoftd/320:35:103
26778995221,7cyclictest25-21ksoftirqd/123:26:241
26778994841,4cyclictest704-21cron21:00:011
427591440,5getstats5703-21ptp4l-jitter00:20:223
427591440,1getstats0-21swapper/319:35:213
26779994440,2cyclictest987-21cron19:55:002
2677999442,40cyclictest0-21swapper/200:00:282
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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