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2026-03-06 - 02:24
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Thu Mar 05, 2026 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
311972230167,51sleep30-21swapper/307:09:123
310492201169,21sleep20-21swapper/207:07:182
311952200167,22sleep10-21swapper/107:09:101
309362199168,21sleep00-21swapper/007:05:510
1814921360,2sleep00-21swapper/009:55:240
138491620,1ptp4l401ktimersoftd/309:30:523
138491600,1ptp4l401ktimersoftd/312:30:193
138491600,1ptp4l401ktimersoftd/312:30:193
29922590,3sleep3391rcuc/308:20:203
138491570,1ptp4l401ktimersoftd/310:29:373
180962550,1sleep10-21swapper/107:45:191
138491500,1ptp4l401ktimersoftd/307:56:273
3126024735,6sleep30-21swapper/307:10:013
3155299430,3cyclictest121rcu_preempt11:10:180
138491430,0ptp4l401ktimersoftd/308:34:553
138491430,0ptp4l401ktimersoftd/307:20:483
3155299420,3cyclictest121rcu_preempt12:25:180
31554994135,3cyclictest33-21ksoftirqd/208:50:002
31554994130,9cyclictest33-21ksoftirqd/208:00:252
31554994018,14cyclictest33-21ksoftirqd/211:10:182
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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