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2026-08-06 - 04:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Thu Aug 06, 2026 00:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591222154,23phc2sys0-21swapper/319:06:053
19952205173,21sleep20-21swapper/219:06:002
19942205171,23sleep10-21swapper/119:06:001
19682201167,22sleep00-21swapper/019:05:370
1037821770,6sleep0264299cyclictest23:45:150
2899721220,6sleep0264299cyclictest23:18:270
138491660,1ptp4l401ktimersoftd/321:15:113
241742630,2sleep20-21swapper/219:50:282
253182590,5sleep2321ktimersoftd/219:55:142
264499564,7cyclictest31502-21unixbench_multi00:25:252
2642995625,4cyclictest9-21ksoftirqd/021:05:250
264499543,6cyclictest27017-21idleruntime-cro00:20:012
2642995423,5cyclictest9-21ksoftirqd/023:55:170
2642995423,4cyclictest9-21ksoftirqd/019:50:150
2642995419,4cyclictest9-21ksoftirqd/000:30:000
138491540,1ptp4l401ktimersoftd/319:14:283
2642995323,4cyclictest9-21ksoftirqd/020:14:340
2642995318,3cyclictest9-21ksoftirqd/019:40:270
2642995314,9cyclictest9-21ksoftirqd/022:20:140
264499523,7cyclictest27387-21cpuspeed_turbos22:10:132
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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