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2026-07-26 - 08:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sun Jul 26, 2026 00:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
69302235169,23sleep30-21swapper/319:08:043
69282202168,22sleep10-21swapper/119:08:011
68112202169,22sleep20-21swapper/219:06:342
70092200167,22sleep00-21swapper/019:09:050
708128261,12sleep30-21swapper/319:10:013
7377996223,4cyclictest41-21ksoftirqd/321:11:543
7377996124,10cyclictest41-21ksoftirqd/319:57:083
7377996027,6cyclictest41-21ksoftirqd/323:40:163
7377996023,7cyclictest41-21ksoftirqd/322:50:153
7377996023,7cyclictest41-21ksoftirqd/322:50:153
7377996022,8cyclictest41-21ksoftirqd/320:38:403
7377996022,4cyclictest41-21ksoftirqd/323:54:143
7377996021,8cyclictest41-21ksoftirqd/323:12:203
7377996021,10cyclictest41-21ksoftirqd/321:08:173
7377995927,9cyclictest41-21ksoftirqd/323:05:013
7377995925,7cyclictest41-21ksoftirqd/320:40:173
7377995922,8cyclictest41-21ksoftirqd/319:40:363
7377995922,4cyclictest41-21ksoftirqd/320:26:293
7377995919,8cyclictest41-21ksoftirqd/322:24:473
7377995919,8cyclictest41-21ksoftirqd/322:24:473
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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