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2026-04-26 - 22:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sun Apr 26, 2026 12:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
310942203170,22sleep20-21swapper/207:06:222
311552202170,22sleep10-21swapper/107:07:091
311452202169,22sleep30-21swapper/307:07:033
312312199166,22sleep00-21swapper/007:08:090
2555821620,2sleep00-21swapper/012:20:260
211112660,2sleep10-21swapper/108:55:251
138491630,8ptp4l401ktimersoftd/309:18:313
87722590,1sleep20-21swapper/208:30:262
3167699585,6cyclictest4075-21sort07:20:012
138491580,1ptp4l401ktimersoftd/312:02:523
3167699541,9cyclictest9754-21tune2fs10:45:162
138491540,1ptp4l401ktimersoftd/310:52:153
3167699521,9cyclictest9492-21/usr/sbin/munin09:40:192
3167699520,10cyclictest4624-21cstates10:35:142
3138125234,11sleep30-21swapper/307:10:013
3167699510,17cyclictest20820-21systemctl10:00:242
3167699510,11cyclictest22166-21irqrtprio12:15:192
3167699510,10cyclictest26894-21cat09:10:002
3167699501,9cyclictest15228-21fschecks_count08:45:162
3167699500,9cyclictest30884-21sed11:25:272
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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