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2026-07-12 - 22:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sun Jul 12, 2026 12:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
533423080,53sleep10-21swapper/107:05:301
138591224163,50phc2sys0-21swapper/307:05:443
56742204171,22sleep20-21swapper/207:07:152
58412203170,22sleep00-21swapper/007:09:190
138591163126,13phc2sys0-21swapper/307:10:023
617021470,6sleep0618799cyclictest11:30:140
1156821470,5sleep3619099cyclictest09:30:143
218242840,3sleep321830-21irqrtprio10:55:193
238372770,2sleep10-21swapper/112:05:171
6189996526,9cyclictest33-21ksoftirqd/207:40:202
6187996429,4cyclictest9-21ksoftirqd/008:20:010
6190996227,4cyclictest41-21ksoftirqd/310:10:253
6190996227,4cyclictest41-21ksoftirqd/310:10:253
6190996129,7cyclictest41-21ksoftirqd/311:25:213
6190996025,10cyclictest41-21ksoftirqd/311:50:273
6190996025,10cyclictest41-21ksoftirqd/311:50:273
6187996025,3cyclictest9-21ksoftirqd/012:20:140
6187996023,5cyclictest9-21ksoftirqd/010:45:140
6187996020,6cyclictest9-21ksoftirqd/008:55:240
6187996019,6cyclictest9-21ksoftirqd/011:15:130
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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