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2026-08-08 - 17:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sat Aug 08, 2026 12:45:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
204542209175,23sleep30-21swapper/307:09:273
204022204171,22sleep10-21swapper/107:08:441
202052200168,21sleep20-21swapper/207:06:122
180842200167,22sleep00-21swapper/007:05:020
1385918262,10phc2sys0-21swapper/307:10:013
121682600,5sleep212171-21phc2sys11:10:232
20796995820,5cyclictest25-21ksoftirqd/110:25:001
49442520,2sleep20-21swapper/210:55:262
267972510,3sleep226801-21irqrtprio10:35:212
20796995116,4cyclictest25-21ksoftirqd/111:35:001
20796995012,7cyclictest25-21ksoftirqd/108:50:001
20796994818,3cyclictest25-21ksoftirqd/107:45:201
20796994812,3cyclictest25-21ksoftirqd/108:20:141
149462480,2sleep20-21swapper/208:00:232
40372470,2sleep00-21swapper/009:50:130
20796994516,4cyclictest25-21ksoftirqd/109:20:231
20796994514,4cyclictest25-21ksoftirqd/109:29:591
20796994415,4cyclictest25-21ksoftirqd/108:25:251
20796994413,8cyclictest25-21ksoftirqd/108:30:271
20796994413,5cyclictest25-21ksoftirqd/110:45:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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