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2026-03-22 - 01:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sat Mar 21, 2026 12:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591198164,23phc2sys0-21swapper/307:06:153
318322193160,22sleep20-21swapper/207:06:532
318782192159,22sleep10-21swapper/107:07:291
319192174112,49sleep00-21swapper/007:08:000
278962750,2sleep30-21swapper/311:20:153
3236999671,24cyclictest15695-21ls08:45:213
3236999660,22cyclictest24438-21awk09:04:593
3236999650,26cyclictest2178-21gpgv12:40:013
3236999650,23cyclictest20379-21sed12:10:143
3236999640,25cyclictest451-21expr10:25:143
3236999630,25cyclictest21562-21mailstats10:00:253
3236999630,24cyclictest29436-21ls09:15:013
278192620,2sleep10-21swapper/108:05:171
3236999610,23cyclictest6796-21sed10:35:243
3236999610,21cyclictest0-21swapper/309:25:283
157672610,2sleep20-21swapper/207:40:192
3236999551,23cyclictest32198-21date12:35:013
3236999550,23cyclictest29746-21date12:30:003
25162550,2sleep10-21swapper/108:20:131
138491550,1ptp4l391rcuc/310:15:293
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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