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2026-02-20 - 01:46
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Thu Feb 19, 2026 12:46:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1902122050,8sleep20-21swapper/207:10:012
138591203170,22phc2sys0-21swapper/307:09:123
187172202169,22sleep10-21swapper/107:08:361
187462199168,20sleep00-21swapper/007:09:000
2922721200,3sleep00-21swapper/007:30:120
138491660,0ptp4l401ktimersoftd/307:47:263
138491660,0ptp4l401ktimersoftd/307:47:263
19117995919,4cyclictest25-21ksoftirqd/112:20:151
19116995828,3cyclictest9-21ksoftirqd/007:40:000
19116995724,3cyclictest9-21ksoftirqd/012:20:140
19117995526,3cyclictest25-21ksoftirqd/108:15:131
19117995526,3cyclictest25-21ksoftirqd/108:15:131
254722540,4sleep125471-21timerandwakeup09:30:241
19117995420,6cyclictest25-21ksoftirqd/109:05:271
19116995423,3cyclictest9-21ksoftirqd/007:55:210
19117995322,4cyclictest25-21ksoftirqd/110:00:211
19116995320,3cyclictest9-21ksoftirqd/009:55:170
138491530,1ptp4l401ktimersoftd/310:40:173
19116995225,3cyclictest9-21ksoftirqd/010:55:120
19116995223,3cyclictest9-21ksoftirqd/011:50:160
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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