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2026-06-29 - 16:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Mon Jun 29, 2026 12:46:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591205171,23phc2sys0-21swapper/307:08:383
283782204169,23sleep00-21swapper/007:06:470
283422204169,23sleep10-21swapper/107:06:191
284302201168,22sleep20-21swapper/207:07:292
262052600,6sleep02892099cyclictest10:20:140
22932600,5sleep22892299cyclictest09:30:232
97592560,4sleep20-21swapper/209:45:182
97592560,4sleep20-21swapper/209:45:182
251492550,5sleep09-21ksoftirqd/011:20:400
117992550,3sleep211803-21cpuspeed_turbos07:40:132
28923995424,7cyclictest41-21ksoftirqd/311:15:013
28923995326,9cyclictest41-21ksoftirqd/311:35:003
28923995226,9cyclictest41-21ksoftirqd/309:00:183
2892399511,6cyclictest15785-21timerwakeupswit07:45:243
28923995020,3cyclictest41-21ksoftirqd/309:43:133
2892399482,6cyclictest401ktimersoftd/310:15:003
2892399472,5cyclictest29430-21grep08:15:153
2892199471,2cyclictest0-21swapper/110:59:441
28923994517,4cyclictest41-21ksoftirqd/309:10:263
2892399445,2cyclictest0-21swapper/310:55:183
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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