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2026-04-19 - 05:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sun Apr 19, 2026 00:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
209772226166,49sleep00-21swapper/019:06:480
138591209168,22phc2sys0-21swapper/319:05:473
209492205171,22sleep20-21swapper/219:06:252
209532201167,22sleep10-21swapper/119:06:291
2123528361,12sleep00-21swapper/019:10:000
21528997126,8cyclictest25-21ksoftirqd/119:50:001
21528996331,3cyclictest25-21ksoftirqd/121:00:201
21528995927,8cyclictest25-21ksoftirqd/119:10:141
21528995821,7cyclictest25-21ksoftirqd/119:55:171
21528995819,9cyclictest25-21ksoftirqd/120:40:131
21528995819,4cyclictest25-21ksoftirqd/100:00:001
138491580,45ptp4l0-21swapper/319:10:023
21528995726,9cyclictest25-21ksoftirqd/119:40:141
21528995622,7cyclictest25-21ksoftirqd/122:30:251
21528995618,7cyclictest25-21ksoftirqd/121:40:231
138491560,1ptp4l401ktimersoftd/319:21:183
2152899552,9cyclictest25-21ksoftirqd/120:30:001
2152899552,9cyclictest25-21ksoftirqd/120:30:001
21528995522,7cyclictest25-21ksoftirqd/119:15:241
21528995419,5cyclictest25-21ksoftirqd/123:00:201
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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