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2026-08-25 - 10:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Tue Aug 25, 2026 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1149922840,3sleep0101ktimersoftd/019:05:180
128912202167,23sleep30-21swapper/319:07:053
127732201168,22sleep10-21swapper/119:05:351
129282200167,22sleep20-21swapper/219:07:302
2366521800,6sleep11341499cyclictest21:40:001
956221730,3sleep01341399cyclictest22:15:170
1517121500,6sleep31341699cyclictest19:10:263
13415996024,4cyclictest33-21ksoftirqd/219:30:142
1341499601,27cyclictest16395-21apt-key23:35:121
13415995728,8cyclictest33-21ksoftirqd/220:15:002
13415995628,7cyclictest33-21ksoftirqd/221:59:592
138491550,1ptp4l401ktimersoftd/300:05:483
13415995524,5cyclictest33-21ksoftirqd/223:00:142
13415995522,7cyclictest33-21ksoftirqd/200:25:002
138491540,1ptp4l401ktimersoftd/323:57:163
1341599525,44cyclictest21915-21irqrtprio19:25:232
13415995237,7cyclictest33-21ksoftirqd/219:40:022
13415995221,8cyclictest33-21ksoftirqd/223:10:002
13413995245,4cyclictest28713-21sh21:50:000
13415995125,3cyclictest33-21ksoftirqd/219:40:142
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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