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2026-08-14 - 15:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Fri Aug 14, 2026 00:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591228167,49phc2sys0-21swapper/319:06:583
14452204169,23sleep00-21swapper/019:06:460
14762203170,21sleep20-21swapper/219:07:042
13862202168,22sleep10-21swapper/119:06:041
2991321620,6sleep1216199cyclictest20:05:121
2195021610,2sleep00-21swapper/022:00:130
1482921610,2sleep1216199cyclictest21:45:171
2668721490,8sleep2216299cyclictest23:15:012
2163996838,3cyclictest41-21ksoftirqd/319:25:163
2163996731,8cyclictest41-21ksoftirqd/323:50:013
2163996632,9cyclictest41-21ksoftirqd/322:20:193
216299667,21cyclictest412-21/usr/sbin/munin00:30:212
216299661,21cyclictest30196-21cut00:25:202
2163996532,4cyclictest41-21ksoftirqd/320:40:003
2163996532,4cyclictest41-21ksoftirqd/320:40:003
2163996530,8cyclictest41-21ksoftirqd/319:55:013
216299651,29cyclictest3658-21sshd22:27:252
2163996430,8cyclictest41-21ksoftirqd/320:10:203
2163996428,9cyclictest41-21ksoftirqd/323:35:003
2163996428,8cyclictest41-21ksoftirqd/319:20:133
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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