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2026-07-10 - 06:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Fri Jul 10, 2026 00:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
88332233169,21sleep10-21swapper/119:09:201
86922205170,23sleep30-21swapper/319:07:293
88322202170,21sleep00-21swapper/019:09:200
86032200167,22sleep20-21swapper/219:06:292
711821830,7sleep1917899cyclictest20:10:141
2488321730,3sleep3918099cyclictest00:00:143
2951921420,7sleep2917999cyclictest00:10:002
888628363,11sleep10-21swapper/119:10:001
9180996926,4cyclictest41-21ksoftirqd/323:00:193
9180996531,4cyclictest41-21ksoftirqd/321:05:013
9180996426,7cyclictest41-21ksoftirqd/300:20:143
9180996324,10cyclictest41-21ksoftirqd/322:50:223
9180996229,4cyclictest41-21ksoftirqd/320:10:133
9180996228,8cyclictest41-21ksoftirqd/321:30:273
9180996228,4cyclictest41-21ksoftirqd/320:35:003
9180996221,8cyclictest41-21ksoftirqd/320:55:273
9180996128,4cyclictest41-21ksoftirqd/319:15:143
9180996032,7cyclictest41-21ksoftirqd/319:45:013
9180996031,4cyclictest41-21ksoftirqd/323:20:193
9180996030,4cyclictest41-21ksoftirqd/319:35:143
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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