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2026-03-19 - 13:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Thu Mar 19, 2026 00:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591203168,23phc2sys0-21swapper/319:07:263
40332201167,22sleep10-21swapper/119:05:031
40342199167,21sleep20-21swapper/219:05:042
61422198166,22sleep00-21swapper/019:08:360
297621450,7sleep0668199cyclictest21:10:230
168972770,1sleep30-21swapper/319:30:133
138491560,1ptp4l401ktimersoftd/322:08:123
69582550,4sleep20-21swapper/223:30:122
269822540,4sleep2321ktimersoftd/219:50:132
21032520,2sleep20-21swapper/200:25:132
138491520,1ptp4l401ktimersoftd/322:20:113
153902510,2sleep00-21swapper/021:35:220
145812470,2sleep10-21swapper/121:35:141
138491470,6ptp4l401ktimersoftd/323:49:003
6682994429,13cyclictest25-21ksoftirqd/122:35:101
6684994338,3cyclictest12094-21sshd20:25:133
6683994136,3cyclictest33-21ksoftirqd/223:50:012
6681994135,4cyclictest11447-21cron19:20:000
138491410,1ptp4l401ktimersoftd/323:56:213
138491410,0ptp4l401ktimersoftd/319:59:223
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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