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2026-08-12 - 11:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Wed Aug 12, 2026 00:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1213522670,5sleep012130-21od19:07:460
2314722440,26sleep10-21swapper/119:09:001
2307422340,4sleep323086-21sh19:09:393
896122210,7sleep28958-21rm19:06:392
2429521490,2sleep10-21swapper/122:45:221
142282680,2sleep30-21swapper/319:11:023
138491650,1ptp4l401ktimersoftd/323:00:173
73022600,5sleep09-21ksoftirqd/021:05:360
4483995913,9cyclictest33-21ksoftirqd/221:25:212
4483995819,9cyclictest33-21ksoftirqd/219:10:552
4483995713,9cyclictest33-21ksoftirqd/223:45:292
65842540,2sleep00-21swapper/019:12:230
138491540,1ptp4l401ktimersoftd/320:41:023
138491540,1ptp4l401ktimersoftd/320:41:023
4483995328,5cyclictest33-21ksoftirqd/223:50:192
161192520,2sleep10-21swapper/122:30:181
138491520,1ptp4l391rcuc/322:15:303
4483994717,8cyclictest33-21ksoftirqd/222:20:222
4483994711,7cyclictest33-21ksoftirqd/223:30:242
4483994617,8cyclictest33-21ksoftirqd/221:55:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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