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2026-03-26 - 06:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Thu Mar 26, 2026 00:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591205171,23phc2sys0-21swapper/319:05:523
69292201169,21sleep20-21swapper/219:09:152
66432201168,22sleep00-21swapper/019:05:310
66392201167,23sleep10-21swapper/119:05:291
699228363,11sleep30-21swapper/319:10:013
63272640,3sleep2728699cyclictest20:10:242
172822640,2sleep20-21swapper/223:50:012
138491540,1ptp4l401ktimersoftd/319:40:573
7287994941,5cyclictest14522-21cron22:39:593
138491480,1ptp4l401ktimersoftd/320:38:583
131772450,3sleep213181-21irqrtprio22:35:182
7287994431,11cyclictest41-21ksoftirqd/320:30:133
138491420,0ptp4l401ktimersoftd/322:24:133
138491410,0ptp4l401ktimersoftd/300:20:003
7287994035,3cyclictest41-21ksoftirqd/323:35:013
7287994011,7cyclictest41-21ksoftirqd/319:54:593
728799400,2cyclictest121rcu_preempt00:05:013
50798400,2rtkit-daemon0-21swapper/120:40:441
138491400,1ptp4l401ktimersoftd/320:53:443
138491400,0ptp4l401ktimersoftd/322:15:133
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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