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2026-05-05 - 08:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Tue May 05, 2026 00:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591208141,23phc2sys0-21swapper/319:06:563
281612204170,22sleep00-21swapper/019:05:450
283112203167,24sleep10-21swapper/119:07:351
282262200168,21sleep20-21swapper/219:06:352
1384911210,1ptp4l12821-21ls00:00:273
138491650,1ptp4l401ktimersoftd/300:15:593
271192590,2sleep00-21swapper/000:30:190
155842580,2sleep10-21swapper/121:55:271
40102550,2sleep30-21swapper/320:30:123
2849725538,10sleep10-21swapper/119:10:001
28792995429,9cyclictest33-21ksoftirqd/219:15:132
28792995024,8cyclictest33-21ksoftirqd/222:10:252
28792994925,8cyclictest33-21ksoftirqd/222:50:142
28792994919,7cyclictest33-21ksoftirqd/222:48:552
2879299491,6cyclictest0-21swapper/223:40:242
28792994819,7cyclictest33-21ksoftirqd/200:37:182
2879299479,5cyclictest33-21ksoftirqd/219:14:472
28792994718,7cyclictest33-21ksoftirqd/223:53:142
134432460,2sleep10-21swapper/120:50:001
2879299453,7cyclictest20589-21sed22:05:272
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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