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2026-09-08 - 07:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Tue Sep 08, 2026 00:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
307682206172,23sleep30-21swapper/319:09:033
305732203170,21sleep20-21swapper/219:06:372
305402201168,22sleep10-21swapper/119:06:121
305082199165,22sleep00-21swapper/019:05:460
630221620,6sleep03113399cyclictest23:40:270
2589321380,7sleep13113499cyclictest00:20:231
138491790,0ptp4l391rcuc/300:35:123
138491780,1ptp4l21168-21ls00:10:283
138491730,1ptp4l391rcuc/323:20:173
31135997135,3cyclictest33-21ksoftirqd/200:35:272
138491650,1ptp4l401ktimersoftd/322:45:243
31135996430,5cyclictest33-21ksoftirqd/222:00:222
31135996130,4cyclictest33-21ksoftirqd/223:20:182
31135996034,6cyclictest33-21ksoftirqd/222:15:002
31135996029,4cyclictest33-21ksoftirqd/223:00:002
31135996029,4cyclictest33-21ksoftirqd/223:00:002
31135996016,4cyclictest33-21ksoftirqd/222:42:542
31135995921,7cyclictest33-21ksoftirqd/219:30:252
138491590,1ptp4l401ktimersoftd/300:05:253
31135995830,7cyclictest33-21ksoftirqd/220:15:272
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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