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2026-04-22 - 19:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Wed Apr 22, 2026 12:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
251262206173,22sleep20-21swapper/207:06:192
251602204170,22sleep10-21swapper/107:06:461
138591203167,24phc2sys0-21swapper/307:05:313
251292199166,22sleep00-21swapper/007:06:200
1043721440,6sleep02570999cyclictest09:55:010
254172134106,15sleep20-21swapper/207:10:012
25710997025,10cyclictest25-21ksoftirqd/111:35:191
25710996631,4cyclictest25-21ksoftirqd/108:55:151
25712996528,8cyclictest41-21ksoftirqd/308:10:003
25712996429,8cyclictest41-21ksoftirqd/310:58:143
25712996427,8cyclictest41-21ksoftirqd/310:10:233
25712996427,8cyclictest41-21ksoftirqd/310:10:233
25712996230,4cyclictest41-21ksoftirqd/309:15:003
25712996230,4cyclictest41-21ksoftirqd/309:15:003
25712996227,7cyclictest41-21ksoftirqd/311:10:013
25712996225,9cyclictest41-21ksoftirqd/309:40:003
25712996130,8cyclictest41-21ksoftirqd/308:25:153
25712996130,10cyclictest41-21ksoftirqd/309:20:233
25712996129,8cyclictest41-21ksoftirqd/308:50:263
25712996129,6cyclictest41-21ksoftirqd/309:45:133
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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