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2026-02-16 - 20:32
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Mon Feb 16, 2026 12:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591229162,23phc2sys0-21swapper/307:07:253
44572203170,22sleep20-21swapper/207:09:242
41832202169,22sleep10-21swapper/107:05:491
41622198166,21sleep00-21swapper/007:05:320
254121620,3sleep3480799cyclictest08:10:133
41121460,5sleep1480599cyclictest11:20:021
480699649,9cyclictest0-21swapper/209:00:192
480699639,19cyclictest0-21swapper/208:40:122
480699639,17cyclictest0-21swapper/209:45:112
4804996328,7cyclictest9-21ksoftirqd/008:35:250
284532630,3sleep328457-21missed_timers07:55:223
4804996226,6cyclictest9-21ksoftirqd/009:40:010
480699619,11cyclictest16100-21irqrtprio10:45:192
4806996014,9cyclictest29299-21sed12:15:242
4804996030,4cyclictest9-21ksoftirqd/012:10:230
4804996023,6cyclictest9-21ksoftirqd/007:10:160
4804996022,5cyclictest9-21ksoftirqd/007:30:140
480699597,16cyclictest0-21swapper/209:58:042
4806995911,11cyclictest23326-21sed08:50:192
4806995910,9cyclictest9768-21/usr/sbin/munin07:20:182
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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