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2026-06-28 - 15:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sun Jun 28, 2026 12:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
84732208173,23sleep30-21swapper/307:08:293
83182202170,21sleep20-21swapper/207:06:272
83102201168,22sleep10-21swapper/107:06:221
82492200168,21sleep00-21swapper/007:05:320
397621680,6sleep1889099cyclictest09:10:131
85982160121,13sleep20-21swapper/207:10:012
53152660,3sleep35318-21unixbench_singl11:20:253
76922570,2sleep00-21swapper/012:30:240
138491560,1ptp4l401ktimersoftd/311:27:083
138491560,1ptp4l401ktimersoftd/310:12:303
86642530,2sleep10-21swapper/111:30:141
138491530,1ptp4l401ktimersoftd/310:28:483
138491530,1ptp4l401ktimersoftd/307:51:323
8891994819,26cyclictest0-21swapper/211:40:252
889199461,42cyclictest13127-21latency_hist11:40:012
138491430,0ptp4l401ktimersoftd/312:08:443
138491430,0ptp4l401ktimersoftd/310:40:073
8890994034,3cyclictest29147-21grep11:05:181
8892993933,3cyclictest775-21ls09:05:003
8890993931,5cyclictest25-21ksoftirqd/111:40:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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