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2025-12-01 - 18:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Mon Dec 01, 2025 12:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
231942223156,22sleep20-21swapper/207:07:142
231402203169,22sleep00-21swapper/007:06:310
427791202125,66phc2sys0-21swapper/307:05:193
211762202168,22sleep10-21swapper/107:05:081
725021410,3sleep10-21swapper/107:40:181
31442700,2sleep20-21swapper/210:45:262
266582630,4sleep326654-21gpgv12:40:003
247712570,4sleep024776-21kernelversion07:10:200
427291560,1ptp4l401ktimersoftd/311:14:123
427291560,1ptp4l401ktimersoftd/311:14:123
234622510,1sleep00-21swapper/012:30:270
202622510,1sleep20-21swapper/209:10:222
23706994944,3cyclictest1442-21sh11:50:013
282312470,2sleep20-21swapper/211:35:242
2370499441,41cyclictest0-21swapper/108:50:271
427291430,36ptp4l0-21swapper/307:10:013
427291430,0ptp4l401ktimersoftd/312:20:193
23704994315,26cyclictest0-21swapper/110:53:261
23703994331,10cyclictest9-21ksoftirqd/008:20:000
427291420,0ptp4l401ktimersoftd/312:10:193
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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