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2026-06-25 - 22:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Thu Jun 25, 2026 12:46:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
89332208175,22sleep20-21swapper/207:09:382
87542207172,23sleep30-21swapper/307:07:183
67352202167,23sleep10-21swapper/107:05:031
88122201167,22sleep00-21swapper/007:08:030
2472621460,6sleep1925599cyclictest12:00:131
2642321400,6sleep3925799cyclictest07:45:003
138491690,1ptp4l401ktimersoftd/310:17:473
9255996228,8cyclictest25-21ksoftirqd/110:30:241
9255996132,4cyclictest25-21ksoftirqd/109:00:121
9255996129,7cyclictest25-21ksoftirqd/112:05:171
9255996129,7cyclictest25-21ksoftirqd/112:05:161
9255996129,7cyclictest25-21ksoftirqd/110:40:261
9255996031,4cyclictest25-21ksoftirqd/109:45:241
9255996029,4cyclictest25-21ksoftirqd/111:59:591
9255996027,6cyclictest25-21ksoftirqd/110:55:271
9255996024,7cyclictest25-21ksoftirqd/111:30:251
9255996024,7cyclictest25-21ksoftirqd/108:00:251
9255996022,7cyclictest25-21ksoftirqd/109:45:001
9255995932,4cyclictest25-21ksoftirqd/108:10:131
9255995931,4cyclictest25-21ksoftirqd/111:24:591
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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