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2026-07-02 - 07:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Thu Jul 02, 2026 00:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
10972206171,23sleep30-21swapper/319:05:333
14262204170,23sleep10-21swapper/119:09:371
12362202169,22sleep20-21swapper/219:07:222
11052202169,22sleep00-21swapper/019:05:390
3051821490,2sleep00-21swapper/023:20:210
1307521390,2sleep2175699cyclictest22:45:212
14572132106,14sleep00-21swapper/019:10:010
1519921280,6sleep2175699cyclictest23:55:172
1519921280,6sleep2175699cyclictest23:55:172
133602670,3sleep3391rcuc/320:35:233
1757996527,4cyclictest41-21ksoftirqd/323:20:143
1756996330,4cyclictest33-21ksoftirqd/220:30:192
1756996328,4cyclictest33-21ksoftirqd/219:10:232
1756996229,4cyclictest33-21ksoftirqd/222:40:142
1756996029,4cyclictest33-21ksoftirqd/220:40:242
1757995927,10cyclictest41-21ksoftirqd/323:55:263
1757995927,10cyclictest41-21ksoftirqd/323:55:263
1756995930,4cyclictest33-21ksoftirqd/223:10:002
1756995927,4cyclictest33-21ksoftirqd/221:55:202
1756995926,4cyclictest33-21ksoftirqd/223:45:142
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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