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2026-09-05 - 13:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sat Sep 05, 2026 00:45:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591235168,22phc2sys0-21swapper/319:09:363
578622270,13sleep10-21swapper/119:05:181
71642206175,21sleep20-21swapper/219:09:172
71132202167,23sleep00-21swapper/019:08:390
2962721610,2sleep3751499cyclictest23:05:233
72202132106,14sleep00-21swapper/019:10:000
7512996830,9cyclictest25-21ksoftirqd/121:50:121
191452610,4sleep319149-21phc2sys22:45:223
5512570,7sleep1751299cyclictest23:15:001
7512995613,10cyclictest25-21ksoftirqd/120:10:281
138491540,1ptp4l401ktimersoftd/322:01:143
751299539,9cyclictest25-21ksoftirqd/121:30:021
7512995218,6cyclictest25-21ksoftirqd/119:40:211
70132520,2sleep00-21swapper/000:30:210
138491520,1ptp4l401ktimersoftd/321:24:183
7512994710,4cyclictest25-21ksoftirqd/121:15:151
7511994716,3cyclictest9-21ksoftirqd/021:55:190
138491470,0ptp4l401ktimersoftd/320:28:463
751299469,4cyclictest25-21ksoftirqd/122:15:211
751299468,4cyclictest25-21ksoftirqd/121:40:251
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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