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2026-05-20 - 08:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Wed May 20, 2026 00:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591208163,33phc2sys0-21swapper/319:08:363
244642207174,22sleep10-21swapper/119:06:551
243772204170,22sleep20-21swapper/219:05:462
246182201168,21sleep00-21swapper/019:08:540
138491560,1ptp4l401ktimersoftd/322:35:173
61372530,1sleep00-21swapper/021:45:190
289652530,2sleep20-21swapper/223:35:212
138491530,0ptp4l401ktimersoftd/322:47:283
72582520,5sleep07261-21unixbench_singl22:50:300
299392520,4sleep3401ktimersoftd/322:35:003
138491510,1ptp4l401ktimersoftd/319:17:143
138491480,0ptp4l401ktimersoftd/321:19:393
25000994639,4cyclictest27311-21cron21:25:003
232512450,35sleep341-21ksoftirqd/300:30:143
138491440,0ptp4l401ktimersoftd/322:51:263
138491430,0ptp4l401ktimersoftd/321:55:213
138491430,0ptp4l401ktimersoftd/321:40:333
2499999421,38cyclictest27588-21sh23:35:012
138491420,0ptp4l401ktimersoftd/300:36:263
24999994136,3cyclictest33-21ksoftirqd/223:10:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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