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2026-08-23 - 19:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sun Aug 23, 2026 12:45:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4432204169,23sleep30-21swapper/307:06:083
7052202169,22sleep10-21swapper/107:09:121
7332201168,22sleep00-21swapper/007:09:310
4562201167,22sleep20-21swapper/207:06:152
281652690,5sleep228166-21unixbench_multi12:20:262
281652690,5sleep228166-21unixbench_multi12:20:262
144352570,1sleep00-21swapper/008:40:160
144352570,1sleep00-21swapper/008:40:160
324192540,3sleep232423-21irqrtprio11:25:192
138491540,1ptp4l401ktimersoftd/310:00:253
138491530,1ptp4l401ktimersoftd/311:25:443
296532490,2sleep10-21swapper/109:10:181
129082460,1sleep20-21swapper/211:50:212
138491450,0ptp4l401ktimersoftd/312:30:163
138491450,0ptp4l401ktimersoftd/308:25:043
96132440,5sleep39617-21irqrtprio08:30:213
233142440,1sleep30-21swapper/311:05:253
138491440,0ptp4l401ktimersoftd/312:19:173
107299430,5cyclictest26092-21taskset11:10:531
138491420,0ptp4l401ktimersoftd/309:55:283
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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