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2026-07-21 - 02:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Mon Jul 20, 2026 12:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
42752205171,22sleep10-21swapper/107:05:591
138591205170,23phc2sys0-21swapper/307:09:123
45152204170,22sleep00-21swapper/007:09:080
42762200167,22sleep20-21swapper/207:06:012
2124321720,5sleep3488499cyclictest10:55:203
4882997227,7cyclictest25-21ksoftirqd/110:45:161
4882997125,7cyclictest25-21ksoftirqd/109:00:281
4882996820,6cyclictest25-21ksoftirqd/112:39:591
488499667,21cyclictest29999-21latency_hist11:15:003
488499667,21cyclictest29999-21latency_hist11:15:003
4882996429,6cyclictest25-21ksoftirqd/110:15:211
4882996330,11cyclictest25-21ksoftirqd/107:25:121
4882996329,4cyclictest25-21ksoftirqd/107:35:011
4882996228,6cyclictest25-21ksoftirqd/111:45:221
4882996228,4cyclictest25-21ksoftirqd/111:30:001
488499600,21cyclictest0-21swapper/310:20:233
4882996027,5cyclictest25-21ksoftirqd/108:40:141
313852600,2sleep00-21swapper/012:20:180
4882995928,9cyclictest25-21ksoftirqd/108:20:141
4882995926,10cyclictest25-21ksoftirqd/107:50:221
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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