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2026-06-14 - 16:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sun Jun 14, 2026 12:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
195712203169,23sleep20-21swapper/207:08:042
138591203173,20phc2sys0-21swapper/307:05:583
195122201168,21sleep00-21swapper/007:07:170
195402200167,22sleep10-21swapper/107:07:391
200562560,1sleep120059-21sed12:35:141
20024995327,8cyclictest41-21ksoftirqd/307:50:133
20024995324,9cyclictest41-21ksoftirqd/311:35:133
20024995229,4cyclictest41-21ksoftirqd/308:50:283
138491520,0ptp4l391rcuc/312:00:543
20024995025,9cyclictest41-21ksoftirqd/310:25:223
20024995022,9cyclictest41-21ksoftirqd/309:40:123
20024995022,4cyclictest41-21ksoftirqd/311:40:233
20024994923,8cyclictest41-21ksoftirqd/311:10:243
2002499484,7cyclictest41-21ksoftirqd/307:23:553
2002499471,6cyclictest32102-21date11:55:003
2002499462,6cyclictest41-21ksoftirqd/311:01:063
2002499455,6cyclictest41-21ksoftirqd/307:10:113
2002499452,6cyclictest41-21ksoftirqd/312:11:593
20024994516,7cyclictest41-21ksoftirqd/311:35:003
20022994540,3cyclictest25-21ksoftirqd/111:40:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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