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2026-08-09 - 19:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sun Aug 09, 2026 00:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591216167,22phc2sys0-21swapper/319:08:123
116912203170,22sleep20-21swapper/219:07:502
115432203169,23sleep10-21swapper/119:05:591
117362202168,22sleep00-21swapper/019:08:250
118602131106,14sleep00-21swapper/019:10:010
1215399633,17cyclictest12446-21df_abs21:20:142
129422570,4sleep30-21swapper/323:30:153
125922570,3sleep30-21swapper/320:15:183
1215399527,6cyclictest1186-21cat23:05:222
1215399501,10cyclictest15934-21irqrtprio23:35:202
1215399494,11cyclictest23493-21cut23:50:192
1215399492,7cyclictest0-21swapper/223:10:242
1215399484,11cyclictest7033-21latency_hist20:04:592
1215399480,3cyclictest24017-21ps22:45:232
1215399470,16cyclictest13922-21/usr/sbin/munin00:35:252
1215399461,8cyclictest19867-21diskstats21:35:162
1215399450,12cyclictest27677-21iostat19:40:192
138491440,0ptp4l401ktimersoftd/322:50:333
138491440,0ptp4l401ktimersoftd/320:56:403
12154994438,3cyclictest16700-21cron21:30:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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