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2026-06-07 - 00:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sat Jun 06, 2026 00:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
24772229163,21sleep20-21swapper/219:09:382
138591205170,23phc2sys0-21swapper/319:06:363
22072204172,21sleep00-21swapper/019:06:470
22332202168,23sleep10-21swapper/119:07:081
1839421860,7sleep1279999cyclictest21:50:151
186521560,7sleep0279899cyclictest00:30:210
90352590,4sleep19040-21latency22:35:191
280199594,11cyclictest16953-21ps22:50:233
280199562,15cyclictest17117-21ssh20:40:243
280199553,12cyclictest13027-21date20:35:003
280199502,17cyclictest3621-21/usr/sbin/munin21:20:163
280099481,44cyclictest0-21swapper/222:40:242
280199461,17cyclictest17961-21/usr/sbin/munin00:00:223
138491460,0ptp4l401ktimersoftd/322:01:223
2800994541,2cyclictest12799-21turbostat.cron23:49:592
135191450,9getstats0-21swapper/322:15:503
138491440,0ptp4l401ktimersoftd/319:39:243
2801994338,3cyclictest13536-21fschecks_count20:35:163
280099431,39cyclictest14872-21cron19:35:002
138491430,0ptp4l401ktimersoftd/320:47:043
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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