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2026-07-15 - 01:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Tue Jul 14, 2026 12:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
231322228201,18sleep00-21swapper/007:06:590
230932206172,23sleep10-21swapper/107:06:271
138591204171,22phc2sys0-21swapper/307:07:003
231292200167,21sleep20-21swapper/207:06:572
219921650,6sleep12366699cyclictest08:35:171
2214321600,3sleep32366899cyclictest12:30:193
138491630,9ptp4l401ktimersoftd/310:37:393
23667995719,6cyclictest33-21ksoftirqd/208:15:002
138491560,1ptp4l391rcuc/308:00:283
135191550,2getstats0-21swapper/309:40:113
23667995215,7cyclictest33-21ksoftirqd/207:50:012
148832510,2sleep10-21swapper/110:05:201
23667995019,4cyclictest33-21ksoftirqd/212:20:222
23667994919,7cyclictest33-21ksoftirqd/209:30:182
23667994816,4cyclictest33-21ksoftirqd/210:55:002
23665994832,14cyclictest9-21ksoftirqd/012:35:000
23667994716,4cyclictest33-21ksoftirqd/208:00:202
2366799467,5cyclictest33-21ksoftirqd/208:30:172
23667994619,8cyclictest33-21ksoftirqd/212:10:192
23667994617,4cyclictest33-21ksoftirqd/211:50:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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