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2026-06-25 - 11:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Thu Jun 25, 2026 00:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
93572225166,48sleep10-21swapper/119:05:581
138591205171,23phc2sys0-21swapper/319:05:363
94402203170,22sleep20-21swapper/219:07:042
95502202168,22sleep00-21swapper/019:08:310
138491770,2ptp4l401ktimersoftd/319:10:023
996799666,12cyclictest12184-21latency_hist20:20:001
996799636,11cyclictest2592-21cpuspeed_turbos21:05:121
996799635,12cyclictest27554-21tr20:50:131
996799635,12cyclictest26718-21sed20:45:271
996799635,12cyclictest21471-21ls20:35:251
9967996310,10cyclictest18688-21ls22:40:241
996799628,10cyclictest30609-21ls23:05:201
996799628,10cyclictest11577-21ls19:10:251
996799627,11cyclictest19504-21latency_hist20:35:001
996799618,16cyclictest25914-21sed00:00:271
996799617,10cyclictest16325-21mailstats20:25:221
996799617,10cyclictest13877-21gzip19:15:231
996799615,12cyclictest0-21swapper/123:00:261
996799614,17cyclictest0-21swapper/121:50:231
996799614,16cyclictest0-21swapper/121:20:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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