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2026-06-03 - 21:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Wed Jun 03, 2026 12:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
49182225162,52sleep20-21swapper/207:06:052
138591207173,23phc2sys0-21swapper/307:08:113
52142204140,22sleep00-21swapper/007:09:490
52202199166,22sleep10-21swapper/107:09:541
523028261,11sleep00-21swapper/007:10:010
5522996417,6cyclictest25-21ksoftirqd/111:45:011
141952640,7sleep2552399cyclictest08:30:212
5522996329,4cyclictest25-21ksoftirqd/111:00:241
5522996328,7cyclictest25-21ksoftirqd/112:25:261
5522996230,4cyclictest25-21ksoftirqd/110:25:011
5522996228,7cyclictest25-21ksoftirqd/111:45:141
5522996228,7cyclictest25-21ksoftirqd/108:20:251
5522996227,7cyclictest25-21ksoftirqd/107:50:131
5521996231,3cyclictest9-21ksoftirqd/012:00:260
5521996231,3cyclictest9-21ksoftirqd/012:00:260
5522996132,9cyclictest25-21ksoftirqd/107:30:011
5522996131,4cyclictest25-21ksoftirqd/111:50:261
5522996130,4cyclictest25-21ksoftirqd/111:30:121
5522996130,4cyclictest25-21ksoftirqd/111:30:121
5522996128,4cyclictest25-21ksoftirqd/108:25:251
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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