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2026-05-17 - 09:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sun May 17, 2026 00:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
325572203169,23sleep30-21swapper/319:09:303
324432201167,23sleep10-21swapper/119:07:591
323172201168,22sleep20-21swapper/219:06:282
324472198166,21sleep00-21swapper/019:08:020
2898521440,7sleep344299cyclictest20:05:173
3260029167,13sleep20-21swapper/219:10:002
138491690,1ptp4l401ktimersoftd/323:40:213
317892640,2sleep10-21swapper/120:10:161
222652620,3sleep319352-21apache219:50:253
440995831,7cyclictest25-21ksoftirqd/122:59:591
440995629,3cyclictest25-21ksoftirqd/123:25:211
440995626,4cyclictest25-21ksoftirqd/119:30:301
440995625,7cyclictest25-21ksoftirqd/123:00:001
440995624,4cyclictest25-21ksoftirqd/123:40:221
440995620,4cyclictest25-21ksoftirqd/121:40:241
440995525,3cyclictest25-21ksoftirqd/122:25:281
440995520,4cyclictest25-21ksoftirqd/121:30:141
440995425,4cyclictest25-21ksoftirqd/120:15:121
440995422,8cyclictest25-21ksoftirqd/121:00:221
440995422,4cyclictest25-21ksoftirqd/122:00:211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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