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2026-08-15 - 03:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sat Aug 15, 2026 00:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
246872207173,22sleep30-21swapper/319:07:243
245362202169,21sleep00-21swapper/019:05:330
245992200167,22sleep20-21swapper/219:06:152
246902199166,22sleep10-21swapper/119:07:261
1882421450,6sleep32518599cyclictest23:15:243
2518499672,62cyclictest19700-21turbostat20:05:002
2518399620,21cyclictest22336-21date21:15:001
70162610,2sleep10-21swapper/122:55:001
242042570,5sleep024209-21unixbench_multi20:10:270
138491550,1ptp4l401ktimersoftd/319:52:323
148692510,3sleep32518599cyclictest22:05:123
109272500,2sleep20-21swapper/221:55:202
230592490,2sleep30-21swapper/321:15:173
25184994842,3cyclictest4410-21ls23:54:592
262192440,1sleep10-21swapper/121:20:221
262192440,1sleep10-21swapper/121:20:211
2518399440,42cyclictest0-21swapper/121:25:231
25185994315,26cyclictest17143-21kworker/3:120:15:233
138491430,0ptp4l401ktimersoftd/320:54:553
138491430,0ptp4l401ktimersoftd/319:25:503
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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