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2026-02-13 - 20:19
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Fri Feb 13, 2026 12:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591203170,22phc2sys0-21swapper/307:07:033
286622200165,23sleep00-21swapper/007:08:570
285762200167,22sleep10-21swapper/107:07:511
287502199167,21sleep20-21swapper/207:10:002
772321430,5sleep12904699cyclictest09:40:171
772321430,5sleep12904699cyclictest09:40:171
169312900,4sleep32904899cyclictest10:00:133
50492640,2sleep229044-21cyclictest09:35:172
108822590,2sleep20-21swapper/211:55:222
123392580,7sleep02904599cyclictest08:45:120
1385915335,12phc2sys0-21swapper/307:10:013
4122500,3sleep30-21swapper/309:25:223
29047994929,17cyclictest33-21ksoftirqd/210:30:592
29047994616,28cyclictest0-21swapper/210:15:222
138491430,0ptp4l401ktimersoftd/311:35:243
138491430,0ptp4l401ktimersoftd/309:45:023
29047994213,27cyclictest0-21swapper/210:25:232
29046994236,3cyclictest1303-21runrttasks08:40:591
138491420,0ptp4l401ktimersoftd/308:15:193
138491410,0ptp4l401ktimersoftd/311:08:183
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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