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2026-05-21 - 00:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Wed May 20, 2026 12:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591232164,24phc2sys0-21swapper/307:09:113
120222203169,23sleep10-21swapper/107:08:481
118762202167,23sleep20-21swapper/207:07:002
118742199165,22sleep00-21swapper/007:06:580
800821340,3sleep01240699cyclictest11:20:150
1211528162,10sleep10-21swapper/107:10:011
12408996530,6cyclictest33-21ksoftirqd/207:54:592
12408996331,6cyclictest33-21ksoftirqd/211:35:132
12408996331,6cyclictest33-21ksoftirqd/211:35:132
12408996331,5cyclictest33-21ksoftirqd/207:45:192
12408996330,6cyclictest33-21ksoftirqd/208:30:272
12408996329,5cyclictest33-21ksoftirqd/211:20:242
12408996328,6cyclictest33-21ksoftirqd/208:30:002
12408996327,6cyclictest33-21ksoftirqd/211:40:242
12408996232,5cyclictest33-21ksoftirqd/208:10:002
12408996230,5cyclictest33-21ksoftirqd/210:05:222
12408996228,6cyclictest33-21ksoftirqd/208:45:242
12408996227,5cyclictest33-21ksoftirqd/212:10:002
12408996226,8cyclictest33-21ksoftirqd/207:15:142
12408996129,6cyclictest33-21ksoftirqd/207:10:172
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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