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2026-08-20 - 12:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Thu Aug 20, 2026 00:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
276882234172,51sleep20-21swapper/219:06:442
276592226160,22sleep30-21swapper/319:06:213
277492204170,22sleep10-21swapper/119:07:321
276352199167,21sleep00-21swapper/019:06:010
1385918564,11phc2sys0-21swapper/319:10:003
138491650,1ptp4l401ktimersoftd/320:58:503
192652620,1sleep30-21swapper/322:05:173
316672600,5sleep22823499cyclictest19:15:192
28234996023,5cyclictest33-21ksoftirqd/223:40:242
28234995723,9cyclictest33-21ksoftirqd/223:55:012
28234995722,6cyclictest33-21ksoftirqd/220:15:232
28234995721,5cyclictest33-21ksoftirqd/219:45:162
188822570,2sleep00-21swapper/023:10:130
28234995626,5cyclictest33-21ksoftirqd/221:45:112
28234995625,8cyclictest33-21ksoftirqd/221:35:172
28234995625,8cyclictest33-21ksoftirqd/221:35:172
28234995623,5cyclictest33-21ksoftirqd/219:30:202
28234995621,5cyclictest33-21ksoftirqd/220:30:092
28234995530,8cyclictest33-21ksoftirqd/200:04:592
28234995521,6cyclictest33-21ksoftirqd/222:25:152
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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