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2025-09-16 - 05:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Tue Sep 16, 2025 00:45:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
134791204171,22phc2sys0-21swapper/319:05:363
216102202167,23sleep20-21swapper/219:08:042
215292202168,22sleep00-21swapper/019:07:090
215302201168,22sleep10-21swapper/119:07:111
217602133107,14sleep10-21swapper/119:10:011
1082621190,3sleep30-21swapper/322:00:243
1347918565,11phc2sys0-21swapper/319:10:003
47292680,8sleep32205499cyclictest22:55:033
295612630,2sleep329560-21wc21:35:003
144292580,3sleep30-21swapper/320:00:003
181002570,2sleep00-21swapper/022:15:220
302462560,3sleep030251-21irqrtprio22:40:200
134991540,1ptp4l401ktimersoftd/321:52:493
130891500,1getstats0-21swapper/323:55:163
175522490,1sleep20-21swapper/200:25:132
22051994236,4cyclictest16848-21cron22:15:000
134991420,0ptp4l401ktimersoftd/319:25:173
134991420,0ptp4l401ktimersoftd/300:15:303
134991410,0ptp4l401ktimersoftd/321:49:173
22053994024,14cyclictest33-21ksoftirqd/219:45:272
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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