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2026-07-18 - 20:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sat Jul 18, 2026 12:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
103972206172,23sleep10-21swapper/107:09:561
103982201168,22sleep20-21swapper/207:09:562
138591200167,22phc2sys0-21swapper/307:09:563
103962195128,22sleep00-21swapper/007:09:540
3213121810,8sleep11070399cyclictest08:55:211
1357921650,5sleep31070599cyclictest12:39:593
464821000,1sleep10-21swapper/112:20:211
64542670,3sleep10-21swapper/112:25:131
1070299646,12cyclictest21183-21bc08:35:090
10705996317,4cyclictest41-21ksoftirqd/308:25:003
1070299635,16cyclictest8378-21latency_hist08:10:010
323812620,1sleep00-21swapper/007:50:250
79462610,5sleep17943-21turbostat11:24:591
1070299595,15cyclictest21718-21cut10:45:200
1070299594,16cyclictest24471-21irqrtprio07:35:180
1070299594,16cyclictest24471-21irqrtprio07:35:180
1070299594,12cyclictest4478-21sed09:05:200
1070299594,11cyclictest10237-21mailstats12:30:250
10705995826,7cyclictest41-21ksoftirqd/307:45:003
10704995830,4cyclictest33-21ksoftirqd/211:35:242
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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