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2025-05-03 - 01:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Fri May 02, 2025 12:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
251232207174,22sleep00-21swapper/007:09:010
250392203170,22sleep30-21swapper/307:07:553
248732203171,21sleep10-21swapper/107:05:441
248742201169,21sleep20-21swapper/207:05:462
2182021330,5sleep02548999cyclictest10:15:230
108342630,3sleep1231rcuc/109:55:181
130691610,4getstats2549299cyclictest11:12:373
239812540,5sleep323983-21irqrtprio10:20:193
134991540,1ptp4l391rcuc/312:28:163
25491995316,6cyclictest33-21ksoftirqd/212:10:232
25491995314,10cyclictest33-21ksoftirqd/211:20:012
24062530,4sleep22410-21cron08:34:592
86372520,2sleep30-21swapper/308:45:203
25491995223,4cyclictest33-21ksoftirqd/208:40:242
25491995220,17cyclictest33-21ksoftirqd/209:10:212
25491995220,17cyclictest33-21ksoftirqd/209:10:202
134991520,1ptp4l401ktimersoftd/307:50:083
25491995121,3cyclictest33-21ksoftirqd/208:20:272
25491995120,4cyclictest33-21ksoftirqd/211:10:172
25491995119,4cyclictest33-21ksoftirqd/212:30:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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