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2026-08-07 - 16:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Fri Aug 07, 2026 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591207173,23phc2sys0-21swapper/307:09:453
290522204170,23sleep10-21swapper/107:06:341
289702202169,22sleep20-21swapper/207:05:312
291352200166,22sleep00-21swapper/007:07:380
138491810,1ptp4l16445-21sed09:55:263
138491760,1ptp4l391rcuc/310:35:233
138491510,1ptp4l401ktimersoftd/307:54:153
2961999491,46cyclictest0-21swapper/209:40:232
29620994843,3cyclictest12113-21apt09:50:003
2961999440,2cyclictest0-21swapper/208:00:232
2961999440,2cyclictest0-21swapper/208:00:232
29620994338,3cyclictest22671-21fschecks_count08:00:143
29620994338,3cyclictest22671-21fschecks_count08:00:143
138491420,0ptp4l401ktimersoftd/312:36:123
138491420,0ptp4l401ktimersoftd/310:54:033
138491410,0ptp4l401ktimersoftd/308:29:173
138491410,0ptp4l401ktimersoftd/307:17:243
29620994025,13cyclictest41-21ksoftirqd/311:55:003
29617994033,4cyclictest23324-21irqrtprio11:15:180
138491400,1ptp4l0-21swapper/309:35:313
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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