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2026-03-11 - 19:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Wed Mar 11, 2026 12:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591220157,51phc2sys0-21swapper/307:08:563
180542206172,23sleep10-21swapper/107:06:401
180832202169,22sleep00-21swapper/007:07:030
181652200167,22sleep20-21swapper/207:08:012
1074921650,5sleep31861399cyclictest08:00:003
2492321400,6sleep21861299cyclictest09:30:252
138491670,1ptp4l401ktimersoftd/308:55:253
14422630,5sleep341-21ksoftirqd/310:55:153
130262590,7sleep01861099cyclictest10:15:010
272002580,3sleep227204-21ptp4l10:40:222
18613995821,9cyclictest41-21ksoftirqd/307:15:123
84442540,3sleep38446-21cpuspeed_turbos10:05:123
18610995421,3cyclictest9-21ksoftirqd/009:25:010
138491540,1ptp4l401ktimersoftd/308:51:403
18611995322,4cyclictest25-21ksoftirqd/108:00:121
18610995324,3cyclictest9-21ksoftirqd/007:15:010
18610995324,3cyclictest9-21ksoftirqd/007:15:010
70282520,2sleep10-21swapper/107:50:201
70282520,2sleep10-21swapper/107:50:191
18611995218,4cyclictest25-21ksoftirqd/110:25:261
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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