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2026-02-18 - 09:59
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Wed Feb 18, 2026 00:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
37492205171,22sleep30-21swapper/319:06:503
38662202168,22sleep10-21swapper/119:08:211
38352201167,22sleep20-21swapper/219:07:582
38652200166,22sleep00-21swapper/019:08:200
446221580,6sleep3428899cyclictest20:15:143
950121190,3sleep0428599cyclictest22:35:160
1385919379,7phc2sys0-21swapper/319:10:013
138491720,1ptp4l401ktimersoftd/300:02:473
104692670,1sleep00-21swapper/020:25:260
13462590,6sleep3428899cyclictest23:25:013
138491560,0ptp4l401ktimersoftd/300:25:263
103102550,2sleep30-21swapper/322:35:223
138491530,1ptp4l401ktimersoftd/322:43:463
189412510,2sleep20-21swapper/221:50:002
138491490,17ptp4l13617-21taskset21:35:573
135191490,9getstats0-21swapper/321:09:423
261512470,2sleep30-21swapper/323:10:013
156242450,2sleep30-21swapper/319:30:253
4287994438,3cyclictest23777-21cron20:55:002
138491430,1ptp4l401ktimersoftd/323:30:403
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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