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2026-07-20 - 12:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Mon Jul 20, 2026 00:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3138122170,9sleep00-21swapper/019:05:290
138591205171,23phc2sys0-21swapper/319:06:313
315472202168,22sleep10-21swapper/119:06:591
314912202168,23sleep20-21swapper/219:06:162
691021770,4sleep13207399cyclictest21:35:141
1385918463,11phc2sys0-21swapper/319:10:013
138491640,1ptp4l401ktimersoftd/322:51:493
138491620,1ptp4l401ktimersoftd/322:00:223
32073996123,7cyclictest25-21ksoftirqd/123:25:231
32073996123,7cyclictest25-21ksoftirqd/122:40:171
32073996027,7cyclictest25-21ksoftirqd/100:25:181
32073996023,7cyclictest25-21ksoftirqd/119:15:201
32073996022,4cyclictest25-21ksoftirqd/123:40:131
32073995927,8cyclictest25-21ksoftirqd/121:20:251
32073995923,7cyclictest25-21ksoftirqd/121:45:241
32073995923,3cyclictest25-21ksoftirqd/120:55:011
138491590,1ptp4l391rcuc/321:45:123
32073995824,6cyclictest25-21ksoftirqd/100:35:141
32073995823,4cyclictest25-21ksoftirqd/100:30:171
32073995820,8cyclictest25-21ksoftirqd/122:45:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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