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2026-02-19 - 13:57
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Thu Feb 19, 2026 00:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591200166,22phc2sys0-21swapper/319:08:223
112152194160,22sleep00-21swapper/019:07:510
113742186154,21sleep20-21swapper/219:09:492
112732170112,46sleep10-21swapper/119:08:371
1138928263,10sleep10-21swapper/119:10:021
138491720,1ptp4l391rcuc/321:04:273
11682996227,4cyclictest33-21ksoftirqd/219:15:002
46592610,3sleep14663-21cpuspeed_turbos00:20:141
149452610,2sleep221944-21apache220:20:172
11682996028,5cyclictest33-21ksoftirqd/219:50:192
11682995926,4cyclictest33-21ksoftirqd/220:25:242
11682995924,7cyclictest33-21ksoftirqd/222:45:232
11682995923,4cyclictest33-21ksoftirqd/200:05:002
11682995827,9cyclictest33-21ksoftirqd/222:25:142
11682995727,4cyclictest33-21ksoftirqd/221:30:142
11682995622,5cyclictest33-21ksoftirqd/222:40:142
11682995621,10cyclictest33-21ksoftirqd/221:00:172
1168299555,10cyclictest33-21ksoftirqd/220:55:242
11682995523,7cyclictest33-21ksoftirqd/223:45:212
11682995523,5cyclictest33-21ksoftirqd/223:35:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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