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2026-08-30 - 04:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sun Aug 30, 2026 00:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591224162,50phc2sys0-21swapper/319:07:003
321662223158,22sleep10-21swapper/119:06:231
321102202168,23sleep20-21swapper/219:05:402
322262200166,22sleep00-21swapper/019:07:060
2450121800,3sleep23274499cyclictest22:05:242
2233621500,6sleep33274599cyclictest20:55:253
232412680,2sleep223245-21cpuspeed_turbos21:00:132
157412630,5sleep015742-21sendmail23:59:590
1385915842,9phc2sys0-21swapper/319:10:013
138491560,1ptp4l391rcuc/320:50:263
138491540,1ptp4l401ktimersoftd/320:19:423
241592500,3sleep30-21swapper/300:15:153
3274599462,41cyclictest15424-21cron21:50:003
3245124532,7sleep10-21swapper/119:10:011
3274299441,40cyclictest15425-21cron21:50:000
134991430,7getstats0-21swapper/319:21:433
32743993934,3cyclictest25-21ksoftirqd/123:10:001
32744993832,4cyclictest33-21ksoftirqd/220:33:372
32744993831,4cyclictest33-21ksoftirqd/222:25:582
3274499380,2cyclictest0-21swapper/220:40:232
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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