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2026-08-28 - 13:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Fri Aug 28, 2026 00:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591231167,52phc2sys0-21swapper/319:08:533
229022202169,21sleep20-21swapper/219:07:142
230962201167,23sleep10-21swapper/119:09:461
229972201166,23sleep00-21swapper/019:08:280
1108421740,6sleep12340799cyclictest00:10:141
138491680,1ptp4l26910-21ls22:30:213
195892640,7sleep12340799cyclictest23:20:231
137272640,8sleep32340999cyclictest23:10:143
30842610,7sleep02340699cyclictest22:50:010
138491590,1ptp4l401ktimersoftd/322:24:433
138491550,1ptp4l401ktimersoftd/323:24:323
21452540,3sleep22144-21phc2sys20:35:232
138491530,1ptp4l401ktimersoftd/322:25:153
13262530,1sleep20-21swapper/222:45:172
138491510,1ptp4l391rcuc/321:39:063
224872490,1sleep30-21swapper/300:31:103
224872490,1sleep30-21swapper/300:31:103
138491460,0ptp4l401ktimersoftd/323:40:073
138491460,0ptp4l401ktimersoftd/319:20:193
23407994438,3cyclictest15437-21cron21:05:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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