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2026-07-12 - 10:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sun Jul 12, 2026 00:45:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138591232167,22phc2sys0-21swapper/319:09:413
294982207174,22sleep10-21swapper/119:09:441
292792205172,22sleep20-21swapper/219:06:592
292772200167,22sleep00-21swapper/019:06:570
194021340,5sleep12996399cyclictest19:15:281
2373921320,3sleep02996299cyclictest22:10:170
138491700,1ptp4l391rcuc/319:10:183
29964996231,3cyclictest33-21ksoftirqd/200:07:342
29964995433,3cyclictest33-21ksoftirqd/221:05:302
138491540,0ptp4l401ktimersoftd/322:40:263
29964995122,5cyclictest33-21ksoftirqd/221:00:172
29964995122,3cyclictest33-21ksoftirqd/222:50:272
29964995120,6cyclictest33-21ksoftirqd/220:15:202
138491510,1ptp4l401ktimersoftd/322:52:223
29964995019,4cyclictest33-21ksoftirqd/222:35:222
29964994923,7cyclictest33-21ksoftirqd/220:00:002
29964994822,7cyclictest33-21ksoftirqd/222:00:002
29964994822,3cyclictest33-21ksoftirqd/200:19:592
29964994817,4cyclictest33-21ksoftirqd/219:30:212
29964994718,3cyclictest33-21ksoftirqd/223:15:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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