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2026-02-24 - 06:53
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Tue Feb 24, 2026 00:45:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
22992207172,23sleep10-21swapper/119:07:471
25032204172,21sleep20-21swapper/219:09:572
24202203167,24sleep30-21swapper/319:08:543
21502198164,23sleep00-21swapper/019:06:050
1385918162,11phc2sys0-21swapper/319:10:013
95432600,5sleep19547-21unixbench_multi22:35:271
251252540,4sleep3280199cyclictest22:05:003
284702530,1sleep30-21swapper/321:05:193
280199473,41cyclictest7556-21cron21:30:003
316612460,2sleep20-21swapper/223:20:252
138491440,0ptp4l401ktimersoftd/323:10:043
2799994330,4cyclictest25-21ksoftirqd/123:55:001
138491430,0ptp4l401ktimersoftd/323:24:163
2800994235,5cyclictest33-21ksoftirqd/200:20:002
138491420,0ptp4l401ktimersoftd/321:30:593
138491420,0ptp4l401ktimersoftd/319:20:213
2801994134,4cyclictest27453-21cron00:20:013
2800994133,5cyclictest33-21ksoftirqd/221:02:522
2800993932,4cyclictest33-21ksoftirqd/223:29:402
2799993922,4cyclictest25-21ksoftirqd/120:20:281
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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