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2026-08-02 - 22:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Sun Aug 02, 2026 12:45:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
100742207173,22sleep30-21swapper/307:09:353
100322203169,22sleep10-21swapper/107:09:001
100432200168,21sleep20-21swapper/207:09:102
98732195162,22sleep00-21swapper/007:07:030
10401996327,4cyclictest9-21ksoftirqd/012:10:000
10401996232,4cyclictest9-21ksoftirqd/008:10:000
10401996132,4cyclictest9-21ksoftirqd/007:20:200
10401996130,6cyclictest9-21ksoftirqd/012:15:000
10401996126,3cyclictest9-21ksoftirqd/011:45:250
10401996122,7cyclictest9-21ksoftirqd/011:10:000
1040499603,16cyclictest0-21swapper/309:50:203
10401996027,5cyclictest9-21ksoftirqd/012:15:170
10401996026,7cyclictest9-21ksoftirqd/012:30:150
10401996024,4cyclictest9-21ksoftirqd/007:10:180
10401996021,5cyclictest9-21ksoftirqd/008:55:140
10401995931,3cyclictest9-21ksoftirqd/009:55:010
10401995928,4cyclictest9-21ksoftirqd/007:35:170
10401995926,5cyclictest9-21ksoftirqd/012:35:210
10401995924,6cyclictest9-21ksoftirqd/007:30:000
10401995922,6cyclictest9-21ksoftirqd/007:45:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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