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2026-03-03 - 01:24
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Mon Mar 02, 2026 12:45:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
262592204171,22sleep20-21swapper/207:07:482
263052202168,22sleep30-21swapper/307:08:253
261312202168,22sleep00-21swapper/007:06:090
261012199166,22sleep10-21swapper/107:05:461
181092590,2sleep20-21swapper/210:05:222
2672299589,11cyclictest3003-21grep11:45:231
119362570,2sleep20-21swapper/208:50:132
138491560,1ptp4l391rcuc/312:10:223
2672299546,16cyclictest20683-21ssh11:15:251
73122530,2sleep00-21swapper/010:50:140
138491530,1ptp4l391rcuc/311:18:013
2672299529,12cyclictest15711-21uptime12:10:281
2672299528,11cyclictest24647-21interrupts12:30:171
26723995019,11cyclictest33-21ksoftirqd/207:45:012
26723994919,7cyclictest33-21ksoftirqd/207:10:182
26723994919,4cyclictest33-21ksoftirqd/211:45:152
26723994819,6cyclictest33-21ksoftirqd/207:40:002
26723994730,3cyclictest33-21ksoftirqd/208:45:142
26723994723,7cyclictest33-21ksoftirqd/212:25:002
26723994718,4cyclictest33-21ksoftirqd/212:20:252
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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