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2026-03-09 - 07:24
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot4.osadl.org (updated Mon Mar 09, 2026 00:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
218122205171,22sleep30-21swapper/319:08:143
216232202167,23sleep10-21swapper/119:05:471
217172201168,22sleep20-21swapper/219:07:012
216272201167,22sleep00-21swapper/019:05:500
1385918363,11phc2sys0-21swapper/319:10:013
95892600,3sleep20-21swapper/219:50:002
95892600,3sleep20-21swapper/219:50:002
22240996013,11cyclictest11248-21grep19:50:242
22238996029,5cyclictest9-21ksoftirqd/023:25:210
22238996029,5cyclictest9-21ksoftirqd/019:50:150
22238996028,6cyclictest9-21ksoftirqd/019:55:260
22238996028,5cyclictest9-21ksoftirqd/000:00:140
22238995929,6cyclictest9-21ksoftirqd/021:05:180
22238995928,5cyclictest9-21ksoftirqd/021:30:240
22238995926,5cyclictest9-21ksoftirqd/023:10:150
139152590,5sleep02223899cyclictest22:05:260
22238995828,5cyclictest9-21ksoftirqd/021:40:130
22238995825,6cyclictest9-21ksoftirqd/021:35:150
22238995822,5cyclictest9-21ksoftirqd/019:30:170
22238995728,5cyclictest9-21ksoftirqd/020:00:370
22238995728,5cyclictest9-21ksoftirqd/019:50:010
22238995728,5cyclictest9-21ksoftirqd/019:50:000
22238995727,6cyclictest9-21ksoftirqd/021:25:150
22238995723,6cyclictest9-21ksoftirqd/022:20:230
22238995721,5cyclictest9-21ksoftirqd/022:40:240
22238995627,5cyclictest9-21ksoftirqd/021:15:000
22238995625,6cyclictest9-21ksoftirqd/020:30:000
22238995624,8cyclictest9-21ksoftirqd/019:25:250
22238995623,6cyclictest9-21ksoftirqd/022:55:010
22238995621,6cyclictest9-21ksoftirqd/000:20:010
22238995620,10cyclictest9-21ksoftirqd/019:15:210
2224199559,11cyclictest1319-21snmpd20:40:143
22238995524,5cyclictest9-21ksoftirqd/022:55:250
22238995524,5cyclictest9-21ksoftirqd/000:25:140
22238995521,6cyclictest9-21ksoftirqd/023:05:000
22238995420,6cyclictest9-21ksoftirqd/023:25:010
22238995420,5cyclictest9-21ksoftirqd/022:35:100
22238995420,5cyclictest9-21ksoftirqd/022:31:060
22238995327,5cyclictest9-21ksoftirqd/023:50:280
22238995321,7cyclictest9-21ksoftirqd/020:30:240
22238995321,5cyclictest9-21ksoftirqd/000:10:170
2223899530,6cyclictest9-21ksoftirqd/021:00:010
2223899523,5cyclictest9-21ksoftirqd/023:55:200
22240995114,12cyclictest31184-21gzip21:35:222
22238995120,5cyclictest9-21ksoftirqd/023:05:120
22238995110,5cyclictest9-21ksoftirqd/019:35:190
2223899509,5cyclictest9-21ksoftirqd/020:05:190
2223899506,6cyclictest9-21ksoftirqd/019:20:160
2223899505,5cyclictest9-21ksoftirqd/021:05:010
2223899504,5cyclictest9-21ksoftirqd/000:10:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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