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2026-07-28 - 22:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot4.osadl.org (updated Tue Jul 28, 2026 12:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
288592205170,23sleep30-21swapper/307:06:053
291062203170,22sleep00-21swapper/007:09:120
288312202169,22sleep20-21swapper/207:05:442
291652201167,23sleep10-21swapper/107:09:571
138591164124,14phc2sys0-21swapper/307:10:013
138591164124,14phc2sys0-21swapper/307:10:013
116212830,5sleep2223-21systemd-journal09:50:002
106352710,3sleep30-21swapper/308:40:253
29464997023,7cyclictest41-21ksoftirqd/311:52:073
224012650,4sleep2321ktimersoftd/210:10:182
20912580,6sleep12946299cyclictest09:30:131
29464995620,4cyclictest41-21ksoftirqd/311:50:003
29461995511,16cyclictest16718-21/usr/sbin/munin11:05:250
29461995511,16cyclictest16718-21/usr/sbin/munin11:05:250
29464995323,4cyclictest41-21ksoftirqd/311:15:143
307482520,4sleep230750-21needreboot07:10:212
307482520,4sleep230750-21needreboot07:10:212
2946199520,3cyclictest31294-21runrttasks10:29:100
201222520,2sleep30-21swapper/307:55:193
50772510,2sleep30-21swapper/309:35:203
138491510,0ptp4l401ktimersoftd/309:31:053
29464994917,5cyclictest41-21ksoftirqd/311:20:223
29464994917,4cyclictest41-21ksoftirqd/310:30:143
29464994913,8cyclictest41-21ksoftirqd/309:55:143
29464994818,4cyclictest41-21ksoftirqd/312:15:213
29464994816,4cyclictest41-21ksoftirqd/310:35:143
29464994716,8cyclictest41-21ksoftirqd/308:20:103
2946199478,17cyclictest1303-21runrttasks07:16:370
29464994619,7cyclictest41-21ksoftirqd/307:15:143
29464994617,4cyclictest41-21ksoftirqd/310:15:013
29464994617,4cyclictest41-21ksoftirqd/309:40:243
29464994611,8cyclictest41-21ksoftirqd/308:45:273
29464994538,4cyclictest41-21ksoftirqd/312:30:003
29464994525,17cyclictest41-21ksoftirqd/312:35:013
29464994525,17cyclictest41-21ksoftirqd/312:35:003
29464994519,6cyclictest41-21ksoftirqd/312:20:183
29464994514,4cyclictest41-21ksoftirqd/308:35:003
29464994513,4cyclictest41-21ksoftirqd/310:50:143
29464994429,12cyclictest41-21ksoftirqd/307:25:013
29464994416,7cyclictest41-21ksoftirqd/309:10:003
29464994415,7cyclictest41-21ksoftirqd/309:45:193
29464994414,8cyclictest41-21ksoftirqd/311:30:003
29464994413,4cyclictest41-21ksoftirqd/310:29:593
2946499440,3cyclictest121rcu_preempt12:00:253
29462994431,4cyclictest25-21ksoftirqd/111:52:071
29464994315,7cyclictest41-21ksoftirqd/310:55:263
29464994314,3cyclictest41-21ksoftirqd/311:30:143
29464994314,3cyclictest41-21ksoftirqd/311:10:173
29464994313,4cyclictest41-21ksoftirqd/312:00:003
29464994313,4cyclictest41-21ksoftirqd/312:00:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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