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2026-05-05 - 22:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot4.osadl.org (updated Tue May 05, 2026 12:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
262542225166,48sleep10-21swapper/107:07:111
242592204169,23sleep30-21swapper/307:05:083
261612203170,22sleep00-21swapper/007:05:580
261582202170,21sleep20-21swapper/207:05:562
688421550,7sleep12677299cyclictest08:40:021
2648028361,14sleep10-21swapper/107:10:011
2648028361,14sleep10-21swapper/107:10:011
138491650,1ptp4l401ktimersoftd/307:30:163
26774995833,3cyclictest41-21ksoftirqd/312:30:203
135191580,6getstats2677499cyclictest10:13:113
138491560,1ptp4l401ktimersoftd/309:26:033
26774995224,4cyclictest41-21ksoftirqd/312:10:203
26774995223,4cyclictest41-21ksoftirqd/311:00:233
26774995214,9cyclictest41-21ksoftirqd/311:50:213
307072510,1sleep20-21swapper/208:20:252
26774995031,3cyclictest41-21ksoftirqd/311:20:133
26774995021,4cyclictest41-21ksoftirqd/310:50:133
138491500,3ptp4l41-21ksoftirqd/307:10:173
138491500,3ptp4l41-21ksoftirqd/307:10:173
2677499498,8cyclictest41-21ksoftirqd/308:55:243
26774994930,3cyclictest41-21ksoftirqd/308:45:133
26774994921,3cyclictest41-21ksoftirqd/310:25:223
26774994920,3cyclictest41-21ksoftirqd/308:20:273
26774994918,4cyclictest41-21ksoftirqd/307:55:013
140642490,1sleep30-21swapper/308:55:003
59192480,1sleep10-21swapper/107:30:261
26774994819,3cyclictest41-21ksoftirqd/310:45:173
26774994818,3cyclictest41-21ksoftirqd/307:25:153
26774994811,8cyclictest41-21ksoftirqd/309:15:123
2677499478,7cyclictest41-21ksoftirqd/308:15:103
26774994719,3cyclictest41-21ksoftirqd/309:35:203
26774994717,4cyclictest41-21ksoftirqd/310:05:243
26774994715,4cyclictest41-21ksoftirqd/312:05:183
26774994620,6cyclictest41-21ksoftirqd/309:55:143
26774994617,7cyclictest41-21ksoftirqd/311:10:133
2677499461,3cyclictest41-21ksoftirqd/312:20:263
26774994610,8cyclictest41-21ksoftirqd/312:00:183
2677499457,10cyclictest41-21ksoftirqd/312:15:203
26774994534,3cyclictest41-21ksoftirqd/308:30:133
26774994519,6cyclictest41-21ksoftirqd/309:45:223
26774994518,3cyclictest41-21ksoftirqd/307:45:193
26774994517,4cyclictest41-21ksoftirqd/309:23:503
26774994514,4cyclictest41-21ksoftirqd/307:55:383
2677499451,3cyclictest121rcu_preempt10:30:163
26774994513,3cyclictest41-21ksoftirqd/311:30:133
26774994513,3cyclictest41-21ksoftirqd/311:30:133
2677499442,6cyclictest121rcu_preempt09:30:133
26774994422,4cyclictest41-21ksoftirqd/310:20:213
26774994418,7cyclictest41-21ksoftirqd/310:40:273
26774994417,7cyclictest41-21ksoftirqd/308:35:243
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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