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2026-02-22 - 02:02
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot4.osadl.org (updated Sat Feb 21, 2026 12:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
201072230163,21sleep00-21swapper/007:08:520
201102201168,22sleep30-21swapper/307:08:563
201092201167,23sleep20-21swapper/207:08:542
200162197164,22sleep10-21swapper/107:07:421
853621760,5sleep02049499cyclictest07:50:170
810321580,4sleep02049499cyclictest10:00:130
105912670,2sleep20-21swapper/210:05:132
136152660,5sleep125-21ksoftirqd/109:05:181
71112590,2sleep37115-21timerwakeupswit12:05:293
71112590,2sleep37115-21timerwakeupswit12:05:293
138491580,1ptp4l401ktimersoftd/311:55:123
138491570,1ptp4l401ktimersoftd/309:30:263
138491570,1ptp4l401ktimersoftd/309:30:253
138491530,1ptp4l391rcuc/309:18:493
138491510,0ptp4l401ktimersoftd/308:25:223
138491500,40ptp4l0-21swapper/307:10:013
138491470,1ptp4l0-21swapper/309:50:383
138491440,0ptp4l401ktimersoftd/310:40:053
138491440,0ptp4l401ktimersoftd/310:06:313
138491430,1ptp4l401ktimersoftd/308:31:253
138491430,0ptp4l401ktimersoftd/311:50:063
138491420,0ptp4l401ktimersoftd/311:35:263
138491420,0ptp4l401ktimersoftd/311:35:263
138491420,0ptp4l401ktimersoftd/308:19:553
221492390,1sleep10-21swapper/107:10:251
2049699390,37cyclictest0-21swapper/209:05:232
50798380,9rtkit-daemon0-21swapper/211:20:042
20496993832,4cyclictest33-21ksoftirqd/209:03:292
20497993730,4cyclictest41-21ksoftirqd/307:50:433
20497993729,5cyclictest41-21ksoftirqd/311:43:143
20496993731,4cyclictest33-21ksoftirqd/211:01:372
20496993730,4cyclictest33-21ksoftirqd/208:10:002
20495993730,4cyclictest25-21ksoftirqd/109:55:171
20494993730,4cyclictest9-21ksoftirqd/011:10:000
20494993730,4cyclictest15290-21cron10:15:010
20497993630,4cyclictest41-21ksoftirqd/310:26:563
20496993630,4cyclictest33-21ksoftirqd/210:40:392
20494993630,4cyclictest9-21ksoftirqd/007:29:010
20494993630,4cyclictest9-21ksoftirqd/007:23:290
20494993629,4cyclictest9-21ksoftirqd/012:32:500
138491360,1ptp4l401ktimersoftd/308:10:183
20497993529,4cyclictest41-21ksoftirqd/312:31:453
20497993529,4cyclictest41-21ksoftirqd/311:09:213
20496993530,3cyclictest33-21ksoftirqd/211:43:022
20496993530,3cyclictest33-21ksoftirqd/210:57:542
20496993528,4cyclictest33-21ksoftirqd/212:21:292
20495993529,4cyclictest25-21ksoftirqd/110:27:551
20494993529,4cyclictest9-21ksoftirqd/012:36:580
20494993529,4cyclictest9-21ksoftirqd/012:36:580
20494993529,4cyclictest9-21ksoftirqd/012:20:540
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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