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2025-11-16 - 06:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot4.osadl.org (updated Sun Nov 16, 2025 00:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
427791229166,51phc2sys0-21swapper/319:05:433
427791229166,51phc2sys0-21swapper/319:05:423
149762204170,22sleep20-21swapper/219:08:302
149762204170,22sleep20-21swapper/219:08:302
149132202167,23sleep10-21swapper/119:07:401
149132202167,23sleep10-21swapper/119:07:401
147812202168,22sleep00-21swapper/019:06:070
147812202168,22sleep00-21swapper/019:06:070
1660121390,6sleep11538699cyclictest19:10:251
427291700,0ptp4l391rcuc/319:32:323
427291650,1ptp4l401ktimersoftd/321:34:433
198272570,3sleep21538799cyclictest21:25:252
38612550,2sleep30-21swapper/319:50:183
427291490,1ptp4l401ktimersoftd/319:11:073
15387994833,12cyclictest971-21cron21:54:592
15387994530,12cyclictest33-21ksoftirqd/221:56:582
427291440,0ptp4l401ktimersoftd/300:30:373
427291430,0ptp4l401ktimersoftd/322:35:153
427291430,0ptp4l401ktimersoftd/322:04:473
427291430,0ptp4l401ktimersoftd/321:46:213
427591420,1getstats0-21swapper/319:44:233
427291420,0ptp4l401ktimersoftd/323:13:023
427291420,0ptp4l401ktimersoftd/322:55:283
427291420,0ptp4l401ktimersoftd/319:36:593
427291410,0ptp4l401ktimersoftd/322:20:053
15388994135,4cyclictest41-21ksoftirqd/320:45:153
1538899411,38cyclictest28044-21cron21:45:003
15388994034,3cyclictest41-21ksoftirqd/323:20:003
15388994032,5cyclictest41-21ksoftirqd/322:40:123
15385994034,4cyclictest9-21ksoftirqd/021:48:100
427291390,0ptp4l401ktimersoftd/322:10:143
15388993936,2cyclictest41-21ksoftirqd/321:25:013
15388993934,3cyclictest41-21ksoftirqd/321:20:003
15388993934,3cyclictest41-21ksoftirqd/321:10:193
15388993934,3cyclictest41-21ksoftirqd/320:05:013
15388993934,3cyclictest41-21ksoftirqd/319:15:293
15388993933,4cyclictest41-21ksoftirqd/320:11:373
15388993932,4cyclictest41-21ksoftirqd/322:17:343
15388993932,4cyclictest41-21ksoftirqd/300:05:163
15387993931,5cyclictest33-21ksoftirqd/200:15:142
15386993933,4cyclictest25-21ksoftirqd/123:35:381
15386993932,4cyclictest25-21ksoftirqd/122:41:231
15385993934,3cyclictest9-21ksoftirqd/022:30:000
15385993932,4cyclictest9-21ksoftirqd/023:14:030
15385993932,4cyclictest9-21ksoftirqd/021:58:040
15388993834,3cyclictest41-21ksoftirqd/321:25:133
15388993834,2cyclictest41-21ksoftirqd/300:30:003
15388993832,4cyclictest41-21ksoftirqd/321:01:143
15388993832,3cyclictest41-21ksoftirqd/323:40:003
15388993831,5cyclictest41-21ksoftirqd/323:59:263
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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