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2025-12-06 - 12:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Sat Dec 06, 2025 00:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
182977599109100,6cyclictest1886366-21kworker/u8:0+flush-179:022:20:000
18297779910396,5cyclictest1843948-21kworker/u8:0+events_unbound19:59:591
1829775999483,8cyclictest1917123-21/usr/sbin/munin23:40:240
1829777999281,9cyclictest1928324-21latency_hist00:15:011
1829775998978,9cyclictest1845826-21latency_hist20:00:010
1829777998580,4cyclictest1920304-21kworker/u8:1+events_unbound00:00:001
1829777998577,6cyclictest1863875-21kworker/u8:1+flush-179:021:00:001
1829775998575,8cyclictest271-21systemd-journal20:50:000
1829775998575,8cyclictest271-21systemd-journal20:50:000
1829777998478,4cyclictest1890943-21kworker/u8:3+flush-179:022:50:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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