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2026-05-21 - 14:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Thu May 21, 2026 00:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
12694999110100,7cyclictest131698-21latency_hist19:25:010
12694999110100,7cyclictest131698-21latency_hist19:25:000
1269509910293,6cyclictest154036-21latency_hist20:35:011
1269499910189,9cyclictest178187-21latency_hist21:50:010
126949999989,7cyclictest1213033-21systemd-journal20:25:000
126949999891,5cyclictest212138-21kworker/u8:2+flush-179:000:20:200
126949999891,5cyclictest212138-21kworker/u8:2+flush-179:000:20:190
126949999685,7cyclictest223618-21latency_hist00:10:000
126949998979,7cyclictest139656-21latency_hist19:50:000
126950998678,5cyclictest210556-21latency_hist23:30:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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