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2026-04-13 - 17:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Mon Apr 13, 2026 12:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11468199910394,7cyclictest1212506-21latency_hist10:35:001
1146815998878,7cyclictest1176969-21latency_hist08:45:000
1146819998778,7cyclictest1225241-21latency_hist11:15:021
1146815998369,11cyclictest266-21systemd-journal09:55:010
1146815998074,4cyclictest1175419-21kworker/u8:1+flush-179:009:55:250
1146815998074,4cyclictest1175419-21kworker/u8:1+flush-179:008:55:170
1146815997871,5cyclictest1241412-21kworker/u8:2+flush-179:012:15:220
1146815997771,4cyclictest1201409-21kworker/u8:0+flush-179:010:15:230
1146815997671,4cyclictest1220436-21kworker/u8:1+flush-179:011:00:220
1146815997669,5cyclictest1162640-21latency_hist08:00:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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