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2026-02-24 - 07:14
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Tue Feb 24, 2026 00:44:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
98150899116108,5cyclictest1074998-21kworker/u8:2+flush-179:000:00:011
981506998071,7cyclictest1049600-21latency_hist22:40:010
981506997670,4cyclictest1059098-21kworker/u8:0+events_unbound00:04:020
981508997365,5cyclictest991250-21kworker/u8:3+flush-179:019:45:001
981506997366,5cyclictest1051553-21kworker/u8:0+flush-179:023:00:010
981506997265,5cyclictest986176-21latency_hist19:25:020
981508997157,13cyclictest1060737-21kworker/u8:2+flush-179:023:30:001
981508996960,6cyclictest1075115-21kworker/u8:3+events_unbound00:00:031
981506996961,6cyclictest1001006-21latency_hist20:10:010
981506996961,5cyclictest997824-21latency_hist20:00:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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