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2025-12-05 - 10:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Fri Dec 05, 2025 00:44:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
32377759910898,7cyclictest3269576-21kworker/u8:3+flush-179:021:00:000
3237779999993,4cyclictest3340943-21kworker/u8:0+events_unbound00:30:291
3237775999794,2cyclictest3311674-21kworker/u8:0+flush-179:023:05:000
3237775999786,7cyclictest3284380-21latency_hist21:35:010
3237775999588,4cyclictest3298932-21kworker/u8:4+flush-179:022:30:010
3237779999489,4cyclictest3306965-21kworker/u8:2+events_unbound23:00:001
3237775999486,6cyclictest3328159-21kworker/u8:2+flush-179:000:00:010
3237775999384,7cyclictest3286004-21latency_hist21:40:010
3237779999187,3cyclictest3317260-21kworker/u8:0+events_unbound23:15:251
3237779999079,9cyclictest3323480-21cp23:35:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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