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2025-12-15 - 12:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Mon Dec 15, 2025 00:44:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2863597998480,3cyclictest2876255-21kworker/u8:3+events_unbound20:15:250
2863597997975,3cyclictest2955222-21kworker/u8:0+events_unbound00:10:250
2863597997975,3cyclictest2896652-21kworker/u8:2+events_unbound20:55:240
2863597997971,3cyclictest2946833-21kworker/u8:0+events_unbound23:35:250
2863597997470,3cyclictest2866639-21kworker/u8:1+events_unbound19:45:260
2863600997364,6cyclictest2879674-21latency_hist20:00:021
2863600997263,7cyclictest2873048-21latency_hist19:40:021
2863597997265,6cyclictest2966017-21kworker/u8:3+events_unbound00:35:300
2863597997263,4cyclictest2956457-21kworker/u8:2+events_unbound00:05:220
2863597997166,4cyclictest2911559-21kworker/u8:2+events_unbound22:05:400
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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