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2026-01-19 - 04:28
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Mon Jan 19, 2026 00:44:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
897046999865,22cyclictest913147-21latency_hist20:00:001
897045999486,6cyclictest957989-21latency_hist22:20:020
897045999082,6cyclictest940528-21kworker/u8:3+events_unbound22:25:000
897045999082,6cyclictest940528-21kworker/u8:3+events_unbound22:25:000
897045998780,4cyclictest942067-21latency_hist21:30:010
897046998660,23cyclictest937523-21/usr/sbin/munin21:15:241
897045998675,9cyclictest990594-40logrotate00:00:000
897046998575,8cyclictest266-21systemd-journal19:20:021
897045997668,6cyclictest906793-21latency_hist19:40:010
897045997467,5cyclictest1000500-21kworker/u8:0+flush-179:000:40:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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