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2026-02-23 - 03:49
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Mon Feb 23, 2026 00:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
23714279910397,4cyclictest2423094-21kworker/u8:1+flush-179:022:45:000
2371427999180,8cyclictest2435799-21latency_hist22:30:000
2371427999084,4cyclictest2398643-21kworker/u8:1+events_unbound20:35:000
2371427998881,5cyclictest2423094-21kworker/u8:1+events_unbound22:35:230
2371427998783,3cyclictest2385379-21kworker/u8:0+flush-179:021:25:010
2371427998678,6cyclictest266-21systemd-journal00:04:000
2371427998672,4cyclictest2460439-21kworker/u8:1+events_unbound23:45:000
2371430998578,5cyclictest2423094-21kworker/u8:1+events_unbound23:15:021
2371427998582,2cyclictest2415094-21kworker/u8:3+events_unbound21:35:000
2371427998468,4cyclictest2464340-21kworker/u8:0+events_unbound00:20:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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