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2026-02-09 - 09:51
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Mon Feb 09, 2026 00:44:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9466359910593,9cyclictest946411-21latency_hist19:10:031
946635999076,11cyclictest1048104-21latency_hist00:25:011
946630998778,7cyclictest1030529-21latency_hist23:30:000
946630998778,7cyclictest1004825-21kworker/u8:2+flush-179:022:50:250
946635998471,9cyclictest1040068-40logrotate00:00:001
946630998477,5cyclictest995492-21kworker/u8:3+flush-179:022:00:310
946630998477,5cyclictest1004825-21kworker/u8:2+flush-179:022:30:240
946630998475,6cyclictest990474-21latency_hist21:25:000
946630998274,6cyclictest974542-21latency_hist20:35:010
946630998175,4cyclictest1014588-21kworker/u8:0+events_unbound00:10:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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