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2026-09-04 - 02:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Thu Sep 03, 2026 12:44:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
148745999145134,8cyclictest1586569-21latency_hist12:15:000
148745999137126,8cyclictest1501963-21latency_hist07:55:010
148745999134121,9cyclictest1506803-21kworker/u8:0+flush-179:008:15:010
148746099132122,4cyclictest1584975-21kworker/u8:1+events_unbound12:10:211
148746099129123,5cyclictest1562243-21kworker/u8:2+events_unbound11:15:231
148746099128116,10cyclictest1213033-21systemd-journal12:25:001
148745999128120,5cyclictest1562243-21kworker/u8:2+events_unbound11:25:250
148745999128118,7cyclictest1506803-21kworker/u8:0+flush-179:008:15:210
148746099127122,4cyclictest1489173-21kworker/u8:0+events_unbound07:20:241
148746099126117,7cyclictest1552100-21kworker/u8:3+flush-179:011:10:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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