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2026-02-23 - 18:11
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Mon Feb 23, 2026 12:44:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
37692049910898,7cyclictest3880887-21latency_hist12:40:011
37692039910378,7cyclictest3843916-21latency_hist11:00:010
3769204999989,7cyclictest3835162-21latency_hist10:35:011
3769203999686,8cyclictest3848686-21apt-get11:15:030
3769203999588,5cyclictest3781857-21apt-get07:50:040
3769204999181,8cyclictest3769331-21/usr/sbin/munin07:10:241
3769203998980,7cyclictest3835169-21apt-get10:35:000
3769203998676,8cyclictest3863607-21/usr/sbin/munin11:45:230
3769203998476,6cyclictest3872903-21latency_hist12:15:010
3769203998272,8cyclictest3801453-21/usr/sbin/munin08:50:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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