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2025-12-01 - 07:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Mon Dec 01, 2025 00:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4037039910493,8cyclictest477904-21latency_hist23:00:010
403703999685,4cyclictest398571-21kworker/u8:1+events_unbound19:25:230
403707999589,5cyclictest482284-21kworker/u8:1+flush-179:000:04:021
403707999589,5cyclictest482284-21kworker/u8:1+flush-179:000:04:011
403703999487,5cyclictest398571-21kworker/u8:1+events_unbound19:45:220
403707999185,4cyclictest402136-21kworker/u8:0+flush-179:019:20:001
403707998573,8cyclictest445799-21latency_hist21:20:001
403703998277,4cyclictest428276-21kworker/u8:3+flush-179:020:25:250
403703998268,4cyclictest482284-21kworker/u8:1+events_unbound23:40:010
403707998170,4cyclictest428276-21kworker/u8:3+events_unbound20:40:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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