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2026-01-21 - 13:02
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Wed Jan 21, 2026 00:44:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
23080339910190,8cyclictest266-21systemd-journal21:00:001
2308033999885,10cyclictest2390671-21latency_hist23:25:001
2308029999282,8cyclictest266-21systemd-journal19:25:010
2308033999078,9cyclictest2345056-21latency_hist21:05:011
2308033998882,4cyclictest2392495-21kworker/u8:1+flush-179:000:04:011
2308029998477,5cyclictest2392521-21kworker/u8:3+flush-179:023:55:240
2308029998372,8cyclictest266-21systemd-journal19:10:180
2308029998275,5cyclictest2366265-21latency_hist22:10:020
2308029998169,10cyclictest2319334-21apt-get19:45:000
2308029997769,6cyclictest2394104-21latency_hist23:35:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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