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2026-01-18 - 10:03
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Sun Jan 18, 2026 00:44:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2313988999586,6cyclictest2345980-21latency_hist20:50:001
2313986999083,4cyclictest2328699-21kworker/u8:2+flush-179:020:20:000
2313986998879,7cyclictest2396111-21kworker/u8:0+flush-179:023:40:000
2313988998778,7cyclictest2346216-21/usr/sbin/munin20:50:231
2313986998678,6cyclictest2384948-21kworker/u8:0+events_unbound23:10:000
2313988998461,20cyclictest2415824-21latency_hist00:35:001
2313988998072,5cyclictest2307844-21kworker/u8:1+events_unbound19:20:011
2313986998071,7cyclictest2351044-21kworker/u8:2+flush-179:021:20:010
2313986998071,6cyclictest2339646-21kworker/u8:1+flush-179:020:50:150
2313988997965,11cyclictest2383139-21apt-get22:50:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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