You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-24 - 22:24
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Tue Feb 24, 2026 12:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
238105999112104,6cyclictest2488182-21latency_hist12:40:021
2381059999589,5cyclictest2459465-21kworker/u8:0+flush-179:011:25:001
2381059999181,8cyclictest2387490-21kworker/u8:1+flush-179:007:45:011
2381057999175,12cyclictest266-21systemd-journal07:25:010
2381059998980,7cyclictest2471997-21kworker/u8:1+flush-179:012:20:011
2381057998875,10cyclictest266-21systemd-journal11:50:010
2381059998467,12cyclictest266-21systemd-journal08:25:011
238105999820,80cyclictest1-21systemd08:15:001
2381059998175,4cyclictest2438588-21kworker/u8:1+flush-179:010:15:221
2381059998172,7cyclictest2435099-21latency_hist09:55:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional