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2026-02-06 - 06:43
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Thu Feb 05, 2026 00:44:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
23180799910581,22cyclictest2322872-21latency_hist19:25:011
2318074999280,10cyclictest2387302-21latency_hist22:45:000
2318079998879,6cyclictest2424516-21latency_hist00:40:011
2318079998570,11cyclictest2356289-21latency_hist21:10:011
2318079998172,6cyclictest2338773-21latency_hist20:15:011
2318079998162,18cyclictest2401912-21kworker/u8:2+flush-179:000:05:001
2318079997871,5cyclictest2359746-21latency_hist21:20:011
2318079997858,18cyclictest2368586-21kworker/u8:0+events_unbound22:40:011
2318074997767,7cyclictest2375562-21kworker/u8:2+events_unbound22:15:180
2318079997670,4cyclictest2311560-21kworker/u8:3+events_unbound19:15:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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