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2026-07-23 - 17:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Thu Jul 23, 2026 12:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
73196399152142,7cyclictest744683-21kworker/u8:1+events_unbound07:55:001
73196399140131,7cyclictest768849-21kworker/u8:0+events_unbound09:10:001
73196199140128,9cyclictest739816-21latency_hist07:35:010
73196399139132,6cyclictest765646-21kworker/u8:3+events_unbound09:15:011
73196399129120,6cyclictest798007-21kworker/u8:2+events_unbound10:45:161
73196399128121,5cyclictest748899-21kworker/u8:0+flush-179:008:10:011
73196399128121,5cyclictest748899-21kworker/u8:0+flush-179:008:10:011
73196399128116,8cyclictest836249-21latency_hist12:35:011
7319619912896,21cyclictest829873-21latency_hist12:15:010
73196399126116,7cyclictest823506-21latency_hist11:55:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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