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2025-12-24 - 14:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Wed Dec 24, 2025 00:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3146197999684,9cyclictest3245819-21latency_hist00:20:011
3146193999687,6cyclictest3226137-21latency_hist23:20:010
3146197999485,6cyclictest3227776-21kworker/u8:0+flush-179:023:30:241
3146193999384,6cyclictest3216582-21latency_hist22:50:000
3146197999284,6cyclictest3155576-21kworker/u8:3+flush-179:020:19:591
3146193999081,7cyclictest3247654-21latency_hist00:25:010
3146193999081,7cyclictest3205439-21latency_hist22:15:010
3146197998878,7cyclictest3216617-21kworker/u8:2+flush-179:023:05:221
3146197998575,7cyclictest3229309-21latency_hist23:30:001
3146197998575,7cyclictest3229309-21latency_hist23:30:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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