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2026-01-15 - 23:57
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Thu Jan 15, 2026 12:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
36561809910797,8cyclictest3727753-21latency_hist10:50:010
3656184999282,7cyclictest3753488-21latency_hist12:10:021
3656180999282,7cyclictest3732539-21latency_hist11:05:010
3656180999080,7cyclictest3712652-21latency_hist10:05:020
3656180999077,9cyclictest266-21systemd-journal09:15:010
3656180998780,5cyclictest3720460-21kworker/u8:1+events_unbound10:40:240
3656180998777,8cyclictest3742319-21/usr/sbin/munin11:35:220
3656180998680,5cyclictest3651580-21kworker/u8:0+events_unbound07:20:240
3656180998678,5cyclictest3662485-21kworker/u8:3+flush-179:007:45:000
3656180998479,4cyclictest3643168-21kworker/u8:2+flush-179:007:50:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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