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2026-01-17 - 22:04
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Sat Jan 17, 2026 12:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
89903199118108,7cyclictest981305-21latency_hist11:20:021
89903199118108,7cyclictest981305-21latency_hist11:20:011
8990289910696,8cyclictest944103-21latency_hist09:25:010
8990289910090,7cyclictest922634-21latency_hist08:20:010
899028999688,5cyclictest962675-21kworker/u8:0+flush-179:011:05:000
899031999585,7cyclictest961619-21latency_hist10:20:011
899031999483,8cyclictest900754-21/usr/sbin/munin07:15:231
899031999483,8cyclictest900754-21/usr/sbin/munin07:15:231
899028999285,6cyclictest912321-21kworker/u8:1+flush-179:008:00:000
899031998673,10cyclictest939075-21apt-get09:09:591
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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