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2026-03-28 - 20:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Sat Mar 28, 2026 12:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3233085999384,7cyclictest3234616-21latency_hist07:15:020
3233086999183,6cyclictest3328574-21latency_hist12:05:011
3233085998979,7cyclictest3267065-21latency_hist08:55:000
3233086998471,10cyclictest3320091-21latency_hist11:40:011
3233086998274,6cyclictest3241285-21kworker/u8:1+events_unbound08:20:241
3233086998175,4cyclictest3299116-21kworker/u8:0+events_unbound10:35:001
3233086998066,11cyclictest3305546-21kworker/u8:3+events_unbound11:05:011
3233085997971,6cyclictest3244540-21latency_hist07:45:010
3233086997869,7cyclictest3294120-21latency_hist10:20:011
3233085997567,6cyclictest3336525-21latency_hist12:30:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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