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2025-12-09 - 07:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Tue Dec 09, 2025 00:44:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17760689910993,14cyclictest1813052-21kworker/u8:0+flush-179:022:00:001
1776068999490,3cyclictest1795341-21kworker/u8:2+events_unbound20:10:241
1776065999489,4cyclictest1869563-21kworker/u8:0+events_unbound00:04:020
1776065999381,5cyclictest1829898-21kworker/u8:2+events_unbound22:05:010
1776065999285,5cyclictest1851608-21kworker/u8:3+events_unbound23:15:020
1776065999086,3cyclictest1821272-21kworker/u8:1+flush-179:021:40:250
1776065999084,5cyclictest1805087-21kworker/u8:1+events_unbound20:45:010
1776065998979,7cyclictest1869577-40logrotate00:00:010
1776068998879,3cyclictest1835684-21kworker/u8:1+events_unbound22:25:251
1776068998574,4cyclictest1808530-21kworker/u8:2+events_unbound20:55:301
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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