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2026-07-16 - 16:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Thu Jul 16, 2026 12:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
269952399153142,7cyclictest2750941-21latency_hist09:50:011
269952399131122,7cyclictest2761806-21kworker/u8:1+events_unbound10:30:001
269952399129122,5cyclictest2738206-21kworker/u8:1+flush-179:009:14:591
269952399122116,4cyclictest2697862-21kworker/u8:2+events_unbound07:10:251
269952399121116,3cyclictest2697862-21kworker/u8:2+flush-179:007:20:251
269952399116110,4cyclictest2786254-21kworker/u8:1+events_unbound12:10:261
269952199115106,6cyclictest2718852-21latency_hist08:10:010
269952399114106,5cyclictest2766822-21kworker/u8:2+flush-179:010:40:201
269952399113104,6cyclictest2799243-21kworker/u8:2+flush-179:012:20:181
269952399112102,7cyclictest2726789-21kworker/u8:0+events_unbound09:05:201
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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