You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-20 - 04:48
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Tue Jan 20, 2026 00:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
368777299125115,8cyclictest3713762-21latency_hist20:30:001
3687769999587,5cyclictest3781366-21kworker/u8:1+flush-179:000:04:010
3687769999487,5cyclictest3717261-21kworker/u8:2+flush-179:021:00:010
3687769999178,11cyclictest3782947-21apt-get00:00:010
3687769998976,10cyclictest266-21systemd-journal22:45:010
3687769998976,10cyclictest266-21systemd-journal22:45:010
3687769998780,6cyclictest3758785-21kworker/u8:3+flush-179:023:00:000
3687769998679,4cyclictest3776812-21kworker/u8:3+events_unbound23:55:010
3687772998465,16cyclictest3713634-21kworker/u8:1+flush-179:021:25:001
3687769998478,4cyclictest3717261-21kworker/u8:2+flush-179:020:45:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional