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2025-12-12 - 10:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Fri Dec 12, 2025 00:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
16802779910392,8cyclictest1690123-21latency_hist19:40:011
1680272999689,5cyclictest1756924-21kworker/u8:2+flush-179:023:25:260
1680272999386,5cyclictest1738862-21kworker/u8:3+flush-179:022:20:000
1680272999386,5cyclictest1738862-21kworker/u8:3+flush-179:022:20:000
1680277998675,8cyclictest1750575-21latency_hist22:45:001
1680272998472,10cyclictest1685191-21cp19:25:010
1680272998472,10cyclictest1685191-21cp19:25:010
1680277998271,8cyclictest1761981-21latency_hist23:20:011
1680277998172,7cyclictest1779787-21kworker/u8:0+flush-179:000:20:011
1680277998069,8cyclictest1701245-21latency_hist20:15:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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