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2026-01-15 - 09:57
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Thu Jan 15, 2026 00:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
22286339910291,9cyclictest2288244-21latency_hist22:15:000
22286369910191,8cyclictest2296205-21latency_hist22:40:011
2228633999860,25cyclictest2248427-21/usr/sbin/munin20:10:250
2228636999383,8cyclictest2293027-21latency_hist22:30:011
2228633998778,7cyclictest2228538-21latency_hist19:10:020
2228636998463,19cyclictest2321989-40mandb00:00:001
2228633998475,7cyclictest2268879-21latency_hist21:15:010
2228633998273,7cyclictest2280291-21latency_hist21:50:010
2228633998273,6cyclictest2234931-21latency_hist19:30:000
2228633998071,7cyclictest2244745-21latency_hist20:00:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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