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2026-02-15 - 14:50
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Sun Feb 15, 2026 00:44:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
915630999990,7cyclictest978931-21latency_hist22:25:010
915630999990,7cyclictest978931-21latency_hist22:25:000
915633999582,10cyclictest266-21systemd-journal00:10:001
915633999479,13cyclictest1012697-21kworker/u8:2+flush-179:000:35:001
915630999481,9cyclictest968801-21latency_hist21:55:010
915633998879,8cyclictest266-21systemd-journal21:20:001
915633998667,18cyclictest1012697-21kworker/u8:2+flush-179:000:15:001
915630998678,6cyclictest993246-21latency_hist23:10:010
915630998477,5cyclictest928546-21kworker/u8:0+flush-179:020:15:000
915633997969,8cyclictest968806-21apt-get21:55:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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