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2026-02-10 - 11:04
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Tue Feb 10, 2026 00:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
373940699117105,9cyclictest3784437-21latency_hist21:30:001
37394029910594,8cyclictest3768323-21kworker/u8:3+events_unbound21:40:000
37394029910193,5cyclictest3744189-21kworker/u8:2+events_unbound19:55:000
3739402999485,7cyclictest3756215-21kworker/u8:1+events_unbound20:15:000
3739402999083,4cyclictest3776263-21kworker/u8:0+events_unbound21:05:520
3739406998984,4cyclictest3768323-21kworker/u8:3+events_unbound21:40:251
3739406998783,3cyclictest3805153-21kworker/u8:3+events_unbound22:45:241
3739402998670,5cyclictest3737807-21kworker/u8:0+events_unbound19:45:170
373940299840,81cyclictest1-21systemd21:00:240
3739406998379,3cyclictest3802936-21kworker/u8:2+events_unbound22:30:251
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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