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2026-05-01 - 00:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Thu Apr 30, 2026 12:44:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
213278299143115,24cyclictest1213033-21systemd-journal10:44:221
213277999116106,8cyclictest510-21rs:main0
2132782999979,4cyclictest2166946-21kworker/u8:2+flush-179:010:17:191
2132779999588,4cyclictest2134464-21latency_hist07:15:010
2132782999282,7cyclictest2191034-21latency_hist10:15:011
2132779999061,23cyclictest492-21polkitd10:44:220
2132782998676,7cyclictest2237201-21latency_hist12:35:001
2132782998578,5cyclictest2166946-21kworker/u8:2+flush-179:009:50:011
2132779998577,6cyclictest2203701-21latency_hist10:50:010
2132782998478,4cyclictest2210682-21kworker/u8:3+flush-179:011:20:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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