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2026-01-22 - 13:56
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Thu Jan 22, 2026 00:44:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
92078499112104,5cyclictest941674-21kworker/u8:3+flush-179:020:40:010
9207899910894,11cyclictest1024154-21latency_hist00:30:011
920784999790,5cyclictest1012680-21kworker/u8:3+flush-179:000:10:010
920784999082,5cyclictest925462-21kworker/u8:3+events_unbound19:25:000
920784998981,5cyclictest961040-21kworker/u8:3+events_unbound21:20:010
920784998881,4cyclictest917131-21kworker/u8:1+events_unbound19:10:230
920784998778,6cyclictest998150-21kworker/u8:3+flush-179:023:15:210
920784998776,8cyclictest932146-21kworker/u8:1+flush-179:020:10:200
920789998676,7cyclictest990403-21kworker/u8:0+flush-179:023:00:001
920794998555,1cyclictest0-21swapper/321:51:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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