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2026-01-20 - 17:02
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Tue Jan 20, 2026 12:44:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
901660999687,6cyclictest935655-21apt-get08:55:000
901660999684,9cyclictest927699-21latency_hist08:30:010
901660999682,10cyclictest904778-21apt-get07:20:000
901664999483,8cyclictest932478-21latency_hist08:45:001
901664999387,4cyclictest916516-21apt-get07:54:181
901664998980,7cyclictest961074-21latency_hist10:10:011
901660998161,17cyclictest1007967-21/usr/sbin/munin12:35:220
901664997974,4cyclictest944435-21kworker/u8:3+events_unbound09:50:001
901664997868,8cyclictest954687-21/usr/sbin/munin09:50:251
901660997670,4cyclictest940392-21kworker/u8:0+flush-179:009:15:160
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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