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2025-12-29 - 03:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Mon Dec 29, 2025 00:44:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
5287339910382,6cyclictest598704-21kworker/u8:1+events_unbound23:00:020
528736999873,21cyclictest614635-21latency_hist23:35:021
528733998979,7cyclictest590443-21latency_hist22:20:010
528736998881,5cyclictest575832-21/usr/sbin/munin21:35:241
528733998578,5cyclictest608191-21kworker/u8:0+flush-179:023:35:020
528733998576,7cyclictest538232-21kworker/u8:1+events_unbound20:10:000
528733998576,7cyclictest538232-21kworker/u8:1+events_unbound20:09:590
52873399850,84cyclictest1-21systemd20:50:010
528733998479,4cyclictest580617-21kworker/u8:2+flush-179:022:00:000
528733998478,5cyclictest536578-21kworker/u8:2+flush-179:019:35:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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