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2026-02-03 - 06:40
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Tue Feb 03, 2026 00:44:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9314629910595,7cyclictest1028757-21latency_hist00:10:021
9314629910191,7cyclictest974360-21kworker/u8:1+flush-179:021:40:001
931460999587,5cyclictest952588-21kworker/u8:1+flush-179:020:20:000
931462998977,9cyclictest938217-21cat19:30:011
931462998774,10cyclictest1025550-40mandb00:00:011
931460998375,6cyclictest1017048-21apt-get23:35:000
931460997867,8cyclictest1002977-21apt-get22:50:120
931460997769,6cyclictest984696-21latency_hist21:55:010
931462997463,9cyclictest266-21systemd-journal23:35:001
931460997262,8cyclictest991572-21apt-get22:15:110
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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