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2026-05-03 - 03:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Sun May 03, 2026 00:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
66970199148137,8cyclictest1213033-21systemd-journal00:04:011
66970199112104,5cyclictest680742-21latency_hist19:45:011
6697019910390,10cyclictest695324-21latency_hist20:30:001
6696999910297,4cyclictest752906-21kworker/u8:1+flush-179:000:04:000
6696999910293,7cyclictest733247-21latency_hist22:25:010
669701999585,8cyclictest756047-21latency_hist23:35:011
669701999585,7cyclictest764064-21kworker/u8:0+flush-179:000:15:021
669701999487,5cyclictest671164-21kworker/u8:1+flush-179:019:30:011
669701999387,4cyclictest764084-21kworker/u8:3+flush-179:000:20:171
669699999383,7cyclictest770728-21latency_hist00:20:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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