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2026-01-16 - 07:36
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Fri Jan 16, 2026 00:44:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
8830409911591,21cyclictest977151-40logrotate00:00:001
8830409910090,7cyclictest884579-21latency_hist19:15:011
883035999788,7cyclictest931804-21latency_hist21:40:010
883040999685,8cyclictest907400-21latency_hist20:25:011
883040999477,15cyclictest924063-21kworker/u8:0+flush-179:021:40:001
883040999384,7cyclictest935217-21kworker/u8:1+events_unbound22:25:021
883040999184,5cyclictest892539-21apt-get19:40:021
883035999081,7cyclictest967348-21latency_hist23:30:010
883040998072,6cyclictest889361-21latency_hist19:30:011
883040998069,8cyclictest923571-21latency_hist21:15:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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