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2026-02-19 - 19:20
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Thu Feb 19, 2026 12:44:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
96662699127103,21cyclictest1008271-21latency_hist09:20:021
9666249910790,13cyclictest266-21systemd-journal07:20:010
966626999888,7cyclictest1019655-21latency_hist09:55:021
966624999790,5cyclictest996477-21kworker/u8:1+events_unbound09:05:240
966624999687,7cyclictest1005110-21kworker/u8:2+events_unbound09:35:000
966624999583,9cyclictest964984-21kworker/u8:2+flush-179:007:30:000
966624999285,5cyclictest1031058-21kworker/u8:2+flush-179:010:40:000
966624998569,5cyclictest1018104-21kworker/u8:3+events_unbound10:45:000
966624998569,5cyclictest1018104-21kworker/u8:3+events_unbound10:45:000
966624998475,7cyclictest1037930-21/usr/sbin/munin10:50:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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