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2026-01-24 - 04:12
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Sat Jan 24, 2026 00:44:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
232487899109101,6cyclictest2352078-21kworker/u8:1+events_unbound20:35:000
23248789910393,7cyclictest266-21systemd-journal21:55:000
2324878999181,7cyclictest2401734-21kworker/u8:0+events_unbound23:20:010
2324878999080,7cyclictest2345471-21latency_hist20:15:000
2324878998874,11cyclictest266-21systemd-journal00:04:010
2324878998681,4cyclictest2324805-21kworker/u8:2+flush-179:019:49:540
2324878998676,7cyclictest2342302-21latency_hist20:05:020
2324878998576,7cyclictest2366479-21kworker/u8:3+events_unbound22:20:010
2324879998475,6cyclictest2329572-21latency_hist19:25:011
2324879998172,6cyclictest2417878-21kworker/u8:3+flush-179:000:00:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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