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2026-02-07 - 08:19
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Sat Feb 07, 2026 00:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
375345399127116,8cyclictest1049265-21cups-browsed00:00:000
37534539910394,6cyclictest3849066-21cat00:10:000
3753453999974,22cyclictest3783859-21latency_hist20:45:010
3753455999587,6cyclictest3774293-21latency_hist20:15:011
3753455999472,20cyclictest3834785-21apt-get23:25:111
3753453999286,4cyclictest3772741-21kworker/u8:2+events_unbound21:30:010
3753455998465,16cyclictest3844068-21latency_hist23:55:011
3753455998173,6cyclictest3785446-21latency_hist20:50:011
3753453998172,7cyclictest3810930-21apt-get22:10:010
3753453998071,7cyclictest3769258-21latency_hist20:00:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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