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2026-04-30 - 00:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Wed Apr 29, 2026 12:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
35993859910798,7cyclictest3683163-21latency_hist11:30:000
35993859910596,7cyclictest3634597-21latency_hist09:00:010
35993859910596,7cyclictest3634597-21latency_hist09:00:010
35993899910296,4cyclictest3593203-21kworker/u8:0+events_unbound07:20:011
35993859910088,9cyclictest1213033-21systemd-journal09:55:000
3599385999588,5cyclictest3670192-21kworker/u8:0+flush-179:010:50:260
3599385999588,5cyclictest3670192-21kworker/u8:0+flush-179:010:50:250
3599385998777,7cyclictest3657386-21latency_hist10:10:010
3599385998777,7cyclictest3657386-21latency_hist10:10:010
3599389998678,6cyclictest3627973-21latency_hist08:40:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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