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2026-05-05 - 19:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Tue May 05, 2026 12:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
338741599114104,8cyclictest3436225-21kworker/u8:0+events_unbound10:00:000
33874159910297,4cyclictest3416642-21kworker/u8:0+events_unbound08:40:000
33874159910293,6cyclictest1213033-21systemd-journal09:55:000
33874159910287,6cyclictest3449813-21kworker/u8:1+events_unbound10:55:010
33874159910088,6cyclictest3395775-21kworker/u8:3+events_unbound08:09:590
3387415999483,9cyclictest3483498-21kworker/u8:3+flush-179:012:40:000
3387415999480,11cyclictest1213033-21systemd-journal11:00:010
3387419999384,7cyclictest3437822-21latency_hist09:50:011
3387419999274,14cyclictest3448157-21kworker/u8:2+flush-179:011:55:011
3387415998882,4cyclictest3408621-21kworker/u8:0+events_unbound08:15:150
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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