You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2025-12-17 - 09:12
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Wed Dec 17, 2025 00:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
151346999687,4cyclictest245173-21kworker/u8:1+events_unbound00:04:011
151342999284,6cyclictest188186-21latency_hist21:05:010
151342999284,6cyclictest188186-21latency_hist21:05:010
151342998881,4cyclictest203074-21kworker/u8:2+flush-179:022:20:250
151342998866,13cyclictest243584-21kworker/u8:2+flush-179:000:15:190
151342998272,8cyclictest175401-21apt-get20:22:060
151346998171,3cyclictest192918-21kworker/u8:0+events_unbound21:20:251
151342998172,7cyclictest233807-21latency_hist23:25:010
151342998171,7cyclictest245258-21kworker/u8:3+flush-179:000:00:210
151346998067,4cyclictest214830-21kworker/u8:4+events_unbound22:35:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional