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2026-05-03 - 19:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Sun May 03, 2026 12:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
205907099115107,6cyclictest2136157-21kworker/u8:1+events_unbound12:10:000
205907099110102,6cyclictest2112302-21latency_hist09:55:000
205907099108102,4cyclictest2114667-21kworker/u8:0+events_unbound10:20:000
20590709910696,7cyclictest2104348-21latency_hist09:30:000
2059070999993,4cyclictest2098944-21kworker/u8:1+flush-179:009:25:020
2059073999660,26cyclictest2074925-21latency_hist08:00:001
2059070999287,4cyclictest2136157-21kworker/u8:1+events_unbound12:00:000
2059070999182,6cyclictest2143425-21kworker/u8:2+flush-179:011:45:000
2059070998777,7cyclictest2079664-21kworker/u8:0+flush-179:008:30:150
2059073998471,9cyclictest2105920-21kworker/u8:3+flush-179:009:50:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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