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2026-05-06 - 19:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Wed May 06, 2026 12:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1956189999585,7cyclictest2031667-21kworker/u8:2+flush-179:011:00:230
1956189999283,6cyclictest2030666-21latency_hist11:00:000
1956193999180,8cyclictest2050057-21latency_hist12:00:021
1956189999180,7cyclictest2008117-21latency_hist09:50:010
1956193998880,5cyclictest2031667-21kworker/u8:2+flush-179:012:25:001
1956189998475,6cyclictest2016329-21latency_hist10:15:010
1956193998376,5cyclictest1960920-21kworker/u8:3+flush-179:008:05:001
1956189998368,10cyclictest2040253-21kworker/u8:3+flush-179:011:40:000
1956193998276,4cyclictest2025885-21kworker/u8:1+flush-179:010:55:241
1956193998175,4cyclictest2031667-21kworker/u8:2+flush-179:012:00:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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