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2026-03-09 - 07:36
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Mon Mar 09, 2026 00:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
361461399114101,10cyclictest3668077-21kworker/u8:2+flush-179:022:40:001
36146119910897,8cyclictest3714827-21latency_hist00:20:000
36146119910695,8cyclictest3708171-40mandb00:00:000
3614611999887,8cyclictest3687439-21kworker/u8:2+flush-179:023:20:000
3614611999585,7cyclictest3721194-21latency_hist00:40:000
3614613998984,4cyclictest3708411-21kworker/u8:1+events_unbound00:04:011
3614613998577,6cyclictest3712982-21apt-get00:15:001
3614613998472,9cyclictest266-21systemd-journal00:00:011
3614611998371,9cyclictest266-21systemd-journal23:20:140
3614611998371,9cyclictest266-21systemd-journal23:20:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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