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2026-02-25 - 04:42
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Wed Feb 25, 2026 00:44:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
37886269910895,10cyclictest266-21systemd-journal00:00:010
3788626999389,3cyclictest3863124-21kworker/u8:0+events_unbound23:00:240
3788626999282,6cyclictest3813035-21latency_hist20:25:010
3788627999183,6cyclictest3794954-21latency_hist19:30:011
3788627998574,9cyclictest3801581-21latency_hist19:50:011
3788626998574,4cyclictest3869540-21kworker/u8:3+events_unbound00:20:210
3788627998480,3cyclictest3814879-21kworker/u8:2+events_unbound20:30:251
3788627998475,6cyclictest3861279-21latency_hist22:55:011
3788626998375,6cyclictest3803425-21latency_hist19:55:010
3788627998172,7cyclictest3877464-21latency_hist23:45:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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