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2026-05-22 - 04:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Fri May 22, 2026 00:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
288755499119113,3cyclictest2885976-21kworker/u8:0+flush-179:019:10:011
288755099117101,12cyclictest2929197-21latency_hist21:20:010
288755499116104,9cyclictest1213033-21systemd-journal23:05:011
288755499106100,4cyclictest2976129-21kworker/u8:0+events_unbound00:00:181
28875549910398,4cyclictest2986796-21kworker/u8:0+events_unbound00:30:001
28875509910090,7cyclictest2911617-21latency_hist20:25:010
2887554999687,7cyclictest2913204-21latency_hist20:30:011
2887550999382,8cyclictest2969772-21latency_hist23:25:010
2887554999183,7cyclictest2961860-21kworker/u8:3+events_unbound23:10:001
2887554999085,4cyclictest2968426-21kworker/u8:2+events_unbound23:20:261
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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