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2026-01-12 - 18:32
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Mon Jan 12, 2026 12:44:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
35878979910898,7cyclictest3591001-21latency_hist07:20:011
3587894999180,8cyclictest3614873-21latency_hist08:35:000
3587894998779,6cyclictest3597369-21latency_hist07:40:020
3587894998072,6cyclictest3686227-21latency_hist12:15:010
3587897997959,19cyclictest3613319-21kworker/u8:2+flush-179:008:45:001
3587903997871,5cyclictest3605347-21turbostat08:05:003
3587894997870,6cyclictest3631192-21kworker/u8:3+flush-179:010:05:000
3587894997867,8cyclictest3678513-21/usr/sbin/munin11:50:230
3587894997669,5cyclictest2911859-21kworker/u8:0+flush-179:007:30:010
358789499751,71cyclictest3689722-21unin-run12:30:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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