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2026-05-17 - 11:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Sun May 17, 2026 00:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
169614699117105,8cyclictest1799041-21latency_hist00:30:011
16961469910887,19cyclictest1789443-40mandb00:00:011
16961469910690,12cyclictest1785976-21latency_hist23:50:011
16961469910495,7cyclictest1707221-21kworker/u8:2+flush-179:021:20:001
16961429910093,6cyclictest1744128-21kworker/u8:0+flush-179:021:50:000
1696142999683,9cyclictest1213033-21systemd-journal23:45:000
1696142999579,11cyclictest1802230-21latency_hist00:40:010
1696146999287,4cyclictest1707221-21kworker/u8:2+flush-179:020:15:151
1696142999279,10cyclictest1213033-21systemd-journal23:05:000
1696146999183,6cyclictest1703968-21kworker/u8:0+flush-179:019:40:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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