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2026-04-24 - 09:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Fri Apr 24, 2026 00:44:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
89401599120111,6cyclictest1213033-21systemd-journal00:04:011
8940159911898,17cyclictest918379-21kworker/u8:3+flush-179:021:20:011
89401599118107,8cyclictest970073-21latency_hist23:05:011
8940159910796,8cyclictest1213033-21systemd-journal20:10:001
8940149910499,4cyclictest976587-21kworker/u8:0+flush-179:000:04:010
894014999986,11cyclictest987833-40logrotate00:00:010
894015999789,5cyclictest963685-21/usr/sbin/munin22:45:241
894014999686,8cyclictest901917-21kworker/u8:2+events_unbound19:40:000
894015999078,9cyclictest960254-21latency_hist22:35:011
894014998980,6cyclictest918379-21kworker/u8:3+events_unbound20:45:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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