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2026-04-23 - 20:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Thu Apr 23, 2026 12:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
369415099125115,8cyclictest3714327-21kworker/u8:1+flush-179:008:20:010
369415099125115,8cyclictest3714327-21kworker/u8:1+flush-179:008:20:010
36941509910796,8cyclictest3737535-21kworker/u8:1+flush-179:009:30:010
36941529910595,6cyclictest3699035-21kworker/u8:0+flush-179:007:40:001
3694152999679,15cyclictest3714327-21kworker/u8:1+flush-179:008:15:251
3694152999679,15cyclictest3714327-21kworker/u8:1+flush-179:008:15:251
3694152999386,5cyclictest3776518-21kworker/u8:0+flush-179:011:40:151
3694150999280,10cyclictest3755315-21apt-get10:20:010
3694150999280,10cyclictest3755315-21apt-get10:20:010
3694152999181,7cyclictest3742316-21latency_hist09:40:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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