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2026-05-10 - 07:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Sun May 10, 2026 00:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
32316059911599,12cyclictest3324868-40logrotate00:00:011
32316019910898,7cyclictest3274750-21latency_hist21:25:010
32316059910795,11cyclictest3311693-21kworker/u8:3+events_unbound23:25:251
3231605999989,8cyclictest3334476-21kworker/u8:1+flush-179:000:40:001
3231605999892,4cyclictest3324934-21kworker/u8:2+flush-179:000:03:591
3231605999683,5cyclictest3254009-21kworker/u8:1+events_unbound20:35:231
3231605999587,6cyclictest3309483-21kworker/u8:1+events_unbound23:10:241
3231605999486,7cyclictest3254009-21kworker/u8:1+events_unbound20:20:001
3231605999383,8cyclictest3249027-21apt-get20:05:041
3231605998980,7cyclictest3260384-21kworker/u8:2+events_unbound21:15:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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