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2026-07-09 - 16:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Thu Jul 09, 2026 12:44:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
57995599145134,8cyclictest684957-21latency_hist12:35:020
57995599145134,8cyclictest684957-21latency_hist12:35:020
57995599145131,5cyclictest592673-21kworker/u8:1+events_unbound08:20:000
57995599131125,5cyclictest683415-21kworker/u8:1+events_unbound12:40:000
57995999127122,3cyclictest605918-21kworker/u8:3+events_unbound08:50:251
57995599126116,7cyclictest600640-21latency_hist08:15:010
57995599126112,10cyclictest1213033-21systemd-journal10:00:000
57995599122117,4cyclictest630122-21kworker/u8:3+events_unbound09:50:250
57995599122117,4cyclictest630122-21kworker/u8:3+events_unbound09:50:250
57995999121106,12cyclictest1213033-21systemd-journal11:10:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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