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2025-12-11 - 08:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Thu Dec 11, 2025 00:44:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31205459910089,3cyclictest3120485-21kworker/u8:3+events_unbound19:20:261
3120545999691,4cyclictest3185387-21kworker/u8:3+events_unbound22:30:251
3120545999488,4cyclictest3174292-21kworker/u8:1+events_unbound23:00:231
3120544999183,5cyclictest3159204-21kworker/u8:3+flush-179:021:35:260
3120545998983,5cyclictest3206867-21kworker/u8:0+events_unbound23:35:241
3120545998881,5cyclictest3203940-21kworker/u8:3+events_unbound23:30:221
3120545998780,5cyclictest3203940-21kworker/u8:3+flush-179:000:00:241
3120545998780,5cyclictest3155218-21kworker/u8:0+events_unbound21:10:241
3120544998678,5cyclictest3222865-21latency_hist00:25:010
3120544998574,7cyclictest3131843-21latency_hist19:45:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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