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2026-01-14 - 09:23
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Wed Jan 14, 2026 00:44:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
36132319911398,11cyclictest3709968-21cat00:10:011
361322999112104,5cyclictest3622675-21latency_hist19:40:010
36132319910899,6cyclictest3611645-21kworker/u8:0+flush-179:020:25:001
36132299910493,8cyclictest3632220-21latency_hist20:10:010
3613231999387,5cyclictest3643662-21kworker/u8:1+events_unbound21:05:241
3613231998982,5cyclictest3692817-21kworker/u8:0+events_unbound23:25:001
3613229998983,4cyclictest3679177-21apt-get22:35:020
3613231998883,4cyclictest3696922-21kworker/u8:2+events_unbound23:45:251
3613231998883,4cyclictest3696922-21kworker/u8:2+events_unbound23:45:241
3613229998779,5cyclictest1-21systemd23:10:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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