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2026-01-13 - 19:44
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Tue Jan 13, 2026 12:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
22047949910087,10cyclictest266-21systemd-journal08:25:001
2204788999891,5cyclictest2258652-21kworker/u8:1+events_unbound10:15:010
2204788999080,4cyclictest2232469-21kworker/u8:0+events_unbound09:00:230
2204794998878,7cyclictest2269783-21kworker/u8:3+flush-179:010:50:011
2204788998878,8cyclictest2221028-21latency_hist08:00:010
2204788998580,4cyclictest2255606-21kworker/u8:2+events_unbound10:00:240
2204788998373,3cyclictest2230802-21kworker/u8:1+events_unbound09:25:100
2204788998277,4cyclictest2224494-21kworker/u8:2+events_unbound08:45:280
2204794997974,4cyclictest2287552-21kworker/u8:2+events_unbound11:54:561
2204794997870,5cyclictest2284393-21latency_hist11:25:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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