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2026-01-12 - 04:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Mon Jan 12, 2026 00:44:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
21709939910695,9cyclictest2264821-40mandb00:00:011
21709939910093,6cyclictest2265822-21kworker/u8:0+events_unbound00:05:011
2170991999885,10cyclictest2264821-40mandb00:00:010
2170991999791,4cyclictest2251859-21kworker/u8:0+events_unbound23:45:000
2170991998979,7cyclictest2206726-21latency_hist21:00:010
2170991998882,4cyclictest2188957-21kworker/u8:0+flush-179:020:05:260
2170991998780,4cyclictest2154674-21kworker/u8:0+flush-179:019:20:000
2170991998675,5cyclictest2188957-21kworker/u8:0+events_unbound20:15:230
2170993998479,4cyclictest2154674-21kworker/u8:0+flush-179:019:20:001
2170991998476,4cyclictest2174102-21kworker/u8:1+flush-179:019:30:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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