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2026-05-25 - 12:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Mon May 25, 2026 00:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
277726599118107,5cyclictest2817583-21kworker/u8:0+events_unbound21:55:240
277726599117108,7cyclictest2855991-21kworker/u8:1+flush-179:023:20:020
277726599115107,6cyclictest2817583-21kworker/u8:0+events_unbound22:10:000
277726799109104,4cyclictest2817583-21kworker/u8:0+events_unbound22:00:241
27772679910893,14cyclictest2846502-21kworker/u8:4+events_unbound22:45:261
277726799107101,4cyclictest2788312-21latency_hist19:45:011
27772659910799,6cyclictest2817583-21kworker/u8:0+events_unbound21:40:000
27772659910393,5cyclictest2788290-21kworker/u8:0+events_unbound19:50:240
27772659910295,5cyclictest2799725-21kworker/u8:2+events_unbound21:15:020
27772679910197,3cyclictest2807772-21kworker/u8:3+events_unbound20:45:251
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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