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2026-02-14 - 13:10
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Sat Feb 14, 2026 00:44:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2303762999688,5cyclictest2370964-21kworker/u8:3+events_unbound22:50:011
2303762999687,7cyclictest2368076-21apt-get22:30:031
2303762999078,9cyclictest2394553-21latency_hist23:50:011
2303762998664,20cyclictest2391625-21/usr/sbin/munin23:40:221
2303758998680,4cyclictest2351612-21kworker/u8:0+flush-179:022:05:000
2303762998574,8cyclictest2314761-21kworker/u8:0+flush-179:020:15:001
2303758998477,5cyclictest2354794-21kworker/u8:2+flush-179:021:55:020
2303758998377,4cyclictest2366223-21kworker/u8:0+events_unbound22:30:010
2303758998376,5cyclictest2366223-21kworker/u8:0+events_unbound22:40:000
2303758998172,7cyclictest2305467-21/usr/sbin/munin19:15:240
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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