You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-11-03 - 05:38
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Mon Nov 03, 2025 00:44:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
28145649910363,24cyclictest2875707-21latency_hist22:20:011
2814562999279,10cyclictest2819226-21latency_hist19:25:010
2814562999184,6cyclictest2848150-21kworker/u8:2+events_unbound21:15:010
2814562998780,5cyclictest2887342-21kworker/u8:2+flush-179:023:20:270
2814562998576,6cyclictest2917907-21kworker/u8:3+flush-179:000:35:000
2814564998166,13cyclictest2859265-21latency_hist21:30:011
2814564998069,8cyclictest2877552-21latency_hist22:25:011
2814562998072,6cyclictest2907834-21kworker/u8:4+flush-179:000:04:000
2814562997667,6cyclictest2904629-21kworker/u8:1+flush-179:000:15:000
2814562997565,6cyclictest2872549-21kworker/u8:1+flush-179:022:15:210
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional