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2025-05-09 - 05:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Fri May 09, 2025 00:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
359405899142130,9cyclictest3687240-40mandb00:00:011
359405599133125,6cyclictest3613567-21kworker/u8:1+flush-179:020:30:220
359405599130120,8cyclictest3610112-21apt-get20:00:000
359405599130120,8cyclictest3610112-21apt-get20:00:000
359405599129115,12cyclictest3687197-40logrotate00:00:020
359405899127117,8cyclictest3662245-21kworker/u8:2+flush-179:023:00:221
359405599125118,5cyclictest3603786-21kworker/u8:0+events_unbound20:00:020
359405599124116,5cyclictest3632844-21kworker/u8:1+events_unbound21:15:200
359405599121112,7cyclictest3597439-21kworker/u8:2+flush-179:019:40:010
359405599120113,5cyclictest3646655-21kworker/u8:0+flush-179:022:15:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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