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2025-12-08 - 04:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Mon Dec 08, 2025 00:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
317291999113102,8cyclictest3266235-40logrotate00:00:010
3172923999787,7cyclictest3245315-21kworker/u8:2+flush-179:023:30:261
3172919998977,10cyclictest271-21systemd-journal19:40:000
3172919998374,7cyclictest3203873-21/usr/sbin/munin20:45:250
3172923998276,4cyclictest3249027-21kworker/u8:0+flush-179:023:25:261
3172923998071,7cyclictest3274506-21/usr/sbin/munin00:25:271
3172923997972,5cyclictest3226204-21kworker/u8:3+flush-179:022:00:011
3172919997967,9cyclictest3223235-21/usr/sbin/munin21:45:250
3172919997868,8cyclictest3229602-21/usr/sbin/munin22:05:250
3172919997768,7cyclictest3221648-21/usr/sbin/munin21:40:240
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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