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2026-06-25 - 16:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Thu Jun 25, 2026 12:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
44621999129107,20cyclictest535533-21kworker/u8:0+flush-179:011:45:011
44621699124117,5cyclictest512524-21kworker/u8:3+events_unbound10:35:010
44621999118109,6cyclictest522563-21latency_hist11:05:011
44621699117106,8cyclictest468507-21latency_hist08:20:010
44621999115105,7cyclictest455769-21latency_hist07:40:011
44621999113104,6cyclictest488426-21kworker/u8:0+flush-179:009:25:151
4462169911390,20cyclictest530516-21latency_hist11:30:010
4462169910798,7cyclictest495033-21kworker/u8:2+flush-179:010:15:000
4462169910595,6cyclictest465350-21kworker/u8:3+flush-179:008:30:010
4462199910390,11cyclictest488426-21kworker/u8:0+flush-179:009:40:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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