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2026-02-20 - 09:02
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Fri Feb 20, 2026 00:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2356637999487,5cyclictest2367966-21apt-get19:45:031
2356634999183,6cyclictest2426309-21latency_hist22:45:000
2356634998274,6cyclictest2392345-21latency_hist21:00:020
2356637997970,6cyclictest2461912-21latency_hist00:35:011
2356634997867,8cyclictest266-21systemd-journal23:50:260
2356634997766,9cyclictest2453694-21apt-get00:10:000
2356637997650,23cyclictest2450498-21cupsd00:00:021
2356637997464,8cyclictest2385982-21latency_hist20:40:021
2356634997466,6cyclictest2366352-21latency_hist19:40:000
2356637997063,5cyclictest2429717-21kworker/u8:1+flush-179:022:55:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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