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2026-01-13 - 14:34
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Tue Jan 13, 2026 00:44:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
79454899108100,5cyclictest808790-21latency_hist19:55:011
79454899108100,5cyclictest808790-21latency_hist19:55:001
7945489910494,8cyclictest867388-21apt-get23:00:031
794548999383,7cyclictest880638-21latency_hist23:40:011
794549999188,2cyclictest0-21swapper/222:09:592
794551998583,1cyclictest0-21swapper/320:28:593
794548998476,6cyclictest836632-21latency_hist21:25:011
794548998471,10cyclictest851209-21apt-get22:10:001
794544997970,6cyclictest802428-21latency_hist19:35:000
794544997867,8cyclictest880871-21/usr/sbin/munin23:40:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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