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2026-04-21 - 00:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Mon Apr 20, 2026 12:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
37463409910596,7cyclictest3754285-21latency_hist07:35:010
37463409910292,8cyclictest3792778-21latency_hist09:35:000
3746341999686,7cyclictest3821965-21latency_hist11:05:011
3746341999284,6cyclictest3845066-21latency_hist12:15:011
3746340999081,6cyclictest3806030-21latency_hist10:15:010
3746340998677,6cyclictest3765458-21latency_hist08:10:010
3746341998577,6cyclictest3812403-21latency_hist10:35:011
3746340998174,5cyclictest3732450-21kworker/u8:0+events_unbound07:20:010
3746340997969,7cyclictest3747914-21latency_hist07:15:010
3746341997668,6cyclictest3784819-21latency_hist09:10:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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