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2026-03-01 - 19:36
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Sun Mar 01, 2026 12:44:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
37276559910776,22cyclictest3732326-21latency_hist07:25:011
3727655999774,20cyclictest3810273-21latency_hist11:25:011
3727653999282,7cyclictest3730740-21latency_hist07:20:010
3727655998272,7cyclictest3743989-21/usr/sbin/munin08:00:221
3727653998071,6cyclictest3742144-21latency_hist07:55:000
3727655997967,7cyclictest3732362-21kworker/u8:2+flush-179:007:30:001
3727653997959,18cyclictest3742383-21/usr/sbin/munin07:55:220
3727653997872,5cyclictest3788596-21kworker/u8:0+flush-179:010:20:010
3727653997872,5cyclictest3788596-21kworker/u8:0+flush-179:010:20:010
3727655997768,7cyclictest3823260-21latency_hist12:05:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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