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2026-01-27 - 05:49
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Tue Jan 27, 2026 00:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
23261329910090,8cyclictest2414159-21latency_hist23:45:011
2326132999889,7cyclictest2351544-21latency_hist20:30:001
2326130999479,12cyclictest266-21systemd-journal00:05:000
2326132998668,15cyclictest2396623-21kworker/u8:1+flush-179:023:00:001
2326132998376,4cyclictest2351551-21apt-get20:30:031
2326132998373,7cyclictest266-21systemd-journal22:50:001
2326132998373,7cyclictest266-21systemd-journal22:49:591
2326132998273,7cyclictest2340394-21latency_hist19:55:011
2326132997973,4cyclictest2393455-21latency_hist22:40:011
2326132997969,8cyclictest266-21systemd-journal20:40:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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