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2026-04-12 - 17:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Sun Apr 12, 2026 12:44:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2589693999585,7cyclictest2624309-21kworker/u8:0+flush-179:008:55:240
2589693999077,9cyclictest2608969-21latency_hist08:10:020
2589693999077,9cyclictest2608969-21latency_hist08:10:010
2589694998980,3cyclictest2592813-21kworker/u8:0+events_unbound07:35:221
2589693998981,5cyclictest2615834-21kworker/u8:0+flush-179:008:30:260
2589694998882,4cyclictest2606033-21kworker/u8:3+events_unbound08:15:241
2589693998779,5cyclictest2646633-21latency_hist10:05:010
2589694998574,9cyclictest2663040-21/usr/sbin/munin10:55:231
2589694998480,3cyclictest2605754-21kworker/u8:2+events_unbound08:35:201
2589694998476,6cyclictest2672622-21latency_hist11:25:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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