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2026-02-07 - 20:55
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Sat Feb 07, 2026 12:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9546979910090,7cyclictest1006077-21latency_hist09:50:011
9546979910090,7cyclictest1006077-21latency_hist09:50:001
954694999789,5cyclictest1038251-21kworker/u8:3+events_unbound11:35:010
954694999787,8cyclictest1056248-21kworker/u8:0+events_unbound12:40:000
954694999686,8cyclictest976612-21kworker/u8:0+events_unbound08:25:010
954694999182,7cyclictest1015629-21latency_hist10:20:000
954694998983,4cyclictest1014044-21kworker/u8:0+events_unbound10:25:240
954694998676,8cyclictest988556-21apt-get08:55:120
954694998578,5cyclictest988535-21kworker/u8:0+events_unbound09:15:010
954694998474,6cyclictest999743-21kworker/u8:1+events_unbound09:35:220
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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