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2026-04-26 - 00:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Sat Apr 25, 2026 12:44:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
88244599117111,5cyclictest928769-21kworker/u8:0+flush-179:009:55:011
88244599109103,5cyclictest974411-21kworker/u8:3+events_unbound12:05:001
8824409910899,7cyclictest865590-21kworker/u8:0+flush-179:007:30:000
88244599106100,4cyclictest895095-21kworker/u8:3+events_unbound08:15:231
8824409910497,5cyclictest934116-21kworker/u8:2+events_unbound10:15:010
8824459910196,4cyclictest973019-21kworker/u8:1+flush-179:012:20:011
882445999889,7cyclictest915798-21apt-get08:55:001
882445999791,4cyclictest895095-21kworker/u8:3+flush-179:008:00:231
882445999791,4cyclictest895095-21kworker/u8:3+flush-179:008:00:221
882445999689,5cyclictest908429-21kworker/u8:2+flush-179:009:20:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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