You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-11-17 - 05:51
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Mon Nov 17, 2025 00:44:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
29950729910088,9cyclictest3070895-21cat23:05:011
29950699910088,9cyclictest268544-21cups-browsed00:00:020
2995069999690,4cyclictest3030924-21kworker/u8:1+flush-179:021:00:260
2995069998764,20cyclictest271-21systemd-journal20:40:000
2995072998475,7cyclictest3093684-21latency_hist00:15:011
2995072998070,7cyclictest3017504-21latency_hist20:20:011
2995072997971,5cyclictest3030924-21kworker/u8:1+flush-179:021:05:261
2995072997560,13cyclictest3094988-21kworker/u8:2+events_unbound00:30:301
2995069997263,6cyclictest3059667-21/usr/sbin/munin22:30:280
2995069996933,27cyclictest3009628-21latency_hist19:55:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional