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2026-01-18 - 16:14
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Sun Jan 18, 2026 12:44:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
37020199910491,4cyclictest3699897-21kworker/u8:1+events_unbound08:35:240
37020199910088,4cyclictest3725131-21kworker/u8:3+events_unbound09:00:250
3702020999582,10cyclictest3795134-21apt-get12:10:001
3702020999084,4cyclictest3699897-21kworker/u8:1+events_unbound08:15:231
3702020998979,8cyclictest3735157-21/usr/sbin/munin09:05:241
3702019998880,6cyclictest3746375-21apt-key09:40:010
3702020998778,6cyclictest3704557-21kworker/u8:0+flush-179:007:35:021
3702019998682,3cyclictest3792985-21kworker/u8:0+events_unbound12:05:250
3702019998681,4cyclictest3773627-21kworker/u8:0+events_unbound11:40:240
3702020998479,4cyclictest3773627-21kworker/u8:0+flush-179:011:45:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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