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2026-02-21 - 09:57
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Sat Feb 21, 2026 00:44:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9526609911691,22cyclictest266-21systemd-journal19:49:590
9526649910893,11cyclictest266-21systemd-journal22:35:011
9526609910794,10cyclictest955906-21apt-get19:20:010
9526649910398,4cyclictest999601-21kworker/u8:1+flush-179:022:00:011
9526609910090,7cyclictest995372-21latency_hist21:20:010
952664999786,8cyclictest1009966-21latency_hist22:05:011
952664999781,15cyclictest954336-21kworker/u8:2+flush-179:019:30:001
952664998979,4cyclictest1037042-21kworker/u8:3+events_unbound23:45:011
952664998881,5cyclictest1029720-21kworker/u8:0+events_unbound23:30:001
952660998677,7cyclictest990851-21/usr/sbin/munin21:05:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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