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2025-11-27 - 07:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Thu Nov 27, 2025 00:44:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
180397699112101,9cyclictest271-21systemd-journal00:04:010
18039769910999,8cyclictest271-21systemd-journal23:40:000
18039789910696,8cyclictest271-21systemd-journal00:00:001
18039789910181,17cyclictest1836248-21kworker/u8:3+flush-179:021:00:001
1803978999085,4cyclictest1811835-21kworker/u8:3+flush-179:019:45:241
1803978999085,4cyclictest1811835-21kworker/u8:3+flush-179:019:45:231
1803976999080,6cyclictest1830133-21kworker/u8:1+flush-179:020:40:190
1803978998884,3cyclictest1830133-21kworker/u8:1+events_unbound21:50:231
1803978998883,4cyclictest1828540-21kworker/u8:3+events_unbound20:30:191
1803976998272,7cyclictest1805476-21latency_hist19:15:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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