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2026-02-26 - 18:53
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Thu Feb 26, 2026 12:44:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
379342699111100,9cyclictest3816210-21apt-get08:20:031
37934229910599,4cyclictest3859668-21apt-get10:35:020
3793426999585,8cyclictest3861758-21/usr/sbin/munin10:40:231
3793426999282,8cyclictest3853289-21latency_hist10:15:001
3793422998978,8cyclictest3840805-21/usr/sbin/munin09:35:230
3793422997970,7cyclictest3839219-21/usr/sbin/munin09:30:220
3793422997871,5cyclictest3877665-21kworker/u8:2+flush-179:011:30:010
3793426997762,14cyclictest3808018-21kworker/u8:1+flush-179:008:10:001
3793426997669,6cyclictest3846962-21kworker/u8:3+events_unbound10:50:011
3793422997670,4cyclictest3838963-21kworker/u8:2+flush-179:009:30:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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