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2025-08-26 - 21:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Tue Aug 26, 2025 12:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
414439899124115,6cyclictest34856-21kworker/u8:0+flush-179:011:35:021
414439599121110,7cyclictest39948-21kworker/u8:2+events_unbound12:10:010
414439599119106,9cyclictest12095-21kworker/u8:0+flush-179:011:05:020
414439899117109,5cyclictest16807-21kworker/u8:2+flush-179:010:35:011
414439599117103,11cyclictest28750-21apt-get11:10:140
414439899109102,5cyclictest4171684-21kworker/u8:1+events_unbound08:40:251
414439899108101,5cyclictest4180750-21kworker/u8:2+flush-179:009:30:011
41443989910799,5cyclictest5397-21kworker/u8:0+flush-179:010:05:021
41443989910690,6cyclictest4180750-21kworker/u8:2+events_unbound09:30:011
41443959910495,7cyclictest44951-21apt-get12:00:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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