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2026-05-23 - 08:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Sat May 23, 2026 00:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
145284599120112,6cyclictest1473967-21kworker/u8:2+events_unbound20:40:011
145284599119112,6cyclictest1508496-21kworker/u8:3+events_unbound22:00:001
145284299119109,7cyclictest1469172-21latency_hist20:00:020
145284599118109,6cyclictest1491438-21kworker/u8:2+events_unbound21:40:011
145284599117103,10cyclictest1213033-21systemd-journal23:25:011
145284299113104,6cyclictest1558965-21latency_hist00:35:000
145284299111103,6cyclictest1508496-21kworker/u8:3+flush-179:021:59:380
145284599110100,7cyclictest1472327-21kworker/u8:0+flush-179:020:25:001
14528429911081,15cyclictest1542989-21latency_hist23:45:010
14528429910595,7cyclictest1551005-21latency_hist00:10:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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