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2026-02-08 - 21:32
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Sun Feb 08, 2026 12:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
37562999910497,5cyclictest3802884-21kworker/u8:3+events_unbound09:35:020
3756299999585,4cyclictest3825744-21kworker/u8:1+events_unbound10:55:240
3756299999482,9cyclictest3849597-21latency_hist12:00:010
3756299999384,6cyclictest3853042-21latency_hist12:10:010
3756299999284,6cyclictest3743743-21kworker/u8:1+events_unbound07:30:250
3756303998777,7cyclictest3767623-21latency_hist07:45:021
3756299998679,5cyclictest3830538-21kworker/u8:3+events_unbound11:05:250
3756299998475,6cyclictest3824104-21kworker/u8:0+events_unbound10:40:150
3756299998379,3cyclictest3777399-21kworker/u8:0+events_unbound08:50:240
3756299998376,5cyclictest3838450-21kworker/u8:0+events_unbound11:25:250
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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