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2025-12-10 - 18:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Wed Dec 10, 2025 12:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17338269910191,7cyclictest1738625-21latency_hist07:25:011
1733813999380,9cyclictest271-21systemd-journal09:10:000
1733826999080,7cyclictest1789040-21latency_hist10:00:011
1733813999086,3cyclictest1810550-21kworker/u8:3+events_unbound11:05:240
1733826998776,8cyclictest1833105-21latency_hist12:15:021
1733813998782,4cyclictest1789059-21kworker/u8:0+events_unbound10:00:230
1733813998277,4cyclictest1789059-21kworker/u8:0+events_unbound10:10:290
1733826998174,5cyclictest1745061-21kworker/u8:2+flush-179:008:40:011
1733813998171,7cyclictest1737023-21latency_hist07:20:020
1733826998069,8cyclictest1755078-21latency_hist08:15:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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