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2025-12-08 - 17:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Mon Dec 08, 2025 12:44:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
368331999988,8cyclictest371493-21latency_hist07:20:010
368331998983,4cyclictest374697-21kworker/u8:0+events_unbound07:40:240
368331998579,4cyclictest374697-21kworker/u8:0+events_unbound07:50:230
368331998377,4cyclictest374697-21kworker/u8:0+events_unbound07:45:240
368331998170,9cyclictest400554-21cat08:50:000
368331998070,8cyclictest456949-21/usr/sbin/munin11:45:240
368331997969,7cyclictest446834-21latency_hist11:15:010
368332997867,8cyclictest437295-21latency_hist10:45:011
368331997772,4cyclictest452481-21kworker/u8:2+events_unbound11:55:010
368332997264,6cyclictest389040-21kworker/u8:3+flush-179:009:00:261
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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