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2026-04-01 - 02:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Tue Mar 31, 2026 12:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31144499910293,6cyclictest3150381-21latency_hist09:00:021
3114445999890,5cyclictest3179320-21kworker/u8:3+events_unbound10:45:240
3114445999689,5cyclictest3189143-21kworker/u8:0+flush-179:011:20:000
3114445999688,6cyclictest3208263-21kworker/u8:0+events_unbound12:10:010
3114445999284,6cyclictest3129200-21kworker/u8:1+flush-179:008:05:010
3114449998777,7cyclictest3133945-21latency_hist08:10:011
3114449998777,6cyclictest3182555-21kworker/u8:1+flush-179:011:20:141
3114445998375,5cyclictest3198412-21kworker/u8:2+events_unbound11:50:230
3114445998175,5cyclictest3112759-21kworker/u8:3+events_unbound07:10:040
3114445998173,6cyclictest3198412-21kworker/u8:2+events_unbound11:40:250
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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