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2026-02-21 - 22:18
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Sat Feb 21, 2026 12:44:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
23530209910089,9cyclictest2450089-21latency_hist12:10:010
2353029999988,8cyclictest266-21systemd-journal08:15:011
2353029999286,4cyclictest2407938-21apt-get10:00:001
2353029999181,8cyclictest2435507-21latency_hist11:25:011
2353029999079,8cyclictest2414794-21/usr/sbin/munin10:20:221
2353029999078,10cyclictest2369441-21apt-get08:00:031
235302099901,85cyclictest1-21systemd09:00:010
2353020998878,8cyclictest2448504-21latency_hist12:05:010
2353029998576,7cyclictest2428592-21kworker/u8:1+events_unbound12:15:231
2353020998578,4cyclictest1-21systemd07:55:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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