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2026-08-06 - 20:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Thu Aug 06, 2026 12:44:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
102018399154143,8cyclictest1071744-21latency_hist09:50:020
102018399138131,5cyclictest1047578-21kworker/u8:2+events_unbound08:50:000
102018399137124,10cyclictest1078349-21kworker/u8:0+flush-179:010:50:010
102018699134121,10cyclictest1115781-21latency_hist12:05:001
102018399131124,4cyclictest1117626-21latency_hist12:10:010
102018399129120,6cyclictest1084992-21kworker/u8:3+events_unbound10:35:010
102018399126119,4cyclictest1086640-21kworker/u8:2+flush-179:010:35:250
102018699125116,5cyclictest1078349-21kworker/u8:0+flush-179:011:00:231
1020183991240,119cyclictest1-21systemd10:05:010
102018699123110,9cyclictest1073330-21latency_hist09:55:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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