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2026-05-07 - 21:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Thu May 07, 2026 12:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
506495999287,4cyclictest519498-21kworker/u8:3+events_unbound08:20:010
506495998880,6cyclictest527415-21latency_hist08:15:000
506495998781,4cyclictest554985-21kworker/u8:2+events_unbound09:45:230
506497998576,6cyclictest550237-21latency_hist09:25:011
506497998560,22cyclictest586012-21/usr/sbin/munin11:15:231
506495998577,7cyclictest532427-21kworker/u8:2+events_unbound09:10:000
506497998464,18cyclictest534084-21kworker/u8:1+flush-179:008:44:591
506495998274,5cyclictest591068-21kworker/u8:1+events_unbound11:35:150
506495998074,4cyclictest525037-21kworker/u8:0+flush-179:008:10:000
506497997867,8cyclictest553395-21kworker/u8:3+flush-179:010:05:221
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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