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2026-02-25 - 17:13
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Wed Feb 25, 2026 12:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9977619910896,9cyclictest266-21systemd-journal12:40:001
997760998677,7cyclictest1037781-21apt-get09:15:040
997760998374,6cyclictest1057120-21latency_hist10:15:000
997760998272,8cyclictest1098843-21apt-get12:25:000
997761998072,6cyclictest1055772-21/usr/sbin/munin10:10:211
997760997569,4cyclictest1001552-21kworker/u8:2+flush-179:009:05:010
997760997465,7cyclictest1092496-21kworker/u8:1+events_unbound12:10:190
997760997465,7cyclictest1092496-21kworker/u8:1+events_unbound12:10:180
997761997361,9cyclictest266-21systemd-journal10:30:001
997761997260,9cyclictest266-21systemd-journal11:25:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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