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2026-06-04 - 14:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Thu Jun 04, 2026 00:44:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
84127499125115,7cyclictest915716-21kworker/u8:2+flush-179:000:04:000
8412749911298,11cyclictest855037-21latency_hist20:20:020
8412749911298,11cyclictest855037-21latency_hist20:20:010
8412759910892,12cyclictest1213033-21systemd-journal20:15:011
8412749910697,7cyclictest1213033-21systemd-journal21:35:000
8412759910377,23cyclictest887911-21latency_hist22:25:001
8412759910293,6cyclictest856885-21latency_hist20:25:021
8412749910189,9cyclictest930378-21latency_hist00:35:000
841274999987,10cyclictest1213033-21systemd-journal23:50:000
841275999890,5cyclictest866168-21latency_hist21:15:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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