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2026-02-18 - 18:53
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Wed Feb 18, 2026 12:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2346743999487,5cyclictest2359503-21kworker/u8:1+events_unbound08:00:011
2346743999483,8cyclictest2388685-21latency_hist09:20:011
2346743999275,15cyclictest2342194-21kworker/u8:3+flush-179:008:20:011
2346743999275,15cyclictest2342194-21kworker/u8:3+flush-179:008:20:011
2346743998881,5cyclictest2375971-21kworker/u8:0+events_unbound08:45:031
2346743998783,3cyclictest2398292-21kworker/u8:2+flush-179:010:05:241
2346743998774,8cyclictest266-21systemd-journal11:40:001
2346742998778,7cyclictest2449716-21latency_hist12:30:020
2346743998581,3cyclictest2375971-21kworker/u8:0+events_unbound08:50:241
2346742998571,11cyclictest266-21systemd-journal09:25:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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