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2026-01-16 - 21:27
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Fri Jan 16, 2026 12:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
22931379910393,7cyclictest2347038-21latency_hist09:55:010
22931409910186,11cyclictest2292833-21latency_hist07:10:021
2293137999988,8cyclictest2296585-21latency_hist07:20:010
2293137999585,7cyclictest2368564-21latency_hist11:00:010
2293137999488,4cyclictest2304102-21kworker/u8:0+events_unbound07:50:220
2293137999281,8cyclictest2375206-21latency_hist11:25:010
2293140998981,6cyclictest2311309-21kworker/u8:1+events_unbound08:35:231
2293137998878,4cyclictest2339059-21kworker/u8:0+events_unbound10:15:230
2293137998878,4cyclictest2339059-21kworker/u8:0+events_unbound10:15:230
2293137998476,3cyclictest2329495-21kworker/u8:0+events_unbound09:10:220
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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