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2026-02-19 - 06:52
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackeslot6.osadl.org (updated Thu Feb 19, 2026 00:44:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
37501329910095,4cyclictest3837894-21kworker/u8:1+events_unbound00:04:001
37501329910091,7cyclictest3773072-21latency_hist20:20:011
3750127999679,14cyclictest3761705-21http19:45:010
3750127999184,5cyclictest3824548-21kworker/u8:0+flush-179:023:30:010
3750132999080,8cyclictest3802316-21apt-get21:50:031
3750127999083,6cyclictest3844283-21kworker/u8:3+flush-179:000:10:010
3750127998781,4cyclictest3758486-21kworker/u8:2+events_unbound19:50:260
3750132998675,9cyclictest3844240-40mandb00:00:021
3750127998679,5cyclictest3851135-21kworker/u8:3+events_unbound00:20:000
3750127998675,4cyclictest3836243-21kworker/u8:3+events_unbound23:35:250
3750132998573,9cyclictest3847715-21latency_hist00:10:001
3750127998476,6cyclictest3829881-21latency_hist23:15:010
3750127998476,6cyclictest3805737-21latency_hist22:00:010
3750127998378,3cyclictest3824548-21kworker/u8:0+flush-179:023:20:230
3750127998378,3cyclictest3790558-21kworker/u8:2+events_unbound21:15:210
3750127998376,5cyclictest3753704-21kworker/u8:3+flush-179:019:25:000
3750132998276,5cyclictest3796299-21kworker/u8:3+events_unbound21:45:001
3750127998270,4cyclictest3790558-21kworker/u8:2+events_unbound22:55:240
3750127998073,5cyclictest3790558-21kworker/u8:2+flush-179:022:50:240
3750127998067,5cyclictest3737609-21kworker/u8:2+flush-179:019:15:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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