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2026-01-22 - 01:59
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackeslot6.osadl.org (updated Wed Jan 21, 2026 12:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3716830999282,8cyclictest3743039-21kworker/u8:0+flush-179:010:20:030
3716831998778,6cyclictest3778597-21latency_hist10:20:021
3716831998266,13cyclictest3712372-21kworker/u8:0+flush-179:007:40:011
3716831998266,13cyclictest3712372-21kworker/u8:0+flush-179:007:40:011
3716830998277,3cyclictest3754505-21kworker/u8:1+flush-179:009:25:120
3716831997969,7cyclictest3757643-21latency_hist09:15:001
3716830997864,11cyclictest266-21systemd-journal11:40:010
3716830997864,11cyclictest266-21systemd-journal11:40:010
3716831997567,5cyclictest3764053-21kworker/u8:3+flush-179:010:00:161
3716830997468,4cyclictest3789112-21kworker/u8:3+events_unbound11:25:180
3716830997466,6cyclictest3806194-21latency_hist11:45:010
3716830997464,8cyclictest266-21systemd-journal12:00:010
3716831997263,7cyclictest3789112-21kworker/u8:3+flush-179:010:55:211
3716830997268,3cyclictest3801400-21kworker/u8:0+events_unbound11:49:550
3716830997268,3cyclictest3741138-21kworker/u8:1+events_unbound08:29:560
3716830997263,7cyclictest3765605-21latency_hist09:40:000
3716831997165,4cyclictest3813661-21kworker/u8:0+flush-179:012:10:261
3716831997165,4cyclictest3785208-21kworker/u8:2+flush-179:011:15:001
3716831997164,5cyclictest3760873-21kworker/u8:2+flush-179:009:35:001
3716830997162,7cyclictest3817323-21latency_hist12:20:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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