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2026-01-26 - 05:18
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackeslot6.osadl.org (updated Mon Jan 26, 2026 00:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
37300209910584,19cyclictest3775316-21kworker/u8:1+flush-179:022:10:011
3730020999789,6cyclictest3817216-21kworker/u8:1+events_unbound23:40:001
3730020999777,19cyclictest3778438-21kworker/u8:2+flush-179:021:45:001
3730020999078,10cyclictest3823874-40mandb00:00:011
3730020998675,9cyclictest266-21systemd-journal00:30:011
3730020998558,19cyclictest3787995-21kworker/u8:0+flush-179:022:15:011
3730020998276,4cyclictest3775316-21kworker/u8:1+flush-179:021:50:011
3730018998273,6cyclictest3815650-21latency_hist23:35:010
3730018998074,4cyclictest3733344-21kworker/u8:0+flush-179:019:20:270
3730018998070,7cyclictest3817495-21/usr/sbin/munin23:40:230
3730020997972,6cyclictest3822068-21kworker/u8:0+events_unbound00:40:001
3730020997469,4cyclictest3739782-21kworker/u8:0+flush-179:019:50:011
3730018997463,8cyclictest3757472-21/usr/sbin/munin20:35:230
3730018997263,7cyclictest266-21systemd-journal21:15:010
3730018997260,8cyclictest266-21systemd-journal00:04:000
3730020997162,7cyclictest3833989-21/usr/sbin/munin00:30:231
3730020997063,6cyclictest3827368-21kworker/u8:1+flush-179:000:10:001
3730020996963,5cyclictest3745158-21kworker/u8:1+flush-179:020:00:201
3730020996963,4cyclictest3760416-21kworker/u8:1+flush-179:020:44:551
3730020996962,5cyclictest3796007-21kworker/u8:3+flush-179:023:20:251
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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