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2025-11-29 - 18:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackeslot6.osadl.org (updated Sat Nov 29, 2025 12:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
380230999987,9cyclictest480211-21latency_hist12:20:001
380230999685,8cyclictest271-21systemd-journal12:40:001
380230998883,4cyclictest425316-21kworker/u8:3+events_unbound09:45:251
380230998480,3cyclictest425316-21kworker/u8:3+flush-179:009:50:261
380230998479,4cyclictest444710-21kworker/u8:4+events_unbound10:30:251
380230998479,4cyclictest444710-21kworker/u8:4+events_unbound10:30:251
380230998479,4cyclictest435128-21kworker/u8:1+events_unbound10:00:231
380230998477,5cyclictest411204-21kworker/u8:1+events_unbound09:35:021
380228998480,3cyclictest411204-21kworker/u8:1+events_unbound09:20:250
380228998378,4cyclictest411204-21kworker/u8:1+events_unbound09:25:260
380230998171,5cyclictest476676-21kworker/u8:1+events_unbound12:30:191
380228998171,7cyclictest485243-21latency_hist12:35:020
380228998076,3cyclictest462747-21kworker/u8:3+events_unbound12:10:210
380230997970,7cyclictest438289-21kworker/u8:0+flush-179:010:25:011
380230997969,4cyclictest431935-21kworker/u8:2+events_unbound10:10:251
380230997873,4cyclictest407757-21kworker/u8:0+flush-179:008:35:251
380230997671,4cyclictest425316-21kworker/u8:3+events_unbound09:40:231
380230997667,4cyclictest378641-21kworker/u8:2+events_unbound07:15:231
380230997571,3cyclictest386415-21kworker/u8:3+events_unbound08:15:241
38022899751,70cyclictest1-21systemd10:45:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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