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2026-01-25 - 03:38
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackeslot6.osadl.org (updated Sun Jan 25, 2026 00:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
93372799112101,8cyclictest1027281-21kworker/u8:1+flush-179:000:20:030
9337289910596,6cyclictest980028-21kworker/u8:0+flush-179:021:40:001
9337289910596,6cyclictest980028-21kworker/u8:0+flush-179:021:40:001
9337289910190,8cyclictest947947-21latency_hist19:55:011
9337289910092,6cyclictest1006020-21kworker/u8:0+flush-179:023:55:001
933728999590,4cyclictest928892-21kworker/u8:2+events_unbound19:40:001
933727999282,7cyclictest975289-21latency_hist21:20:010
933728998883,4cyclictest1027281-21kworker/u8:1+flush-179:000:20:261
933728998376,6cyclictest964870-21kworker/u8:2+flush-179:021:10:011
933728998175,5cyclictest962337-21kworker/u8:0+flush-179:021:00:231
933728998076,3cyclictest928892-21kworker/u8:2+events_unbound19:30:211
933728998071,6cyclictest1022238-21latency_hist23:45:011
933728997873,4cyclictest985122-21kworker/u8:3+events_unbound22:00:001
933728997871,5cyclictest928892-21kworker/u8:2+events_unbound20:35:231
933727997867,8cyclictest967048-21latency_hist20:55:010
933728997772,4cyclictest1006020-21kworker/u8:0+events_unbound23:15:221
933728997772,4cyclictest1006020-21kworker/u8:0+events_unbound23:15:221
933728997770,5cyclictest928892-21kworker/u8:2+events_unbound19:15:141
933728997669,5cyclictest944809-21kworker/u8:3+flush-179:020:15:211
933728997667,7cyclictest941556-21kworker/u8:0+flush-179:019:40:201
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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