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2026-01-29 - 06:11
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackeslot6.osadl.org (updated Thu Jan 29, 2026 00:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
373123899129118,8cyclictest266-21systemd-journal00:00:010
373123899129118,8cyclictest266-21systemd-journal00:00:010
3731239999283,6cyclictest3799086-21kworker/u8:2+events_unbound23:25:001
3731239999186,3cyclictest3803266-21kworker/u8:0+flush-179:022:55:021
3731239999082,6cyclictest3835953-21latency_hist00:35:011
3731239998779,5cyclictest3781319-21kworker/u8:2+flush-179:022:05:001
3731239998777,7cyclictest3818380-21/usr/sbin/munin23:40:231
3731239998677,6cyclictest3781319-21kworker/u8:2+flush-179:022:00:011
3731239998575,7cyclictest266-21systemd-journal00:04:001
3731239998276,4cyclictest3776239-21kworker/u8:3+events_unbound21:35:241
3731239998274,5cyclictest3734284-21kworker/u8:2+flush-179:019:55:011
3731239998270,5cyclictest3831230-21kworker/u8:0+events_unbound00:25:011
3731239998174,5cyclictest3768285-21kworker/u8:0+flush-179:021:10:011
3731239997772,4cyclictest3831230-21kworker/u8:0+events_unbound00:35:241
3731239997667,7cyclictest3799086-21kworker/u8:2+flush-179:022:50:001
3731238997665,8cyclictest3827974-21/usr/sbin/munin00:10:220
3731239997568,5cyclictest3812014-21kworker/u8:1+events_unbound23:35:231
3731239997566,7cyclictest3781319-21kworker/u8:2+flush-179:022:20:011
3731239997565,6cyclictest3768285-21kworker/u8:0+flush-179:021:15:201
3731239997465,6cyclictest3760347-21latency_hist20:40:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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