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2026-01-15 - 18:27
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackeslot6.osadl.org (updated Thu Jan 15, 2026 12:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
36561809910797,8cyclictest3727753-21latency_hist10:50:010
3656184999282,7cyclictest3753488-21latency_hist12:10:021
3656180999282,7cyclictest3732539-21latency_hist11:05:010
3656180999080,7cyclictest3712652-21latency_hist10:05:020
3656180999077,9cyclictest266-21systemd-journal09:15:010
3656180998780,5cyclictest3720460-21kworker/u8:1+events_unbound10:40:240
3656180998777,8cyclictest3742319-21/usr/sbin/munin11:35:220
3656180998680,5cyclictest3651580-21kworker/u8:0+events_unbound07:20:240
3656180998678,5cyclictest3662485-21kworker/u8:3+flush-179:007:45:000
3656180998479,4cyclictest3643168-21kworker/u8:2+flush-179:007:50:230
3656180998476,5cyclictest3673589-21kworker/u8:2+flush-179:008:25:190
3656180998476,5cyclictest3673589-21kworker/u8:2+flush-179:008:25:190
3656180998474,7cyclictest3673614-21latency_hist08:05:000
3656184998272,7cyclictest3711054-21latency_hist10:00:011
3656184998270,9cyclictest3719539-21latency_hist10:25:021
3656184998269,10cyclictest266-21systemd-journal08:00:011
3656184998171,7cyclictest3673589-21kworker/u8:2+flush-179:008:15:261
3656180998173,6cyclictest3712701-21kworker/u8:3+flush-179:010:05:030
3656180997870,5cyclictest3670399-21kworker/u8:0+flush-179:008:15:200
3656184997767,8cyclictest510-21rs:main1
3656184997760,15cyclictest3670399-21kworker/u8:0+flush-179:008:40:001
3656180997771,4cyclictest3743724-21kworker/u8:2+events_unbound11:45:220
3656180997767,7cyclictest3701242-21latency_hist09:30:010
3656184997666,7cyclictest3729338-21latency_hist10:55:021
3656180997672,3cyclictest3737277-21kworker/u8:1+flush-179:012:00:010
3656180997671,4cyclictest3662485-21kworker/u8:3+events_unbound07:30:230
3656180997667,6cyclictest3690039-21latency_hist08:55:010
3656180997667,6cyclictest3690039-21latency_hist08:55:010
3656180997666,8cyclictest3751884-21kworker/u8:0+flush-179:012:10:250
3656180997571,3cyclictest3667273-21kworker/u8:1+flush-179:007:50:010
3656180997570,4cyclictest3748686-21kworker/u8:2+flush-179:012:30:000
3656180997569,4cyclictest3670399-21kworker/u8:0+events_unbound07:55:230
3656180997567,5cyclictest3687274-21kworker/u8:0+flush-179:008:45:210
3656180997567,5cyclictest3687274-21kworker/u8:0+flush-179:008:45:210
3656180997469,4cyclictest3739951-21kworker/u8:2+events_unbound11:25:230
3656180997467,5cyclictest3708656-21kworker/u8:0+events_unbound10:15:240
3656180997467,5cyclictest3654583-21kworker/u8:1+flush-179:007:10:230
3656180997363,7cyclictest3716343-21latency_hist10:15:000
3656180997361,10cyclictest3722978-21/usr/sbin/munin10:35:000
3656184997164,5cyclictest3673589-21kworker/u8:2+flush-179:008:15:001
3656180997167,3cyclictest191rcuc/009:05:000
3656180997162,7cyclictest3665650-21latency_hist07:40:010
3656180997064,4cyclictest3691657-21kworker/u8:2+flush-179:009:40:200
3656180997057,5cyclictest3643168-21kworker/u8:2+flush-179:007:15:200
3656180996963,4cyclictest3691657-21kworker/u8:2+events_unbound10:20:140
3656180996962,5cyclictest3670399-21kworker/u8:0+flush-179:008:10:000
3656184996742,22cyclictest3706026-21latency_hist09:45:011
3656180996762,4cyclictest3688172-21kworker/u8:1+events_unbound09:05:250
3656180996760,5cyclictest3708656-21kworker/u8:0+events_unbound09:55:020
3656180996760,5cyclictest3682491-21kworker/u8:1+events_unbound08:30:240
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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