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2026-01-24 - 09:59
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackeslot6.osadl.org (updated Sat Jan 24, 2026 00:44:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
232487899109101,6cyclictest2352078-21kworker/u8:1+events_unbound20:35:000
23248789910393,7cyclictest266-21systemd-journal21:55:000
2324878999181,7cyclictest2401734-21kworker/u8:0+events_unbound23:20:010
2324878999080,7cyclictest2345471-21latency_hist20:15:000
2324878998874,11cyclictest266-21systemd-journal00:04:010
2324878998681,4cyclictest2324805-21kworker/u8:2+flush-179:019:49:540
2324878998676,7cyclictest2342302-21latency_hist20:05:020
2324878998576,7cyclictest2366479-21kworker/u8:3+events_unbound22:20:010
2324879998475,6cyclictest2329572-21latency_hist19:25:011
2324879998172,6cyclictest2417878-21kworker/u8:3+flush-179:000:00:011
2324879998066,11cyclictest2363283-21kworker/u8:2+flush-179:021:30:001
2324878998072,6cyclictest2409623-21kworker/u8:0+flush-179:023:55:220
2324879997873,3cyclictest2406443-21kworker/u8:2+flush-179:023:45:161
2324879997865,10cyclictest2324748-21kworker/u8:0+flush-179:019:25:231
2324878997872,4cyclictest2398540-21kworker/u8:3+flush-179:023:10:000
2324878997668,5cyclictest2342275-21kworker/u8:2+flush-179:020:40:010
2324878997667,7cyclictest2406443-21kworker/u8:2+flush-179:023:40:000
2324879997567,5cyclictest2422686-21latency_hist00:15:011
2324879997565,8cyclictest2427456-21kworker/u8:2+flush-179:000:30:211
2324879997564,7cyclictest2366479-21kworker/u8:3+flush-179:021:50:251
2324879997364,6cyclictest2366415-21latency_hist21:20:021
2324879997364,6cyclictest2366415-21latency_hist21:20:011
2324878997268,3cyclictest2339152-21kworker/u8:3+events_unbound20:45:230
2324878997164,5cyclictest2393979-21kworker/u8:1+flush-179:022:50:000
2324879996965,2cyclictest0-21swapper/122:04:591
2324878996957,9cyclictest266-21systemd-journal21:25:010
2324878996864,3cyclictest2363283-21kworker/u8:2+flush-179:022:14:560
2324879996754,10cyclictest2371170-21kworker/u8:0+flush-179:021:35:011
2324878996760,4cyclictest2339152-21kworker/u8:3+events_unbound21:05:000
232487899670,65cyclictest1-21systemd23:05:000
2324879996659,5cyclictest2335938-21latency_hist19:45:011
2324879996659,5cyclictest2335938-21latency_hist19:45:001
2324878996660,4cyclictest2363283-21kworker/u8:2+events_unbound22:20:120
2324878996660,4cyclictest2334318-21kworker/u8:1+flush-179:019:55:250
2324879996561,2cyclictest714-21Xorg23:50:591
2324879996560,2cyclictest714-21Xorg23:21:591
2324879996456,6cyclictest2419514-21latency_hist00:05:001
2324878996458,4cyclictest2339152-21kworker/u8:3+flush-179:020:50:140
2324878996458,4cyclictest2339152-21kworker/u8:3+flush-179:020:50:140
2324878996456,6cyclictest2324805-21kworker/u8:2+flush-179:019:35:000
2324879996359,3cyclictest2324805-21kworker/u8:2+events_unbound19:33:531
2324879996355,6cyclictest2342538-21/usr/sbin/munin20:05:221
2324878996357,4cyclictest2393979-21kworker/u8:1+events_unbound23:10:170
2324878996356,5cyclictest2366479-21kworker/u8:3+flush-179:021:35:200
2324878996252,8cyclictest2417878-21kworker/u8:3+flush-179:000:20:010
2324879996157,3cyclictest2324748-21kworker/u8:0+events_unbound19:16:541
2324879996153,6cyclictest2350509-21latency_hist20:30:021
232487899610,59cyclictest1-21systemd19:40:230
232487899610,59cyclictest1-21systemd19:40:230
2324879996056,3cyclictest2334318-21kworker/u8:1+events_unbound19:46:361
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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