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2026-02-02 - 03:15
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackeslot6.osadl.org (updated Sun Feb 01, 2026 12:44:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
95328299122112,3cyclictest962775-21kworker/u8:4+events_unbound08:20:001
9532829910093,5cyclictest977334-21kworker/u8:1+events_unbound08:25:001
953280999888,7cyclictest1054996-21latency_hist12:25:000
953282999790,4cyclictest1032993-21kworker/u8:3+events_unbound11:15:231
953280999686,7cyclictest1049959-21latency_hist12:10:010
953282999488,5cyclictest1000098-21kworker/u8:2+events_unbound09:45:221
953280999486,5cyclictest962775-21kworker/u8:4+events_unbound08:00:000
953280999183,6cyclictest1039874-21kworker/u8:0+flush-179:012:30:010
953282999079,8cyclictest980510-21apt-get08:35:021
953280998982,5cyclictest1039874-21kworker/u8:0+events_unbound12:15:240
953280998982,5cyclictest1039874-21kworker/u8:0+events_unbound12:15:240
953282998682,3cyclictest957927-21kworker/u8:2+events_unbound08:10:251
953282998682,3cyclictest1026090-21kworker/u8:3+flush-179:010:55:011
953282998475,6cyclictest948413-21kworker/u8:3+events_unbound07:10:191
953282998378,4cyclictest986033-21kworker/u8:1+flush-179:009:10:201
953280998377,4cyclictest970707-21latency_hist08:05:010
953282998172,7cyclictest1024241-21latency_hist10:50:001
953282997972,5cyclictest986033-21kworker/u8:1+events_unbound08:50:231
953282997972,5cyclictest974178-21kworker/u8:0+flush-179:008:30:211
953282997971,6cyclictest965925-21latency_hist07:50:011
953282997872,4cyclictest957927-21kworker/u8:2+events_unbound08:10:011
953280997873,4cyclictest1004904-21kworker/u8:0+flush-179:010:10:250
953280997871,5cyclictest986033-21kworker/u8:1+flush-179:009:05:230
953280997871,5cyclictest1016039-21kworker/u8:0+flush-179:010:35:230
953282997769,6cyclictest1022657-21latency_hist10:45:001
953280997765,10cyclictest510-21rs:main0
953280997568,5cyclictest1016034-21latency_hist10:25:010
953282997461,4cyclictest986033-21kworker/u8:1+events_unbound10:15:191
953282997263,7cyclictest982419-21kworker/u8:2+events_unbound08:45:141
953280997266,4cyclictest1043631-21kworker/u8:2+flush-179:012:05:000
953282997163,6cyclictest1004904-21kworker/u8:0+events_unbound10:05:201
953282997065,4cyclictest1051261-21kworker/u8:2+events_unbound12:15:021
953282997065,4cyclictest1051261-21kworker/u8:2+events_unbound12:15:021
953282997063,5cyclictest1022701-21kworker/u8:0+flush-179:011:05:211
953282997062,6cyclictest957927-21kworker/u8:2+flush-179:007:40:001
953280997064,4cyclictest957927-21kworker/u8:2+flush-179:008:10:000
953280997064,4cyclictest957927-21kworker/u8:2+flush-179:007:50:230
953280997064,4cyclictest1030860-21kworker/u8:2+flush-179:011:25:260
953282996964,4cyclictest992822-21kworker/u8:0+events_unbound09:25:011
953282996862,4cyclictest957927-21kworker/u8:2+events_unbound07:25:241
953282996860,5cyclictest992161-21latency_hist09:10:011
95328799670,65cyclictest0-21swapper/308:41:593
953282996755,10cyclictest1019204-21latency_hist10:35:011
953280996762,3cyclictest1011301-21kworker/u8:2+flush-179:010:50:250
953282996660,5cyclictest1022701-21kworker/u8:0+events_unbound11:20:151
953282996660,4cyclictest982419-21kworker/u8:2+events_unbound08:40:181
953280996663,2cyclictest0-21swapper/011:20:000
953280996661,4cyclictest1039874-21kworker/u8:0+flush-179:012:30:240
95328799650,63cyclictest0-21swapper/308:32:593
953282996559,4cyclictest1048610-21kworker/u8:1+flush-179:012:10:151
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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