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2025-09-14 - 03:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackeslot6.osadl.org (updated Sun Sep 14, 2025 00:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
394456699121114,5cyclictest4041960-21kworker/u8:0+events_unbound00:15:011
394456699112100,9cyclictest3968933-21latency_hist20:25:001
39445639910594,9cyclictest3969187-21apt-get20:25:120
39445639910190,8cyclictest4014090-21kworker/u8:3+flush-179:023:20:000
3944566999989,7cyclictest3950881-21latency_hist19:30:021
3944566999892,4cyclictest4014090-21kworker/u8:3+events_unbound23:00:261
3944566999885,10cyclictest4038230-40mandb00:00:001
3944563999890,6cyclictest4014034-21kworker/u8:1+flush-179:022:45:220
3944563999890,6cyclictest4014034-21kworker/u8:1+flush-179:022:45:210
3944566999786,8cyclictest3946095-21latency_hist19:15:021
3944563999785,9cyclictest3985108-21latency_hist21:15:010
3944566999584,8cyclictest3968354-21kworker/u8:1+flush-179:021:30:251
3944563999584,9cyclictest3962300-21latency_hist20:05:010
3944563999487,5cyclictest3968354-21kworker/u8:1+flush-179:021:40:010
3944563999487,5cyclictest3954045-21kworker/u8:0+events_unbound19:45:000
3944566999384,6cyclictest3999715-21kworker/u8:3+flush-179:022:10:231
3944563999385,6cyclictest4031571-21apt-get23:40:000
3944566999180,8cyclictest3959082-21kworker/u8:1+flush-179:020:05:011
3944566998882,4cyclictest4014090-21kworker/u8:3+flush-179:023:25:231
3944566998878,7cyclictest4002898-21latency_hist22:10:001
3944563998679,5cyclictest4041960-21kworker/u8:0+flush-179:000:15:010
3944566998476,6cyclictest4038267-21kworker/u8:2+flush-179:000:05:261
3944563998474,8cyclictest3972110-21latency_hist20:35:010
3944566998276,4cyclictest3939978-21kworker/u8:1+events_unbound19:10:011
3944563998273,7cyclictest3968354-21kworker/u8:1+flush-179:021:15:220
3944566998175,5cyclictest3968354-21kworker/u8:1+flush-179:021:40:231
3944566998175,4cyclictest3986668-21kworker/u8:0+flush-179:021:35:231
3944566998170,8cyclictest3999710-21latency_hist22:00:021
3944566998170,8cyclictest3999710-21latency_hist22:00:021
3944566997972,5cyclictest4007718-21kworker/u8:3+flush-179:022:30:241
3944563997971,6cyclictest3991484-21latency_hist21:35:010
3944566997871,5cyclictest3959082-21kworker/u8:1+flush-179:020:05:301
3944563997870,5cyclictest4014090-21kworker/u8:3+events_unbound23:20:270
3944563997866,9cyclictest4020427-21latency_hist23:05:010
3944563997768,7cyclictest3999715-21kworker/u8:3+flush-179:022:10:000
3944566997668,6cyclictest3998087-21kworker/u8:0+flush-179:022:40:231
3944563997668,6cyclictest3968354-21kworker/u8:1+events_unbound21:45:240
3944563997666,7cyclictest3944524-21kworker/u8:3+flush-179:019:15:180
3944566997569,5cyclictest3968354-21kworker/u8:1+flush-179:020:54:551
3944563997568,5cyclictest3954045-21kworker/u8:0+events_unbound19:50:220
3944563997564,9cyclictest4051551-21latency_hist00:40:000
3944566997468,4cyclictest4014090-21kworker/u8:3+flush-179:023:15:191
3944566997467,5cyclictest3944521-21kworker/u8:0+flush-179:019:20:131
3944563997468,4cyclictest3959082-21kworker/u8:1+flush-179:020:10:190
3944563997466,6cyclictest3968354-21kworker/u8:1+events_unbound21:25:240
3944566997367,4cyclictest3968354-21kworker/u8:1+flush-179:020:35:001
3944563997367,4cyclictest3956479-21kworker/u8:2+flush-179:019:55:230
3944563997367,4cyclictest3956479-21kworker/u8:2+flush-179:019:55:230
3944563997363,7cyclictest3988308-21latency_hist21:25:010
3944563997363,4cyclictest3959135-21kworker/u8:3+events_unbound20:05:180
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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