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2026-02-25 - 14:36
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackeslot6.osadl.org (updated Wed Feb 25, 2026 00:44:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
37886269910895,10cyclictest266-21systemd-journal00:00:010
3788626999389,3cyclictest3863124-21kworker/u8:0+events_unbound23:00:240
3788626999282,6cyclictest3813035-21latency_hist20:25:010
3788627999183,6cyclictest3794954-21latency_hist19:30:011
3788627998574,9cyclictest3801581-21latency_hist19:50:011
3788626998574,4cyclictest3869540-21kworker/u8:3+events_unbound00:20:210
3788627998480,3cyclictest3814879-21kworker/u8:2+events_unbound20:30:251
3788627998475,6cyclictest3861279-21latency_hist22:55:011
3788626998375,6cyclictest3803425-21latency_hist19:55:010
3788627998172,7cyclictest3877464-21latency_hist23:45:021
3788627998073,3cyclictest3856761-21kworker/u8:1+events_unbound22:40:231
3788626998075,4cyclictest3800032-21kworker/u8:3+flush-179:020:05:240
3788626998072,6cyclictest3849895-21latency_hist22:20:020
3788627997970,8cyclictest3859740-21kworker/u8:2+flush-179:023:00:001
3788627997969,8cyclictest3826263-21/usr/sbin/munin21:05:241
3788627997969,8cyclictest3826263-21/usr/sbin/munin21:05:231
3788626997874,3cyclictest3869540-21kworker/u8:3+flush-179:023:45:210
3788626997768,6cyclictest3859696-21latency_hist22:50:000
3788626997768,4cyclictest3863124-21kworker/u8:0+events_unbound23:10:260
3788627997668,6cyclictest266-21systemd-journal22:40:001
3788627997570,4cyclictest3885506-21kworker/u8:2+events_unbound00:15:141
3788626997570,4cyclictest3859674-21kworker/u8:0+flush-179:022:50:220
3788627997469,4cyclictest3819639-21kworker/u8:2+events_unbound20:50:191
3788626997369,3cyclictest3863124-21kworker/u8:0+flush-179:023:15:230
3788626997369,3cyclictest3830800-21kworker/u8:3+events_unbound21:35:190
3788626997368,4cyclictest3883842-21kworker/u8:1+events_unbound00:15:240
3788626997368,4cyclictest3869540-21kworker/u8:3+flush-179:000:35:230
3788626997368,4cyclictest3799972-21kworker/u8:0+events_unbound19:55:210
3788626997363,4cyclictest3885506-21kworker/u8:2+events_unbound00:10:240
3788627997268,3cyclictest3799972-21kworker/u8:0+flush-179:019:44:551
3788627997267,4cyclictest3800032-21kworker/u8:3+events_unbound20:10:241
3788626997268,3cyclictest3804988-21kworker/u8:1+flush-179:020:15:200
3788626997267,4cyclictest3819639-21kworker/u8:2+flush-179:020:55:230
3788626997166,4cyclictest3774598-21kworker/u8:1+events_unbound19:20:180
3788627997063,5cyclictest3890283-21kworker/u8:0+flush-179:000:40:001
3788627996965,3cyclictest3838795-21kworker/u8:2+events_unbound22:30:191
3788626996965,3cyclictest3825500-21kworker/u8:0+events_unbound21:15:200
3788626996960,7cyclictest266-21systemd-journal20:34:550
3788626996960,4cyclictest3838795-21kworker/u8:2+events_unbound22:20:200
3788627996864,3cyclictest3797874-21kworker/u8:2+events_unbound19:50:201
3788627996863,4cyclictest3869540-21kworker/u8:3+flush-179:000:34:551
3788627996859,6cyclictest3819660-21latency_hist20:45:011
3788626996864,3cyclictest3883842-21kworker/u8:1+flush-179:000:05:190
3788626996863,4cyclictest3890283-21kworker/u8:0+events_unbound00:30:190
3788626996863,4cyclictest3818032-21kworker/u8:1+events_unbound21:00:250
3788626996863,4cyclictest3774598-21kworker/u8:1+flush-179:019:19:550
3788626996860,3cyclictest3774598-21kworker/u8:1+events_unbound19:10:190
3788627996763,3cyclictest3841962-21kworker/u8:3+events_unbound22:00:261
3788627996763,3cyclictest3787036-21kworker/u8:0+flush-179:019:24:551
3788627996759,6cyclictest3848311-21kworker/u8:3+flush-179:022:30:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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