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2026-02-17 - 14:56
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackeslot6.osadl.org (updated Tue Feb 17, 2026 00:44:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
23558499910696,8cyclictest2375746-21kworker/u8:0+flush-179:020:20:001
23558469910292,8cyclictest2384958-21latency_hist20:40:010
23558499910088,9cyclictest2415256-21latency_hist22:15:001
2355849999889,7cyclictest2389753-21kworker/u8:3+flush-179:021:10:001
2355849999791,4cyclictest2355789-21kworker/u8:0+flush-179:019:35:001
2355846999686,8cyclictest2421888-21latency_hist22:35:020
2355846999685,9cyclictest2391317-21apt-get20:57:570
2355849998983,5cyclictest2396182-21kworker/u8:1+events_unbound21:20:011
2355849998376,5cyclictest2360553-21kworker/u8:1+flush-179:019:40:001
2355849998273,6cyclictest2431744-21kworker/u8:2+flush-179:023:50:001
2355849998272,7cyclictest2407280-21kworker/u8:0+flush-179:022:00:001
2355846998272,7cyclictest2431709-21latency_hist23:05:010
2355846998271,9cyclictest2366929-21latency_hist19:45:010
2355849998074,4cyclictest2408865-21kworker/u8:2+flush-179:022:10:011
2355849998069,8cyclictest2384963-21kworker/u8:1+events_unbound20:50:011
2355849997767,4cyclictest2373796-21kworker/u8:4+events_unbound20:15:001
2355849997671,4cyclictest2442892-21kworker/u8:3+flush-179:023:45:001
2355849997571,3cyclictest2434914-21kworker/u8:1+events_unbound23:35:231
2355849997469,4cyclictest2427163-21kworker/u8:1+flush-179:022:55:001
2355849997368,4cyclictest2431744-21kworker/u8:2+flush-179:023:15:241
2355849997366,5cyclictest2360553-21kworker/u8:1+events_unbound19:40:241
2355849997264,6cyclictest2375746-21kworker/u8:0+flush-179:020:50:251
2355846997061,7cyclictest2407301-21latency_hist21:50:000
2355846997061,6cyclictest266-21systemd-journal19:20:010
2355846996955,10cyclictest266-21systemd-journal00:00:010
2355849996861,6cyclictest2446683-21kworker/u8:0+flush-179:000:00:251
2355849996858,4cyclictest2368758-21kworker/u8:0+events_unbound19:50:001
2355849996761,4cyclictest2452491-21kworker/u8:0+flush-179:000:10:221
2355849996759,6cyclictest2420311-21kworker/u8:4+events_unbound22:45:131
2355849996758,6cyclictest2370395-21kworker/u8:2+events_unbound20:05:151
2355846996759,6cyclictest2394560-21latency_hist21:10:000
2355849996662,3cyclictest2389753-21kworker/u8:3+flush-179:021:00:221
2355849996661,3cyclictest2431744-21kworker/u8:2+events_unbound23:30:231
2355849996659,5cyclictest2360553-21kworker/u8:1+events_unbound19:55:151
2355846996653,10cyclictest2460964-21diskstats00:35:150
2355849996560,4cyclictest2420311-21kworker/u8:4+events_unbound22:30:221
2355849996560,4cyclictest2355791-21kworker/u8:2+flush-179:019:14:551
2355849996559,5cyclictest2427163-21kworker/u8:1+events_unbound23:00:011
2355849996459,4cyclictest2415234-21kworker/u8:1+flush-179:022:15:211
2355849996458,4cyclictest2458823-21latency_hist00:30:011
2355849996458,4cyclictest2360553-21kworker/u8:1+events_unbound20:00:131
2355849996457,5cyclictest2431744-21kworker/u8:2+events_unbound23:25:181
2355849996456,6cyclictest2420311-21kworker/u8:4+events_unbound23:10:211
2355849996455,7cyclictest2408865-21kworker/u8:2+flush-179:022:00:211
2355849996359,3cyclictest2455661-21kworker/u8:3+flush-179:000:35:261
2355849996256,4cyclictest2423800-21kworker/u8:0+flush-179:023:05:161
2355849996256,4cyclictest2420311-21kworker/u8:4+flush-179:023:00:151
2355849996255,6cyclictest2375746-21kworker/u8:0+events_unbound20:40:231
2355849996255,5cyclictest2392962-21kworker/u8:0+events_unbound21:35:141
2355849996254,5cyclictest2447652-21kworker/u8:1+flush-179:000:05:211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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