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2025-11-30 - 19:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackeslot6.osadl.org (updated Sun Nov 30, 2025 12:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31935879910091,7cyclictest3234568-21kworker/u8:1+flush-179:009:55:001
3193584999482,9cyclictest3198260-21latency_hist07:25:010
3193587998982,4cyclictest3277625-21kworker/u8:1+events_unbound11:30:251
3193584998879,7cyclictest3229555-21latency_hist09:00:010
3193584998681,4cyclictest3234568-21kworker/u8:1+flush-179:009:20:010
3193584998674,10cyclictest3277625-21kworker/u8:1+flush-179:012:40:000
3193587998476,6cyclictest3210494-21kworker/u8:0+flush-179:008:35:221
3193587998176,3cyclictest3223359-21kworker/u8:2+flush-179:008:45:251
3193587998175,4cyclictest3211573-21kworker/u8:3+flush-179:008:05:221
3193584998175,5cyclictest3193493-21kworker/u8:1+events_unbound08:00:240
3193584998175,4cyclictest3246030-21kworker/u8:0+flush-179:010:00:000
3193587998074,4cyclictest3193493-21kworker/u8:1+flush-179:008:00:001
3193587998073,5cyclictest3240789-21kworker/u8:0+flush-179:009:40:001
3193584998074,5cyclictest3277625-21kworker/u8:1+flush-179:012:10:250
3193587997975,3cyclictest3237615-21kworker/u8:3+flush-179:009:35:011
3193587997974,4cyclictest3277625-21kworker/u8:1+flush-179:012:35:251
3193587997972,5cyclictest3234568-21kworker/u8:1+events_unbound09:20:221
3193587997868,6cyclictest3193493-21kworker/u8:1+events_unbound07:35:011
3193584997872,4cyclictest3210494-21kworker/u8:0+flush-179:008:15:240
3193587997569,4cyclictest3193493-21kworker/u8:1+flush-179:007:30:001
3193587997468,4cyclictest3205206-21kworker/u8:0+flush-179:007:50:161
3193587997368,3cyclictest3280869-21kworker/u8:3+flush-179:011:50:141
3193587997367,5cyclictest3223359-21kworker/u8:2+flush-179:008:40:261
3193587997267,4cyclictest3234568-21kworker/u8:1+flush-179:009:40:231
3193587997267,4cyclictest3234568-21kworker/u8:1+flush-179:009:40:221
3193584997268,3cyclictest3289089-21kworker/u8:3+events_unbound12:25:010
3193584997265,6cyclictest3187442-21kworker/u8:0+events_unbound07:25:010
3193584997165,4cyclictest3289089-21kworker/u8:3+flush-179:012:15:160
3193584997162,6cyclictest3193493-21kworker/u8:1+flush-179:007:35:230
3193584997159,9cyclictest3214736-21kworker/u8:1+flush-179:008:40:160
3193584997065,4cyclictest3187442-21kworker/u8:0+events_unbound07:10:230
3193584997065,4cyclictest3187442-21kworker/u8:0+events_unbound07:10:230
3193587996960,7cyclictest3246030-21kworker/u8:0+flush-179:009:55:261
3193587996862,4cyclictest3284297-21kworker/u8:2+flush-179:012:05:001
3193587996862,4cyclictest3214736-21kworker/u8:1+events_unbound09:00:231
3193587996857,8cyclictest3256944-21latency_hist10:25:011
3193584996862,4cyclictest3261690-21kworker/u8:2+flush-179:010:45:230
3193584996861,6cyclictest3214736-21kworker/u8:1+flush-179:008:25:230
3193587996763,3cyclictest3269715-21kworker/u8:3+flush-179:011:10:271
3193587996761,4cyclictest3273299-21kworker/u8:0+events_unbound11:35:251
3193584996762,4cyclictest3249007-21kworker/u8:2+events_unbound10:15:230
3193584996759,7cyclictest3229808-21kworker/u8:2+flush-179:009:05:010
3193584996660,4cyclictest3234568-21kworker/u8:1+events_unbound10:05:170
3193587996561,3cyclictest3269715-21kworker/u8:3+flush-179:011:15:251
3193587996560,4cyclictest3277625-21kworker/u8:1+flush-179:012:15:001
3193587996559,4cyclictest3244131-21kworker/u8:2+flush-179:009:45:201
3193587996456,6cyclictest3214736-21kworker/u8:1+flush-179:008:55:211
3193587996456,5cyclictest3214736-21kworker/u8:1+flush-179:009:05:161
3193587996454,8cyclictest3263553-21/usr/sbin/munin10:45:251
3193584996460,3cyclictest3277625-21kworker/u8:1+flush-179:011:55:570
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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