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2026-06-28 - 18:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackeslot6.osadl.org (updated Sun Jun 28, 2026 12:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17805799130119,8cyclictest203725-21latency_hist08:30:010
17806199126115,8cyclictest276688-21latency_hist12:15:011
17805799121111,7cyclictest198942-21latency_hist08:15:000
17806199120113,6cyclictest226228-21kworker/u8:0+flush-179:010:00:011
17806199115108,5cyclictest226228-21kworker/u8:0+events_unbound09:45:001
17806199112106,4cyclictest177988-21kworker/u8:2+flush-179:007:25:251
1780579911299,10cyclictest1213033-21systemd-journal12:25:000
1780619910790,5cyclictest236373-21kworker/u8:1+events_unbound10:45:001
17806199107100,4cyclictest241156-21kworker/u8:2+events_unbound10:30:241
17806199106101,4cyclictest236373-21kworker/u8:1+flush-179:010:35:261
1780619910495,6cyclictest215131-21latency_hist09:05:011
1780619910397,4cyclictest210332-21kworker/u8:1+events_unbound08:50:221
1780619910394,7cyclictest268478-21latency_hist11:50:001
1780619910194,5cyclictest241156-21kworker/u8:2+events_unbound10:30:021
1780619910194,5cyclictest241156-21kworker/u8:2+events_unbound10:30:011
1780619910095,4cyclictest268512-21kworker/u8:3+events_unbound12:00:241
1780619910095,4cyclictest265274-21kworker/u8:2+flush-179:012:25:261
1780619910093,6cyclictest241156-21kworker/u8:2+events_unbound10:25:011
1780619910093,6cyclictest241156-21kworker/u8:2+events_unbound10:25:011
1780619910093,5cyclictest254195-21kworker/u8:0+flush-179:011:25:211
1780619910089,8cyclictest192833-21apt-get07:55:121
178061999992,5cyclictest276721-21kworker/u8:0+events_unbound12:20:171
178061999991,6cyclictest249414-21kworker/u8:0+flush-179:010:50:251
178057999993,4cyclictest177988-21kworker/u8:2+events_unbound07:35:210
178057999993,4cyclictest177988-21kworker/u8:2+events_unbound07:35:200
178057999889,7cyclictest262112-21latency_hist11:30:010
178057999888,7cyclictest233451-21kworker/u8:1+flush-179:010:00:250
178061999788,6cyclictest225189-21latency_hist09:35:011
178057999585,7cyclictest265274-21kworker/u8:2+flush-179:012:10:140
178061999488,4cyclictest268512-21kworker/u8:3+flush-179:012:05:251
178061999486,6cyclictest216954-21kworker/u8:2+flush-179:009:10:201
178057999382,8cyclictest255745-21latency_hist11:10:000
178061999287,3cyclictest257318-21kworker/u8:1+flush-179:011:20:151
178061999282,7cyclictest241156-21kworker/u8:2+flush-179:010:45:211
178061999185,4cyclictest257318-21kworker/u8:1+flush-179:011:50:201
178061999083,5cyclictest257318-21kworker/u8:1+events_unbound11:55:141
178061998984,4cyclictest187594-21kworker/u8:0+flush-179:008:04:551
178061998983,4cyclictest216954-21kworker/u8:2+events_unbound09:15:241
178061998980,6cyclictest200588-21kworker/u8:1+flush-179:008:30:211
178057998979,7cyclictest241156-21kworker/u8:2+events_unbound10:45:240
178061998881,6cyclictest283311-21kworker/u8:2+flush-179:012:40:001
178061998881,5cyclictest163642-21kworker/u8:1+flush-179:007:10:161
178061998781,5cyclictest265274-21kworker/u8:2+flush-179:012:15:221
178061998780,5cyclictest185916-21kworker/u8:3+events_unbound07:50:131
178061998779,6cyclictest236373-21kworker/u8:1+flush-179:010:10:001
178061998777,8cyclictest179815-21apt-get07:15:121
178057998758,28cyclictest0-21swapper/008:50:590
178057998575,7cyclictest200585-21kworker/u8:0+flush-179:008:20:220
178061998479,4cyclictest195806-21kworker/u8:3+flush-179:008:09:561
178057998472,8cyclictest185916-21kworker/u8:3+flush-179:007:50:210
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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