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2026-07-05 - 03:08

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #f, slot #5

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackfslot5s.osadl.org (updated Sat Jul 04, 2026 12:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
24735995138,8cyclictest0-21swapper/11
24735995036,9cyclictest0-21swapper/11
24735995035,10cyclictest0-21swapper/11
24735995034,10cyclictest0-21swapper/11
24741994940,5cyclictest0-21swapper/11
24741994839,5cyclictest0-21swapper/11
24735994832,11cyclictest0-21swapper/11
24735994738,5cyclictest0-21swapper/11
24735994734,8cyclictest0-21swapper/11
24735994733,9cyclictest0-21swapper/11
24735994733,9cyclictest0-21swapper/11
24735994733,9cyclictest0-21swapper/11
24735994733,9cyclictest0-21swapper/11
24735994731,10cyclictest0-21swapper/11
24735994731,10cyclictest0-21swapper/11
24741994637,5cyclictest0-21swapper/11
24741994637,5cyclictest0-21swapper/11
24741994637,5cyclictest0-21swapper/11
24735994637,5cyclictest0-21swapper/11
24735994636,5cyclictest0-21swapper/11
24735994633,8cyclictest0-21swapper/11
24735994633,8cyclictest0-21swapper/11
24735994629,11cyclictest0-21swapper/11
24741994537,4cyclictest0-21swapper/11
24735994536,5cyclictest0-21swapper/11
24735994536,5cyclictest0-21swapper/11
24735994535,5cyclictest0-21swapper/11
24735994531,9cyclictest0-21swapper/11
24735994529,10cyclictest0-21swapper/11
24741994434,5cyclictest0-21swapper/11
24735994435,5cyclictest0-21swapper/11
24735994434,5cyclictest0-21swapper/11
24735994431,8cyclictest0-21swapper/11
24735994431,8cyclictest0-21swapper/11
24735994429,10cyclictest0-21swapper/11
24741994334,5cyclictest0-21swapper/11
24735994334,5cyclictest0-21swapper/11
24735994334,5cyclictest0-21swapper/11
24741994232,5cyclictest0-21swapper/11
24735994233,5cyclictest0-21swapper/11
24735994233,5cyclictest0-21swapper/11
24735994233,4cyclictest0-21swapper/11
24735994232,5cyclictest0-21swapper/11
24735994232,5cyclictest0-21swapper/11
24735994229,8cyclictest0-21swapper/11
24735994133,5cyclictest0-21swapper/11
24735994133,5cyclictest0-21swapper/11
24735994132,5cyclictest0-21swapper/11
24735994132,5cyclictest0-21swapper/11
24735994131,5cyclictest0-21swapper/11
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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