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2026-05-06 - 00:25

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #f, slot #5

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackfslot5s.osadl.org (updated Tue May 05, 2026 12:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20874994929,14cyclictest0-21swapper/11
20874994630,12cyclictest0-21swapper/11
20874994528,11cyclictest0-21swapper/11
20865994535,5cyclictest0-21swapper/11
20865994434,5cyclictest0-21swapper/11
20874994328,10cyclictest0-21swapper/11
20874994327,11cyclictest0-21swapper/11
20874994327,10cyclictest0-21swapper/11
20874994226,11cyclictest0-21swapper/11
20874994225,11cyclictest0-21swapper/11
20874994225,11cyclictest0-21swapper/11
20865994232,5cyclictest0-21swapper/11
20874994128,8cyclictest0-21swapper/11
20874994127,9cyclictest0-21swapper/11
20874994126,9cyclictest0-21swapper/11
20874994126,10cyclictest0-21swapper/11
20874994125,11cyclictest0-21swapper/11
20874994125,10cyclictest0-21swapper/11
20874994124,11cyclictest0-21swapper/11
20874994121,14cyclictest0-21swapper/11
20874994027,8cyclictest0-21swapper/11
20874994026,9cyclictest0-21swapper/11
20874994026,8cyclictest0-21swapper/11
20874994026,10cyclictest0-21swapper/11
20874994025,9cyclictest0-21swapper/11
20874994025,10cyclictest0-21swapper/11
20874994024,11cyclictest0-21swapper/11
20874994024,11cyclictest0-21swapper/11
20874994024,10cyclictest0-21swapper/11
20874994024,10cyclictest0-21swapper/11
20874994023,11cyclictest0-21swapper/11
20865994031,5cyclictest0-21swapper/11
20874993926,8cyclictest0-21swapper/11
20874993925,9cyclictest0-21swapper/11
20874993925,11cyclictest0-21swapper/11
20874993924,9cyclictest0-21swapper/11
20874993924,9cyclictest0-21swapper/11
20874993924,10cyclictest0-21swapper/11
20874993923,10cyclictest0-21swapper/11
20874993922,11cyclictest0-21swapper/11
20874993921,12cyclictest0-21swapper/11
20865993930,5cyclictest0-21swapper/11
20874993824,9cyclictest0-21swapper/11
20874993824,8cyclictest0-21swapper/11
20874993823,9cyclictest0-21swapper/11
20874993822,10cyclictest0-21swapper/11
20874993822,10cyclictest0-21swapper/11
20865993829,5cyclictest0-21swapper/11
20874993724,8cyclictest0-21swapper/11
20874993722,9cyclictest0-21swapper/11
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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