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2026-03-06 - 22:55

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #f, slot #5

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackfslot5s.osadl.org (updated Fri Mar 06, 2026 12:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19909995439,10cyclictest0-21swapper/11
19909995337,11cyclictest0-21swapper/11
19909995136,10cyclictest0-21swapper/11
19909995135,11cyclictest0-21swapper/11
19909995037,9cyclictest0-21swapper/11
19909995036,9cyclictest0-21swapper/11
19909995035,10cyclictest0-21swapper/11
19909994936,8cyclictest0-21swapper/11
19909994936,7cyclictest0-21swapper/11
19909994934,10cyclictest0-21swapper/11
19909994934,10cyclictest0-21swapper/11
19909994834,9cyclictest0-21swapper/11
19909994834,9cyclictest0-21swapper/11
19909994831,11cyclictest0-21swapper/11
19909994735,7cyclictest0-21swapper/11
19909994733,9cyclictest0-21swapper/11
19909994731,10cyclictest0-21swapper/11
19909994636,5cyclictest0-21swapper/11
19909994633,8cyclictest0-21swapper/11
19909994633,7cyclictest0-21swapper/11
19909994631,9cyclictest0-21swapper/11
19909994631,9cyclictest0-21swapper/11
19912994535,5cyclictest0-21swapper/11
19909994536,5cyclictest0-21swapper/11
19909994535,5cyclictest0-21swapper/11
19909994535,5cyclictest0-21swapper/11
19909994535,5cyclictest0-21swapper/11
19909994532,7cyclictest0-21swapper/11
19909994531,9cyclictest0-21swapper/11
19906994536,5cyclictest0-21swapper/11
19906994535,5cyclictest0-21swapper/11
19906994535,5cyclictest0-21swapper/11
19906994535,5cyclictest0-21swapper/11
19906994535,5cyclictest0-21swapper/11
19909994434,5cyclictest0-21swapper/11
19909994429,9cyclictest0-21swapper/11
19906994434,5cyclictest0-21swapper/11
19906994434,5cyclictest0-21swapper/11
19912994334,5cyclictest0-21swapper/11
19909994333,5cyclictest0-21swapper/11
19909994330,8cyclictest0-21swapper/11
19909994329,8cyclictest0-21swapper/11
19909994329,8cyclictest0-21swapper/11
19909994328,9cyclictest0-21swapper/11
19906994334,4cyclictest0-21swapper/11
19906994333,5cyclictest0-21swapper/11
19906994332,5cyclictest0-21swapper/11
19909994233,5cyclictest0-21swapper/11
19909994232,5cyclictest0-21swapper/11
19909994232,5cyclictest0-21swapper/11
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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