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2026-02-19 - 18:05
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #f, slot #5

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackfslot5s.osadl.org (updated Thu Feb 19, 2026 12:43:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26487994633,8cyclictest0-21swapper/11
26487994633,8cyclictest0-21swapper/11
26487994632,9cyclictest0-21swapper/11
26492994535,5cyclictest0-21swapper/11
26487994527,12cyclictest0-21swapper/11
26487994526,13cyclictest0-21swapper/11
26487994526,13cyclictest0-21swapper/11
26492994435,5cyclictest0-21swapper/11
26492994434,5cyclictest0-21swapper/11
26487994434,5cyclictest0-21swapper/11
26487994426,12cyclictest0-21swapper/11
26487994329,8cyclictest0-21swapper/11
26487994328,10cyclictest0-21swapper/11
26487994327,10cyclictest0-21swapper/11
26487994326,11cyclictest0-21swapper/11
26487994325,12cyclictest0-21swapper/11
26487994232,5cyclictest0-21swapper/11
26487994228,8cyclictest0-21swapper/11
26487994226,10cyclictest0-21swapper/11
26487994224,12cyclictest0-21swapper/11
26492994131,5cyclictest0-21swapper/11
26492994131,5cyclictest0-21swapper/11
26492994131,5cyclictest0-21swapper/11
26492994131,5cyclictest0-21swapper/11
26492994131,5cyclictest0-21swapper/11
26492994131,5cyclictest0-21swapper/11
26487994125,10cyclictest0-21swapper/11
26487994125,10cyclictest0-21swapper/11
26487994124,12cyclictest0-21swapper/11
26487994124,11cyclictest0-21swapper/11
26487994123,12cyclictest0-21swapper/11
26487994123,12cyclictest0-21swapper/11
26492994032,5cyclictest0-21swapper/11
26492994031,5cyclictest0-21swapper/11
26492994030,5cyclictest0-21swapper/11
26492994030,5cyclictest0-21swapper/11
26492994030,5cyclictest0-21swapper/11
26487994030,5cyclictest0-21swapper/11
26487994030,5cyclictest0-21swapper/11
26487994028,7cyclictest0-21swapper/11
26487994026,8cyclictest0-21swapper/11
26487994025,9cyclictest0-21swapper/11
26487994024,11cyclictest0-21swapper/11
26487994024,10cyclictest0-21swapper/11
26487994024,10cyclictest0-21swapper/11
26487994024,10cyclictest0-21swapper/11
26492993929,5cyclictest0-21swapper/11
26492993929,5cyclictest0-21swapper/11
26487993929,5cyclictest0-21swapper/11
26487993927,7cyclictest0-21swapper/11
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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