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2026-06-18 - 20:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot4.osadl.org (updated Thu Jun 18, 2026 12:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
24061932262185,28sleep10-21swapper/107:09:451
24058192253180,58sleep00-21swapper/007:05:460
24475802620,3sleep12447431-21python308:50:011
179699510,3rtkit-daemon0-21swapper/109:22:281
24636532500,4sleep02463657-21cpuspeed_turbos09:20:140
179699480,5rtkit-daemon2506438-21ssh10:18:191
25173672430,1sleep00-21swapper/010:33:370
2406349994114,6cyclictest26-21ksoftirqd/112:25:001
2406349994014,5cyclictest26-21ksoftirqd/112:30:001
2406349993914,5cyclictest26-21ksoftirqd/112:15:021
240634499389,6cyclictest13-21ksoftirqd/012:25:200
2406344993812,10cyclictest13-21ksoftirqd/011:50:120
2406349993715,7cyclictest26-21ksoftirqd/107:30:011
240634499378,6cyclictest13-21ksoftirqd/011:20:200
2406349993614,7cyclictest26-21ksoftirqd/110:15:011
2406349993612,4cyclictest26-21ksoftirqd/111:15:221
2406344993614,7cyclictest13-21ksoftirqd/011:35:010
2406349993513,6cyclictest26-21ksoftirqd/108:45:011
240634999348,5cyclictest26-21ksoftirqd/111:01:021
2406349993413,6cyclictest26-21ksoftirqd/110:20:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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