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2024-04-26 - 09:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot3.osadl.org (updated Fri Apr 26, 2024 00:46:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1739422200,6sleep10-21swapper/119:05:271
576981810,68rtkit-daemon0-21swapper/219:07:522
8255911230,51ptp4l401ktimersoftd/319:05:143
1652821190,8sleep21861199cyclictest23:40:132
2306021120,2sleep20-21swapper/222:45:172
1363121100,3sleep10-21swapper/122:25:131
1142421070,3sleep1231rcuc/123:30:011
8255911040,2ptp4l11386-21ptp4l20:00:303
114622970,5sleep3391rcuc/323:30:103
1861099708,15cyclictest8538-21sed22:15:001
1861099689,15cyclictest16664-21mailstats21:20:271
1861099688,14cyclictest4420-21latency_hist23:15:011
1861099687,14cyclictest23577-21ptp4l-jitter21:35:311
1861099657,13cyclictest27935-21date21:45:251
1861099657,13cyclictest25506-21cpu00:00:111
1861099657,12cyclictest22610-21cat22:45:121
18612996431,10cyclictest41-21ksoftirqd/323:00:013
18612996430,10cyclictest41-21ksoftirqd/323:15:003
1861099649,13cyclictest16367-21sed20:10:331
1861099647,14cyclictest17998-21cpu22:35:111
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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