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2021-07-24 - 21:47

Dates and Events:

OSADL Articles:

2021-02-09 12:00

Open Source OPC UA PubSub over TSN project phase #3 launched

Letter of Intent with call for participation is now available


2016-11-12 12:00

Raspberry Pi and real-time Linux

Let's have a look at the OSADL QA Farm data


2016-09-17 12:00

Preemption latency of real-time Linux systems

How to measure it – and how to fix it, if it's too high?



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OSADL QA Farm on Real-time of Mainline Linux

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Number of cores/hyperthreads and bogoMIPS (x86 CPU strings, Intel names)

BoxArchCoresMHzBogo​MIPSEffective
r0s0x86_​644 x 225004000024.07. 13:10
r0s1x86_​644 x 223005599224.07. 13:10
r0s1sx86_​644 x 233005280024.07. 13:10
r0s2x86_​644 x 235005587224.07. 13:11
r0s2sx86_​648 x 2360011520022.12. 13:11
r0s3x86_​648 x 2360011520024.07. 13:11
r0s4x86_​642 x 237002952824.07. 13:12
r0s4sx86_​646 x 236008640024.07. 13:12
r0s5x86_​648 x 2350011520024.07. 13:13
r0s5sx86_​644 x 234005439224.07. 13:13
r0s6x86_​648 x 2360011520024.07. 13:14
r0s6sx86_​648 x 2360011520024.07. 13:14
r0s7x86_​648 x 2360011520024.07. 13:14
r0s7sx86_​648 x 2360011520024.07. 13:15
r0s8x86_​648 x 2360011520024.07. 13:15
r0s8sx86_​646 x 234708337624.07. 13:16
r1s0x86_​644 x 131002479624.07. 13:16
r1s1x86_​642 x 226002169624.07. 13:17
r1s2x86_​644 x 123002799624.07. 13:17
r1s3x86_​644 x 235005600026.05. 01:16
r1s3sx86_​644 x 235005600026.05. 01:16
r1s4arm​v7l2 x 112004824.07. 13:18
r1s4sarm​v7l2 x 14004824.07. 13:18
r1s5aarch​644 x 1120079624.07. 13:19
r1s6x86_​642 x 221301706424.07. 13:19
r1s6sx86_​642 x 216671333224.07. 13:19
r1s7arm​v6l1 x 1166753002.05. 01:22
r1s8i6861 x 21600639824.07. 13:21
r1s8sx86_​644 x 119001519624.07. 13:21
r2s0x86_​644 x 131002480024.07. 13:21
r2s1arm​v5tejl1 x 120019924.07. 13:22
r2s2arm​v7l1 x 172049924.07. 13:22
r2s3arm​v7l1 x 160049524.07. 13:22
r2s4mips​641 x 180053110.01. 01:23
r2s5ppc1 x 13966626.01. 13:22
r2s6i6861 x 11500299924.07. 13:23
r2s6sx86_​644 x 119901599209.02. 01:27
r2s7x86_​644 x 137002960010.03. 13:24
r2s8ppc1 x 14006609.07. 01:27
r3s0i6864 x 235005599224.07. 13:30
r3s1i6864 x 124001912824.07. 13:30
r3s2i6861 x 11530306209.03. 13:27
r3s2sx86_​641 x 11800359009.03. 13:27
r3s3x86_​646 x 233338000424.07. 13:31
r3s4x86_​641 x 21400560010.01. 01:28
r3s5i5861 x 113326515.07. 13:29
r3s5sppc2 x 1120040017.03. 01:27
r3s6x86_​641 x 21660666624.07. 13:32
r3s6sx86_​642 x 226672133224.07. 13:33
r3s7i6861 x 1533106624.07. 13:33
r3s8i6866 x 132003852624.07. 13:34
r4s0x86_​642 x 223001839624.07. 13:35
r4s1arm​v7l4 x 11500108023.07. 13:36
r4s1sarm​v7l4 x 11500108024.07. 13:35
r4s2arm​v7l1 x 180039824.07. 13:36
r4s2sarm​v7l1 x 180053024.07. 13:38
r4s3i5861 x 150099624.07. 13:39
r4s3si6861 x 11466293213.06. 13:41
r4s4ppc4 x 1120049824.07. 13:41
r4s5arm​v7l1 x 1500024.07. 13:43
r4s5saarch​644 x 1160020030.01. 13:41
r4s6x86_​644 x 234005425624.07. 13:43
r4s6sarm​v7l0 x 1 x 110006624.07. 13:43
r4s7i6864 x 118331466424.07. 13:44
r4s7sx86_​642 x 11833733224.07. 13:44
r4s8arm​v7l1 x 140039824.07. 13:45
r4s8sarm​v7l1 x 140039824.07. 13:45
r5s0x86_​642 x 222001758224.07. 13:46
r5s1x86_​646 x 133334009224.07. 13:46
r5s2x86_​644 x 127002169911.06. 13:48
r5s2sx86_​644 x 240006386312.04. 01:34
r5s3x86_​644 x 220003187224.07. 13:46
r5s3sx86_​644 x 116001274824.07. 13:47
r5s4x86_​642 x 225302026424.07. 13:47
r5s4si6862 x 225302026511.06. 13:50
r5s5arm​v7l1 x 160059724.07. 13:48
r5s5sarm​v7l1 x 160060024.07. 13:50
r5s6ppc1 x 153313324.07. 13:53
r5s7arm​v7l1 x 15286424.07. 13:53
r5s7sarm​v7l1 x 15284824.07. 13:54
r5s8ppc1 x 1400263715.07. 01:50
r6s0x86_​642 x 10 x 2170013614024.07. 13:56
r6s1x86_​642 x 12000797824.07. 13:56
r6s2x86_​642 x 11667957802.01. 13:55
r6s3x86_​644 x 222003512024.07. 13:57
r6s4x86_​642 x 11100437614.07. 13:55
r6s5i6861 x 11500299224.07. 13:57
r6s6i6861 x 11600319124.07. 13:58
r6s7i6862 x 12300917624.07. 13:59
r6s8x86_​642 x 223001835624.07. 13:59
r7s0x86_​642 x 223001840024.07. 13:59
r7s1x86_​644 x 116001284024.07. 14:00
r7s2i6861 x 1600119619.07. 13:52
r7s2sarm​v7l4 x 11500108020.07. 01:53
r7s3arm​v6l1 x 1700524.07. 14:00
r7s3sarm​v7l4 x 1140035624.07. 14:02
r7s4arm​v7l1 x 153634831.05. 14:00
r7s5i6861 x 11300259324.07. 14:03
r7s5sarm​v7l2 x 140040010.04. 13:59
r7s6arm​v7l1 x 1100039830.05. 02:03
r7s7x86_​644 x 116001276724.07. 14:04
r7s7sx86_​642 x 223001844824.07. 14:04
r7s8arm​v7l1 x 1100099524.07. 14:05
r7s8sarm​v7l1 x 1100079624.07. 14:05
r8s0x86_​642 x 223001840024.07. 14:05
r8s1i5861 x 130060124.07. 14:06
r8s2x86_​642 x 221001676024.07. 14:07
r8s2sx86_​642 x 221001676024.07. 14:07
r8s3x86_​644 x 126672127724.07. 14:07
r8s4i6864 x 118331466424.07. 14:08
r8s4si6862 x 11833733226.03. 14:13
r8s5i6864 x 234005440024.07. 14:08
r8s6arm​v7l1 x 150049824.07. 14:09
r8s7x86_​642 x 127001077624.07. 14:09
r8s7sx86_​642 x 133001324824.07. 14:09
r8s8x86_​642 x 11300514424.07. 14:10
r9s0x86_​642 x 223001840024.07. 14:10
r9s1x86_​642 x 12000399224.07. 14:11
r9s1sarm​v7l1 x 1125022.07. 09:38
r9s2x86_​644 x 116001274824.07. 14:11
r9s3x86_​644 x 116001274824.07. 14:12
r9s3sx86_​644 x 130002400024.07. 14:12
r9s4i6861 x 21000398824.07. 14:13
r9s4sx86_​642 x 11333534724.07. 14:13
r9s5x86_​642 x 127001077624.07. 14:14
r9s5sx86_​644 x 234005439224.07. 14:14
r9s6x86_​642 x 230002396724.07. 14:14
r9s7arm​v7l2 x 11000024.07. 14:15
r9s8arm​v7l1 x 160059725.06. 02:14
r9s8sarm​v7l1 x 180079624.07. 14:15
ras0x86_​642 x 223001841724.07. 14:16
ras1i6861 x 11400279924.07. 14:16
ras2x86_​642 x 11067426624.07. 14:17
ras3aarch​648 x 12000400024.07. 14:17
ras3sarm​v7l8 x 1130074421.05. 14:08
ras4arm​v7l1 x 150039805.08. 02:11
ras4sarm​v7l1 x 160059707.02. 02:45
ras5arm​v7l2 x 110002424.07. 14:18
ras5sarm​v7l2 x 110002420.07. 02:13
ras6arm​v7l1 x 11000198724.07. 14:18
ras6sarm​v7l1 x 11000198724.07. 14:18
ras7ppc1 x 13966524.07. 14:19
ras8i6862 x 125001077425.06. 02:24
ras8sx86_​644 x 116001274824.07. 14:19
rbs0i6862 x 225001760024.07. 14:19
rbs1x86_​644 x 131002479624.07. 14:20
rbs2x86_​644 x 232005120024.07. 14:20
rbs3arm​v7l4 x 190017604.06. 02:22
rbs3sarm​v7l4 x 1140035624.07. 14:21
rbs4x86_​644 x 11200960010.06. 14:25
rbs4sx86_​644 x 116001274824.07. 14:22
rbs5i6864 x 220004941424.07. 14:22
rbs5saarch​644 x 118006424.07. 14:22
rbs6x86_​644 x 119151532424.07. 14:23
rbs6sx86_​642 x 11333533224.07. 14:24
rbs7arm​v7l4 x 19964803.05. 02:22
rbs7sarm​v7l4 x 1996632406.06. 14:27
rbs8arm​v7l2 x 1666265024.07. 14:25
rbs8sx86_​644 x 227004319224.07. 14:25
rcs0x86_​648 x 224007736824.07. 14:26
rcs1x86_​646 x 234678327124.07. 14:26
rcs2x86_​642 x 128001123224.07. 14:27
rcs3i6862 x 11400558624.07. 14:27
rcs3sx86_​644 x 233005269624.07. 14:28
rcs4x86_​642 x 11100437624.07. 14:29
rcs4sx86_​644 x 11100875224.07. 14:30
rcs5x86_​642 x 128001119824.07. 14:30
rcs5sx86_​642 x 128001119824.07. 14:32
rcs6x86_​644 x 235006399224.07. 14:34
rcs7x86_​642 x 218001440024.07. 14:34
rcs7sx86_​644 x 115001198024.07. 14:35
rcs8x86_​6416 x 2370021715224.07. 14:36
rcs8sx86_​644 x 233005280024.07. 14:36
rds0x86_​644 x 218003199224.07. 14:36
rds1x86_​644 x 119101532424.07. 14:37
rds2x86_​644 x 119101532424.07. 14:37
rds3x86_​644 x 119101532424.07. 14:38
rds4x86_​644 x 119101532424.07. 14:38
rds5x86_​644 x 116001274824.07. 14:39
rds6x86_​644 x 116001274824.07. 14:39
rds7x86_​644 x 116001274824.07. 14:40
rds8x86_​644 x 116001274824.07. 14:40
res0x86_​644 x 218003199224.07. 14:40
res1x86_​644 x 222002880024.07. 14:41
res2x86_​644 x 222002880024.07. 14:41
res5x86_​642 x 222001920024.07. 14:41
res6x86_​642 x 222001920024.07. 14:42
 

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