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2024-04-16 - 15:18

Dates and Events:

OSADL Articles:

2023-11-12 12:00

Open Source License Obligations Checklists even better now

Import the checklists to other tools, create context diffs and merged lists


2023-03-01 12:00

Embedded Linux distributions

Results of the online "wish list"


2022-01-13 12:00

Phase #3 of OSADL project on OPC UA PubSub over TSN successfully completed

Another important milestone on the way to interoperable Open Source real-time Ethernet has been reached


2021-02-09 12:00

Open Source OPC UA PubSub over TSN project phase #3 launched

Letter of Intent with call for participation is now available



OSADL Projects

OSADL QA Farm on Real-time of Mainline Linux

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Number of cores/hyperthreads and bogoMIPS (x86 CPU strings, Intel names)

Box ↑ArchCoresMHzBogo​MIPSEffective
r0s0x86_​644 x 22,50040,00016.04. 13:10
r0s1x86_​644 x 22,30055,99216.04. 13:11
r0s1sx86_​644 x 23,30052,67216.04. 13:12
r0s2x86_​644 x 23,50055,86416.04. 13:13
r0s2sx86_​6410 x 13,70073,99016.04. 13:14
r0s3x86_​648 x 23,600115,20016.04. 13:15
r0s3sx86_​644 x 23,60067,20016.04. 13:18
r0s4x86_​648 x 23,600115,20016.04. 13:20
r0s4sx86_​648 x 23,600115,20016.04. 13:21
r0s5x86_​648 x 23,500115,20016.04. 13:22
r0s5sx86_​648 x 23,600115,20016.04. 13:23
r0s6x86_​648 x 23,600115,20016.04. 13:28
r0s6sx86_​6410 x 23,700147,98016.04. 01:23
r0s7x86_​648 x 23,600115,20016.04. 13:29
r0s7sx86_​642 x 23,70029,52816.04. 13:32
r0s8x86_​648 x 23,600115,20016.04. 13:33
r0s8sx86_​646 x 23,47083,38816.04. 13:35
r1s0x86_​644 x 13,10024,79616.04. 13:36
r1s1x86_​642 x 22,60021,69616.04. 13:37
r1s2x86_​644 x 12,30028,00016.04. 13:38
r1s2sx86_​644 x 12,30028,00016.04. 13:39
r1s3x86_​644 x 12,80022,42416.04. 13:40
r1s3sx86_​644 x 12,60020,88826.10. 13:42
r1s4arm​v7l2 x 11,2004816.04. 13:41
r1s4sarm​v7l2 x 14004816.04. 13:41
r1s5aarch​644 x 11,20079616.04. 13:42
r1s6x86_​642 x 22,13017,06416.04. 13:43
r1s6sx86_​642 x 21,66713,33216.04. 13:44
r1s7arm​v6l1 x 11,66753016.04. 13:45
r1s8i6861 x 21,6006,39816.04. 13:45
r1s8sx86_​644 x 11,90015,19616.04. 13:46
r2s0x86_​644 x 13,10024,80016.04. 13:46
r2s1arm​v5tejl1 x 120019916.04. 13:47
r2s2arm​v7l1 x 172049916.04. 13:48
r2s3arm​v7l0 x 1 x 162462416.04. 13:48
r2s3sarm​v7l0 x 1 x 16001,20016.04. 13:49
r2s4mips​641 x 180053124.12. 13:46
r2s5ppc1 x 13966627.03. 13:43
r2s6i6861 x 11,5002,99916.04. 13:50
r2s6saarch​644 x 11,3506416.04. 13:51
r2s7aarch​644 x 12,40043216.04. 13:52
r2s7saarch​644 x 11,50043216.04. 13:53
r2s8ppc1 x 14006616.04. 13:55
r3s0i6864 x 23,50055,99216.04. 13:56
r3s1i6864 x 12,40019,12716.04. 13:57
r3s2riscv641 x 11,00028416.04. 13:58
r3s2sriscv644 x 1028416.04. 13:59
r3s3x86_​646 x 23,33379,99216.04. 14:00
r3s4aarch​646 x 11,3009616.04. 14:01
r3s5i5861 x 113326516.04. 14:03
r3s5sppc2 x 11,20040016.04. 14:05
r3s6x86_​641 x 11,6603,33316.04. 14:06
r3s6sx86_​642 x 22,66721,33216.04. 14:07
r3s7i6861 x 15331,06616.04. 14:07
r3s8i6866 x 13,20038,52616.04. 14:08
r4s0x86_​642 x 22,30018,39616.04. 14:09
r4s1arm​v7l4 x 11,50086416.04. 14:10
r4s1sarm​v7l4 x 11,5001,00816.04. 14:12
r4s2arm​v7l1 x 180079616.04. 14:13
r4s2sarm​v7l1 x 180053016.04. 14:15
r4s3i5861 x 150099616.04. 14:17
r4s3si6861 x 11,4662,93215.04. 14:11
r4s4ppc4 x 11,20049816.04. 14:18
r4s5arm​v7l1 x 1500016.04. 14:22
r4s5saarch​644 x 11,60020027.03. 14:13
r4s6x86_​644 x 23,40054,25616.04. 14:22
r4s6sarm​v7l0 x 1 x 11,0006616.04. 14:24
r4s7i6864 x 11,83314,66416.04. 14:26
r4s7sx86_​642 x 11,8337,33216.04. 14:27
r4s8arm​v7l1 x 140039816.04. 14:28
r4s8sarm​v7l1 x 140039816.04. 14:29
r5s0x86_​642 x 22,20017,58216.04. 14:29
r5s1x86_​646 x 13,33340,09216.04. 14:30
r5s2x86_​644 x 12,70021,69916.04. 14:31
r5s2sx86_​644 x 24,00063,86312.04. 01:34
r5s3x86_​644 x 22,00031,87216.04. 14:31
r5s3sx86_​644 x 11,60012,74816.04. 14:32
r5s4x86_​642 x 22,53020,26416.04. 14:33
r5s4sx86_​642 x 22,53020,26416.04. 14:34
r5s5arm​v7l1 x 160059716.04. 14:37
r5s5sarm​v7l1 x 160060016.04. 14:38
r5s6ppc1 x 153313316.04. 14:42
r5s7arm​v7l1 x 15286416.04. 14:43
r5s7sarm​v7l1 x 15286416.04. 14:45
r6s0x86_​642 x 10 x 21,700136,18016.04. 14:47
r6s1x86_​642 x 12,0007,97816.04. 14:48
r6s2x86_​642 x 11,6679,57816.04. 14:49
r6s3x86_​644 x 22,20035,12016.04. 14:50
r6s4x86_​642 x 11,1004,37616.04. 14:51
r6s5i6861 x 11,5001,12216.04. 14:51
r6s6i6861 x 11,6003,19116.04. 14:53
r6s7i6862 x 12,3009,17611.01. 02:44
r6s8x86_​642 x 22,30018,35616.04. 14:54
r7s0x86_​642 x 22,30018,40016.04. 14:55
r7s1x86_​644 x 11,60012,84016.04. 14:56
r7s2sarm​v7l4 x 11,50072013.07. 02:16
r7s3arm​v6l1 x 1700516.04. 14:56
r7s3sarm​v7l4 x 11,40035616.04. 14:58
r7s4arm​v7l1 x 153634816.04. 15:00
r7s4sarm​v7l4 x 11,5001,08016.04. 15:01
r7s5i6861 x 11,3002,59316.04. 15:02
r7s6arm​v7l1 x 11,00039828.02. 14:10
r7s7x86_​644 x 11,60012,76716.04. 15:03
r7s7sx86_​642 x 22,30018,39616.04. 15:03
r7s8arm​v7l1 x 11,00099516.04. 15:04
r7s8sarm​v7l1 x 11,00059716.04. 15:06
r8s0x86_​642 x 22,30018,40016.04. 15:06
r8s1i5861 x 130060126.03. 02:51
r8s2x86_​642 x 22,10016,76016.04. 15:07
r8s2sx86_​642 x 22,10016,76016.04. 15:08
r8s3x86_​644 x 12,66721,28016.04. 15:10
r8s4x86_​644 x 21,60028,80016.04. 15:11
r8s4sx86_​644 x 21,60028,80016.04. 15:11
r8s5i6864 x 23,40054,40016.04. 15:12
r8s6arm​v7l1 x 150049816.04. 15:13
r8s7x86_​642 x 12,70010,77616.04. 15:14
r8s7sx86_​642 x 13,30013,19816.04. 15:15
r8s8x86_​642 x 11,3005,14416.04. 15:16
r9s0x86_​642 x 22,30018,40016.04. 15:17
r9s1x86_​642 x 12,0003,99216.04. 15:18
r9s1sarm​v7l1 x 101,25014.04. 18:03
r9s2x86_​644 x 11,60012,74816.04. 03:05
r9s2sx86_​644 x 11,60012,74830.08. 17:02
r9s3x86_​644 x 11,60012,74816.04. 03:06
r9s3sx86_​644 x 13,00024,00016.04. 03:06
r9s4i6861 x 21,0003,99016.04. 03:07
r9s4sx86_​642 x 11,3335,34716.04. 03:12
r9s5x86_​642 x 12,70010,77413.07. 03:15
r9s5sx86_​642 x 13,50013,99816.04. 03:13
r9s6x86_​642 x 23,00023,94416.04. 03:14
r9s7arm​v7l2 x 11,000016.04. 03:16
r9s8sarm​v7l1 x 180079616.04. 03:16
ras0x86_​642 x 22,30018,41616.04. 03:17
ras1i6861 x 11,4002,79916.04. 03:18
ras2x86_​642 x 11,0674,26616.04. 03:19
ras3aarch​648 x 12,0004,00016.04. 03:19
ras3sarm​v7l1 x 11,30084016.04. 03:20
ras4arm​v7l1 x 150039816.04. 03:20
ras4sarm​v7l1 x 160059707.02. 02:45
ras5arm​v7l2 x 11,0002416.04. 03:21
ras5sarm​v7l2 x 11,0002416.04. 03:21
ras6arm​v7l1 x 11,0001,98716.04. 03:22
ras6sarm​v7l1 x 11,0001,98716.04. 03:23
ras7ppc1 x 13966516.04. 03:24
ras8x86_​644 x 11,60014,40016.04. 03:24
ras8sx86_​644 x 11,60012,74816.04. 03:25
rbs0i6862 x 22,50017,60016.04. 03:26
rbs1x86_​644 x 13,10028,80016.04. 03:26
rbs2x86_​644 x 23,20051,20016.04. 03:27
rbs2sx86_​641 x 13,500007.09. 15:06
rbs3arm​v7l4 x 19962416.04. 03:28
rbs3sarm​v7l4 x 11,40035616.04. 03:29
rbs4x86_​644 x 11,2009,60016.04. 03:30
rbs4sx86_​644 x 11,60012,74816.04. 03:31
rbs5i6864 x 2049,53916.04. 03:31
rbs5saarch​644 x 11,6006416.04. 03:32
rbs6x86_​644 x 11,91515,32416.04. 03:32
rbs6sx86_​642 x 11,3335,33216.04. 03:34
rbs7arm​v7l4 x 19961216.04. 03:35
rbs7sarm​v7l4 x 19962416.04. 03:36
rbs8arm​v7l2 x 16662,65016.04. 03:37
rbs8sx86_​644 x 22,40038,70416.04. 03:38
rcs0x86_​648 x 22,40076,60016.04. 03:40
rcs1x86_​646 x 23,46783,37616.04. 03:41
rcs2x86_​642 x 12,80011,23216.04. 03:42
rcs3i6862 x 11,4005,58616.04. 03:43
rcs3sx86_​644 x 23,30052,69616.04. 03:44
rcs4x86_​642 x 11,1004,37616.04. 03:46
rcs4sx86_​644 x 11,1008,75216.04. 03:48
rcs5x86_​642 x 12,80011,19816.04. 03:50
rcs5sx86_​642 x 12,80011,19816.04. 03:52
rcs6x86_​644 x 23,50063,99216.04. 03:55
rcs7x86_​642 x 21,80014,39616.04. 03:56
rcs7sx86_​644 x 11,50011,98016.04. 03:57
rcs8x86_​6416 x 23,700217,15216.04. 04:01
rcs8sx86_​644 x 23,30052,79216.04. 04:02
rds0x86_​644 x 21,80031,99216.04. 04:03
rds1x86_​644 x 11,91015,32416.04. 04:04
rds2x86_​644 x 11,91015,32416.04. 04:05
rds3x86_​644 x 11,91015,32416.04. 04:06
rds4x86_​644 x 11,91015,32416.04. 04:06
rds5x86_​644 x 11,60012,74816.04. 04:07
rds6x86_​644 x 11,60012,74816.04. 04:08
rds7x86_​644 x 11,60012,74816.04. 04:09
rds8x86_​644 x 11,60012,74816.04. 04:09
res0x86_​644 x 21,80031,99216.04. 04:10
res1x86_​644 x 11,60014,40016.04. 04:11
res1sx86_​644 x 11,60014,40016.04. 04:12
res2x86_​644 x 11,60014,40016.04. 04:12
res3x86_​644 x 12,00015,97216.04. 04:13
res3saarch​640 x 1 x 11,0001,60016.04. 04:14
res4x86_​644 x 11,90015,05216.04. 04:15
res4sx86_​644 x 11,90015,05216.04. 04:16
res5x86_​642 x 22,20019,20016.04. 04:16
res5sx86_​642 x 22,20019,20016.04. 04:17
res6x86_​644 x 11,1008,75216.04. 04:18
res6saarch​644 x 101,60016.04. 04:19
res7arm​v7l0 x 1 x 11,0001216.04. 04:20
res7sarm​v7l0 x 1 x 11,0001212.01. 05:12
res8x86_​644 x 11,90015,05216.04. 04:21
res8sx86_​644 x 11,90015,05216.04. 04:22
rfs0x86_​6416 x 22,000128,00016.04. 04:23
rfs1aarch​644 x 11,50043216.04. 04:24
rfs2aarch​644 x 11,50043216.04. 04:24
rfs4arm​v7l1 x 180080016.04. 04:25
rfs4sarm​v7l1 x 180080016.04. 04:27
 

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