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2025-05-01 - 01:40

Dates and Events:

OSADL Articles:

2024-10-02 12:00

Linux is now an RTOS!

PREEMPT_RT is mainline - What's next?


2023-11-12 12:00

Open Source License Obligations Checklists even better now

Import the checklists to other tools, create context diffs and merged lists


2023-03-01 12:00

Embedded Linux distributions

Results of the online "wish list"


2022-01-13 12:00

Phase #3 of OSADL project on OPC UA PubSub over TSN successfully completed

Another important milestone on the way to interoperable Open Source real-time Ethernet has been reached


2021-02-09 12:00

Open Source OPC UA PubSub over TSN project phase #3 launched

Letter of Intent with call for participation is now available



OSADL Projects

OSADL QA Farm on Real-time of Mainline Linux

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Number of cores/hyperthreads and bogoMIPS (x86 CPU strings, Intel names)

Box ↑ArchCoresMHzBogo​MIPSEffective
r0s0x86_​644 x 22,50040,00001.05. 01:10
r0s0sx86_​644 x 23,40054,39201.05. 01:11
r0s1x86_​644 x 22,30056,00001.05. 01:11
r0s1sx86_​644 x 23,30052,79201.05. 01:11
r0s2x86_​644 x 23,50055,86401.05. 01:12
r0s2sx86_​6410 x 13,70073,99001.05. 01:12
r0s3x86_​648 x 23,600115,20001.05. 01:13
r0s3sx86_​644 x 23,60067,20001.05. 01:15
r0s4x86_​648 x 23,600115,20001.05. 01:16
r0s4sx86_​648 x 23,600115,20001.05. 01:16
r0s5x86_​648 x 23,500115,20001.04. 13:16
r0s5sx86_​648 x 23,600115,20001.05. 01:17
r0s6x86_​648 x 23,600115,20028.02. 13:18
r0s6sx86_​6410 x 23,700147,98001.05. 01:18
r0s7x86_​648 x 23,600115,20001.05. 01:19
r0s7sx86_​642 x 23,70029,53201.05. 01:19
r0s8x86_​648 x 23,600115,20001.05. 01:20
r0s8sx86_​646 x 23,47083,37601.05. 01:21
r1s0x86_​644 x 13,10024,80001.05. 01:22
r1s1x86_​642 x 22,60021,69601.05. 01:22
r1s2x86_​644 x 12,30028,00001.05. 01:23
r1s2sx86_​644 x 12,30028,00001.05. 01:23
r1s3x86_​644 x 12,80022,42401.05. 01:24
r1s3sx86_​644 x 12,60020,88826.10. 13:42
r1s4arm​v7l2 x 11,2004801.05. 01:25
r1s4sarm​v7l2 x 14004801.05. 01:26
r1s5aarch​644 x 11,20079601.05. 01:26
r1s6x86_​642 x 22,13017,06401.05. 01:26
r1s6sx86_​642 x 21,66713,33201.05. 01:27
r1s7arm​v6l1 x 11,66753001.05. 01:28
r1s8i6861 x 21,6006,39801.05. 01:28
r1s8sx86_​644 x 11,90015,19601.05. 01:29
r2s0x86_​644 x 13,10024,80001.05. 01:29
r2s1arm​v5tejl1 x 120019901.05. 01:30
r2s2arm​v7l1 x 172049901.05. 01:30
r2s3arm​v7l0 x 1 x 162462401.05. 01:31
r2s3sarm​v7l0 x 2 x 16001,20001.05. 01:31
r2s4mips​641 x 180053124.12. 13:46
r2s5ppc1 x 13966601.05. 01:32
r2s5sarm​v7l4 x 11,20015201.05. 01:33
r2s6i6861 x 11,5002,99901.05. 01:34
r2s6saarch​644 x 11,3506401.05. 01:34
r2s7aarch​644 x 12,40043201.05. 01:34
r2s7saarch​644 x 11,50043201.05. 01:35
r2s8ppc1 x 14006601.05. 01:36
r3s0i6864 x 23,50055,99201.05. 01:37
r3s1i6864 x 12,40019,12701.05. 01:38
r3s2riscv641 x 11,00028401.05. 01:38
r3s2sriscv644 x 1028401.05. 01:39
r3s3x86_​646 x 23,33379,99201.05. 01:40
r3s3sx86_​644 x 13,40011,98030.04. 13:41
r3s4aarch​646 x 11,3009630.04. 13:42
r3s5i5861 x 113326530.04. 13:43
r3s5sppc2 x 11,20040030.04. 13:44
r3s6x86_​641 x 21,6606,66630.04. 13:44
r3s6sx86_​642 x 22,66721,33230.04. 13:45
r3s7i6861 x 15331,06617.03. 13:50
r3s8i6864 x 13,20027,36430.04. 13:46
r4s0x86_​642 x 22,30018,40030.04. 13:46
r4s1arm​v7l4 x 11,50079230.04. 13:47
r4s1sarm​v7l4 x 11,50086430.04. 13:48
r4s2arm​v7l1 x 180079630.04. 13:49
r4s2sarm​v7l1 x 180047730.04. 13:50
r4s3i5861 x 150099630.04. 13:52
r4s3si6861 x 11,4662,93228.07. 02:17
r4s4ppc4 x 11,20049830.04. 13:53
r4s5arm​v7l1 x 1500030.04. 13:57
r4s5saarch​644 x 11,60020030.04. 13:57
r4s6x86_​644 x 23,40054,25630.04. 13:57
r4s6sarm​v7l0 x 1 x 11,0006630.04. 13:59
r4s7i6864 x 11,83314,66430.04. 14:00
r4s7sx86_​642 x 11,8337,33230.04. 14:01
r4s8arm​v7l1 x 140039830.04. 14:01
r4s8sarm​v7l1 x 140039830.04. 14:02
r5s0x86_​642 x 22,20017,58230.04. 14:02
r5s1x86_​648 x 13,33353,44830.04. 14:03
r5s2x86_​644 x 12,70021,69930.04. 14:03
r5s2sx86_​644 x 24,00063,86312.04. 01:34
r5s3x86_​644 x 22,00031,87230.04. 14:04
r5s3sx86_​644 x 11,60012,74830.04. 14:05
r5s4x86_​642 x 22,53020,26430.04. 14:06
r5s4sx86_​642 x 22,53020,26430.04. 14:06
r5s5arm​v7l1 x 160059730.04. 14:08
r5s5sarm​v7l1 x 160060030.04. 14:09
r5s6ppc1 x 153313330.04. 14:12
r5s7arm​v7l1 x 15286430.04. 14:13
r5s7sarm​v7l1 x 15284830.04. 14:14
r5s8x86_​644 x 12,00015,97230.04. 14:16
r6s0x86_​642 x 10 x 21,700136,18030.04. 14:16
r6s1x86_​642 x 12,0007,97830.04. 14:17
r6s2x86_​642 x 11,6679,57830.04. 14:17
r6s3x86_​644 x 22,20035,12030.04. 14:18
r6s4x86_​642 x 11,1004,37630.04. 14:18
r6s5i6861 x 11,5002,99230.04. 14:19
r6s6i6861 x 11,6003,19230.04. 14:20
r6s7i6862 x 12,3009,17630.04. 14:21
r6s8x86_​642 x 22,30018,35630.04. 14:21
r7s0x86_​642 x 22,30018,40030.04. 14:22
r7s1x86_​644 x 11,60012,84030.04. 14:22
r7s2aarch​642 x 11,7009630.04. 14:22
r7s2sriscv644 x 1028430.04. 14:23
r7s3arm​v6l1 x 1700530.04. 14:25
r7s3sarm​v7l4 x 11,40035630.04. 14:27
r7s4arm​v7l1 x 153635130.04. 14:28
r7s4sarm​v7l4 x 11,5001,08030.04. 14:29
r7s5i6861 x 11,3002,59330.04. 14:29
r7s6arm​v7l1 x 11,00039828.02. 14:10
r7s7x86_​644 x 11,60012,76730.04. 14:30
r7s7sx86_​642 x 22,30018,39630.04. 14:31
r7s8arm​v7l1 x 11,00099530.04. 14:31
r7s8sarm​v7l1 x 11,00099630.04. 14:32
r8s0x86_​642 x 22,30018,40030.04. 14:33
r8s1i5861 x 135070130.04. 14:34
r8s2x86_​642 x 22,10016,76030.04. 14:35
r8s2sx86_​642 x 22,10016,76030.04. 14:35
r8s3x86_​644 x 12,66721,28030.04. 14:36
r8s4x86_​644 x 21,60028,80030.04. 14:36
r8s4sx86_​644 x 21,60028,80030.04. 14:37
r8s5i6864 x 23,40054,40030.04. 14:37
r8s6arm​v7l1 x 150049830.04. 14:38
r8s6sx86_​644 x 13,30026,41630.04. 14:38
r8s7x86_​644 x 13,20025,49630.04. 14:39
r8s7sx86_​642 x 13,00011,98030.04. 14:40
r8s8x86_​642 x 11,3005,14430.04. 14:41
r9s0x86_​642 x 22,30018,39630.04. 14:41
r9s1x86_​642 x 12,0003,99230.04. 14:42
r9s1sarm​v7l1 x 101,25014.04. 18:03
r9s2x86_​644 x 11,60012,74830.04. 14:42
r9s2sx86_​644 x 11,60012,74830.08. 17:02
r9s3x86_​644 x 11,60012,74830.04. 14:43
r9s3sx86_​644 x 13,00024,00030.04. 14:44
r9s4i6861 x 21,0003,99030.04. 14:45
r9s4sx86_​642 x 11,3335,34730.04. 14:50
r9s5x86_​642 x 12,70010,77413.07. 03:15
r9s5sx86_​642 x 13,30013,19830.04. 14:50
r9s6x86_​642 x 23,00023,94430.04. 14:51
r9s7arm​v7l2 x 11,000030.04. 14:52
r9s8sarm​v7l1 x 180079630.04. 14:52
ras0x86_​642 x 22,30018,41830.04. 14:53
ras1i6861 x 11,4002,79930.04. 14:53
ras2x86_​642 x 11,0674,26630.04. 14:54
ras2sx86_​644 x 11,90015,05230.04. 14:54
ras3aarch​648 x 12,0004,00030.04. 14:55
ras3sarm​v7l1 x 11,30084030.04. 14:56
ras4arm​v7l1 x 150039830.04. 14:56
ras4sarm​v7l1 x 160059707.02. 02:45
ras5arm​v7l2 x 11,0002430.04. 14:56
ras5sarm​v7l2 x 11,0002430.04. 14:57
ras6aarch​648 x 12,0003,20030.04. 14:57
ras6sarm​v7l1 x 11,0001,98730.04. 14:58
ras7ppc1 x 13966530.04. 14:59
ras8x86_​644 x 11,60014,40030.04. 14:59
ras8sx86_​644 x 11,60012,74830.04. 15:00
rbs0i6862 x 22,50017,60030.04. 15:00
rbs1x86_​644 x 12,00015,97230.04. 15:01
rbs2x86_​644 x 12,00015,97230.04. 15:01
rbs2sx86_​641 x 13,500007.09. 15:06
rbs3arm​v7l4 x 19962430.04. 15:02
rbs3sarm​v7l4 x 11,40035630.04. 15:03
rbs4x86_​644 x 11,2009,60030.04. 15:04
rbs4sx86_​644 x 11,60012,74830.04. 15:04
rbs5i6864 x 2049,55130.04. 15:05
rbs5saarch​644 x 11,6006430.04. 15:05
rbs6x86_​644 x 11,91515,32430.04. 15:06
rbs6sx86_​642 x 11,3335,33229.08. 03:00
rbs7arm​v7l4 x 19961230.04. 03:09
rbs7sarm​v7l4 x 19962430.04. 15:07
rbs8arm​v7l2 x 16662,65030.04. 15:07
rbs8sx86_​644 x 22,40038,70430.04. 15:08
rcs0x86_​648 x 22,40076,60030.04. 15:10
rcs1x86_​646 x 23,46783,37630.04. 15:10
rcs2x86_​642 x 12,80011,23230.04. 15:11
rcs3i6862 x 11,4005,58630.04. 15:11
rcs3sx86_​644 x 13,30026,39630.04. 15:12
rcs4x86_​642 x 11,1004,37630.04. 15:13
rcs5x86_​642 x 12,80011,19830.04. 15:14
rcs5sx86_​642 x 12,80011,19830.04. 15:16
rcs6x86_​644 x 23,50063,99230.04. 15:16
rcs7x86_​642 x 21,80014,40030.04. 15:17
rcs7sx86_​644 x 11,50011,98030.04. 15:18
rcs8x86_​6416 x 23,700217,15230.04. 15:22
rcs8sx86_​644 x 23,30052,80030.04. 15:22
rds0x86_​644 x 21,80031,99230.04. 15:23
rds1x86_​644 x 11,60012,74830.04. 15:24
rds2x86_​644 x 11,60012,74830.04. 15:24
rds3x86_​644 x 11,60012,74830.04. 15:25
rds4x86_​644 x 11,60012,74830.04. 15:25
rds5x86_​644 x 11,60012,74830.04. 15:26
rds6x86_​644 x 11,60012,74830.04. 15:26
rds7x86_​644 x 11,60012,74830.04. 15:27
rds8x86_​644 x 11,60012,74830.04. 15:27
res0x86_​644 x 23,40054,39230.04. 15:28
res1x86_​644 x 11,60014,40030.04. 15:29
res1sx86_​644 x 11,60014,40030.04. 15:29
res2x86_​644 x 11,60014,40030.04. 15:30
res3x86_​644 x 12,00015,97230.04. 15:31
res3saarch​640 x 1 x 11,0001,60030.04. 15:31
res4x86_​644 x 11,90015,05230.04. 15:32
res4sx86_​644 x 11,90015,05230.04. 15:32
res5x86_​642 x 22,20019,20030.04. 15:33
res5sx86_​642 x 22,20019,20030.04. 15:33
res6x86_​644 x 11,1008,75230.04. 15:34
res6saarch​644 x 101,60030.04. 15:35
res7arm​v7l0 x 1 x 11,0001230.04. 15:36
res7sarm​v7l0 x 1 x 11,0001230.04. 15:36
res8x86_​644 x 11,90015,05230.04. 15:37
res8sx86_​644 x 11,90015,05230.04. 15:37
rfs0x86_​6416 x 22,000127,96830.04. 15:38
rfs1aarch​644 x 11,50043230.04. 15:39
rfs1saarch​644 x 11,50043230.04. 15:39
rfs2x86_​644 x 13,00023,99630.04. 15:39
rfs2sx86_​642 x 13,00011,99830.04. 15:40
rfs3x86_​644 x 11,60012,74830.04. 15:40
rfs3sx86_​644 x 11,60012,74830.04. 15:41
rfs4arm​v7l1 x 180080029.04. 03:55
rfs4sarm​v7l1 x 180080030.04. 15:42
rfs5aarch​644 x 11,2006430.04. 15:43
rfs5saarch​644 x 11,2006430.04. 15:43
rfs6arm​v7l1 x 16671,33230.04. 15:44
rfs6sarm​v7l1 x 16671,33230.04. 15:44
rfs7x86_​644 x 22,60041,60030.04. 15:45
rfs7sx86_​644 x 17006,44830.04. 15:46
rfs8arm​v7l1 x 11,00012004.03. 03:47
 

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