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2026-07-14 - 01:31

Dates and Events:

electronica 2026
10.11. - 13.11.

OSADL Articles:

2024-10-02 12:00

Linux is now an RTOS!

PREEMPT_RT is mainline - What's next?


2023-11-12 12:00

Open Source License Obligations Checklists even better now

Import the checklists to other tools, create context diffs and merged lists


2023-03-01 12:00

Embedded Linux distributions

Results of the online "wish list"


2022-01-13 12:00

Phase #3 of OSADL project on OPC UA PubSub over TSN successfully completed

Another important milestone on the way to interoperable Open Source real-time Ethernet has been reached


2021-02-09 12:00

Open Source OPC UA PubSub over TSN project phase #3 launched

Letter of Intent with call for participation is now available



OSADL Projects

OSADL QA Farm on Real-time of Mainline Linux

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Number of cores/hyperthreads and bogoMIPS (x86 CPU strings, Intel names)

Box ↑ArchCoresMHzBogo​MIPSEffective
r0s0x86_​644 x 22,50039,99214.07. 01:10
r0s0sx86_​644 x 23,40054,39214.07. 01:10
r0s1x86_​644 x 22,30056,00014.07. 01:11
r0s1sx86_​644 x 23,30052,80014.07. 01:11
r0s2x86_​644 x 23,50055,87214.07. 01:12
r0s2sx86_​6410 x 13,70073,99014.07. 01:12
r0s3x86_​648 x 23,600115,20014.07. 01:13
r0s3sx86_​644 x 23,60067,20014.07. 01:14
r0s4x86_​648 x 23,600115,20014.07. 01:15
r0s4sx86_​648 x 23,600115,20014.07. 01:16
r0s5x86_​648 x 23,500115,20014.07. 01:17
r0s5sx86_​648 x 23,600115,20014.07. 01:17
r0s6x86_​648 x 23,600115,20014.07. 01:18
r0s6sx86_​6410 x 23,700147,98014.07. 01:18
r0s7x86_​6410 x 13,70073,99014.07. 01:19
r0s7sx86_​642 x 23,70029,53223.05. 13:21
r0s8x86_​648 x 23,600115,20014.03. 13:20
r0s8sx86_​646 x 23,47083,38814.07. 01:20
r1s0x86_​644 x 13,10024,80014.07. 01:21
r1s1x86_​642 x 22,60021,69614.07. 01:22
r1s2x86_​644 x 12,30027,99614.07. 01:22
r1s2sx86_​644 x 12,30028,00014.07. 01:23
r1s3x86_​644 x 12,80022,42414.07. 01:23
r1s3saarch​646 x 12,00028814.07. 01:24
r1s4arm​v7l2 x 11,2004814.07. 01:24
r1s4sarm​v7l2 x 14004814.07. 01:25
r1s5aarch​644 x 11,20079614.07. 01:26
r1s6x86_​642 x 22,13017,06414.07. 01:26
r1s6sx86_​642 x 21,66713,33214.07. 01:27
r1s7arm​v6l1 x 11,66753014.07. 01:27
r1s8i6861 x 21,6006,40014.07. 01:28
r1s8sx86_​644 x 11,90015,19614.07. 01:28
r2s0x86_​644 x 13,60024,79614.07. 01:29
r2s1arm​v5tejl1 x 120019914.07. 01:29
r2s2arm​v7l1 x 172049913.07. 13:35
r2s3arm​v7l0 x 1 x 162462413.07. 13:36
r2s3sarm​v7l0 x 2 x 16001,20022.06. 13:31
r2s4mips​641 x 180053129.09. 13:34
r2s5ppc1 x 13966620.06. 13:32
r2s5sarm​v7l4 x 11,20015212.12. 01:35
r2s6i6861 x 11,5002,99913.07. 13:37
r2s6saarch​644 x 11,3506413.07. 13:38
r2s7aarch​644 x 12,40043213.07. 13:38
r2s7saarch​644 x 11,50043213.07. 13:39
r2s8ppc1 x 14006613.07. 13:40
r3s0i6864 x 23,50055,99213.07. 13:41
r3s1i6864 x 12,40019,12813.07. 13:42
r3s2riscv641 x 11,00028413.07. 13:42
r3s2sriscv644 x 1028413.07. 13:43
r3s3x86_​646 x 23,33379,99213.07. 13:44
r3s3sx86_​644 x 13,40011,98013.07. 13:44
r3s4aarch​646 x 11,3009613.07. 13:45
r3s5i5861 x 113326513.07. 13:47
r3s5sppc2 x 11,20040013.07. 13:50
r3s6x86_​641 x 21,6606,66613.07. 13:50
r3s6sx86_​642 x 22,66721,33213.07. 13:51
r3s7i6861 x 15331,06613.07. 13:51
r4s0x86_​642 x 22,30018,39613.07. 13:52
r4s1arm​v7l4 x 11,50079213.07. 13:53
r4s1sarm​v7l4 x 11,50086413.07. 13:54
r4s2arm​v7l1 x 180079613.07. 13:54
r4s2sarm​v7l1 x 180053013.07. 13:56
r4s3i5861 x 150099613.07. 13:57
r4s3si6861 x 11,4662,93228.07. 02:17
r4s4ppc4 x 11,20049813.07. 13:59
r4s5arm​v7l1 x 1500013.07. 14:02
r4s5saarch​644 x 11,60020013.07. 14:02
r4s6x86_​644 x 23,40054,25613.07. 14:03
r4s6sarm​v7l0 x 1 x 11,0006613.07. 14:04
r4s7i6864 x 11,83314,66413.07. 14:06
r4s7sx86_​642 x 11,8337,33213.07. 14:06
r4s8arm​v7l1 x 140039813.07. 14:07
r4s8sarm​v7l1 x 140039813.07. 14:07
r5s0x86_​642 x 22,20017,58413.07. 14:08
r5s1x86_​646 x 13,33340,08613.07. 14:08
r5s2x86_​644 x 12,70021,69913.07. 14:09
r5s2sx86_​644 x 24,00063,86312.04. 01:34
r5s3x86_​644 x 22,00031,87213.07. 14:10
r5s3sx86_​644 x 11,60012,74813.07. 14:11
r5s4x86_​642 x 22,53020,26413.07. 14:11
r5s4sx86_​644 x 11,60012,74813.07. 14:12
r5s5arm​v7l1 x 160059713.07. 02:11
r5s5sarm​v7l1 x 160060013.07. 14:14
r5s6ppc1 x 153313313.07. 14:17
r5s7arm​v7l1 x 15284813.07. 14:17
r5s7sarm​v7l1 x 15284813.07. 14:19
r5s8x86_​644 x 12,00015,97213.07. 14:21
r6s0x86_​642 x 10 x 21,700136,14013.07. 14:21
r6s1x86_​642 x 12,0007,97812.12. 02:21
r6s2x86_​642 x 11,6679,57813.07. 14:22
r6s3x86_​644 x 22,20035,12013.07. 14:22
r6s4x86_​642 x 11,1004,37613.07. 14:23
r6s5i6861 x 11,5002,99213.07. 14:24
r6s6i6861 x 11,6003,19213.07. 14:25
r6s7i6862 x 12,3009,17627.06. 14:17
r6s8x86_​642 x 22,30018,35613.07. 14:26
r7s0x86_​642 x 22,30018,40013.07. 14:27
r7s1x86_​644 x 11,60012,83913.07. 14:27
r7s2aarch​642 x 11,7009613.07. 14:28
r7s2sriscv644 x 1028413.07. 14:28
r7s3arm​v6l1 x 1700513.07. 14:30
r7s3sarm​v7l4 x 11,40035613.07. 14:32
r7s4arm​v7l1 x 153634813.07. 14:33
r7s4sarm​v7l4 x 11,5001,08013.07. 14:34
r7s5i6861 x 11,3002,59313.07. 14:34
r7s6arm​v7l1 x 11,00039802.07. 02:27
r7s7x86_​644 x 11,60012,76713.07. 14:35
r7s7sx86_​642 x 22,30018,39613.07. 14:36
r7s8arm​v7l1 x 11,00099513.07. 14:36
r7s8sarm​v7l1 x 11,00079613.07. 14:37
r8s0x86_​642 x 22,30018,40013.07. 14:38
r8s1i5861 x 135070113.07. 14:39
r8s2aarch​644 x 11,4001,60013.07. 14:40
r8s2saarch​644 x 11,4001,60013.07. 14:41
r8s3x86_​644 x 12,66721,28013.07. 14:41
r8s4x86_​644 x 21,60028,80013.07. 14:42
r8s4sx86_​644 x 21,60028,80013.07. 14:42
r8s5i6864 x 23,40054,40013.07. 14:43
r8s6arm​v7l1 x 150049813.07. 14:43
r8s6sx86_​644 x 13,30026,41613.07. 14:43
r8s7x86_​644 x 13,20025,49613.07. 14:44
r8s7sx86_​642 x 13,00011,98013.07. 14:45
r8s8x86_​642 x 11,3005,14413.07. 14:45
r9s0x86_​644 x 23,60057,60013.07. 14:46
r9s1x86_​642 x 12,0007,98412.02. 14:30
r9s1sarm​v7l1 x 101,25014.04. 18:03
r9s2arm​v7l0 x 1 x 155040013.07. 14:47
r9s2sarm​v7l0 x 1 x 155040013.07. 14:48
r9s3x86_​644 x 11,60012,74813.07. 14:48
r9s3sx86_​644 x 13,00024,00013.07. 14:49
r9s4i6861 x 21,0003,99013.07. 14:49
r9s4sx86_​642 x 11,3335,34713.07. 14:50
r9s5x86_​644 x 21,90028,80013.07. 14:51
r9s5sx86_​642 x 13,30013,19813.07. 14:51
r9s6x86_​642 x 23,00023,94409.06. 14:37
r9s7arm​v7l2 x 11,000013.07. 14:52
r9s8aarch​644 x 1043213.07. 14:52
r9s8sriscv644 x 1028413.07. 14:53
ras0x86_​642 x 22,30018,41813.07. 14:53
ras1i6861 x 11,4002,79913.07. 14:54
ras2x86_​642 x 11,0674,26613.07. 14:54
ras2sx86_​644 x 11,90015,05213.07. 14:55
ras3aarch​648 x 12,0004,00006.05. 03:01
ras3sarm​v7l1 x 11,30084013.07. 14:55
ras4aarch​648 x 12,40038413.07. 14:56
ras4saarch​648 x 12,40038429.09. 03:02
ras5arm​v7l2 x 11,0002413.07. 14:57
ras5sarm​v7l2 x 11,0002413.07. 14:57
ras6aarch​648 x 12,0003,20022.06. 02:51
ras6sarm​v7l1 x 11,0001,98713.07. 14:57
ras7ppc1 x 13966513.07. 14:58
ras8x86_​644 x 11,60014,40013.07. 14:58
ras8sx86_​644 x 11,60012,74813.07. 14:59
rbs0i6862 x 22,50017,60013.07. 14:59
rbs3arm​v7l4 x 19962413.07. 15:00
rbs3sarm​v7l4 x 11,40035613.07. 15:01
rbs4x86_​644 x 11,2009,60013.07. 15:02
rbs4sx86_​644 x 11,60012,74813.07. 15:02
rbs5i6864 x 2052,36513.07. 15:03
rbs5saarch​644 x 11,6006413.07. 15:03
rbs6x86_​644 x 11,91515,32413.07. 15:04
rbs6sx86_​642 x 11,3335,33229.08. 03:00
rbs7arm​v7l4 x 19961213.07. 15:05
rbs7sarm​v7l4 x 19962413.07. 15:07
rbs8arm​v7l2 x 16662,65013.07. 15:07
rbs8sx86_​644 x 22,40038,70413.07. 15:08
rcs0x86_​648 x 22,40076,59213.07. 15:09
rcs1x86_​646 x 23,46783,37713.07. 15:10
rcs2x86_​642 x 12,80011,23213.07. 15:11
rcs3i6862 x 11,4005,58613.07. 15:12
rcs3sx86_​644 x 13,30026,39613.07. 15:13
rcs4x86_​642 x 11,1004,37613.07. 15:13
rcs5x86_​642 x 12,80011,19813.07. 15:14
rcs5sx86_​642 x 12,80011,19813.07. 15:16
rcs6x86_​644 x 23,50063,99213.07. 15:17
rcs7x86_​642 x 21,80014,40013.07. 15:17
rcs7sx86_​644 x 11,50011,98013.07. 15:18
rcs8x86_​6416 x 23,700217,18413.07. 15:22
rcs8sx86_​644 x 23,30052,80013.07. 15:23
rds0x86_​644 x 21,80031,99213.07. 15:23
rds1x86_​644 x 11,60012,74813.07. 15:24
rds2x86_​644 x 11,60012,74813.07. 15:25
rds3x86_​644 x 11,60012,74813.07. 15:25
rds4x86_​644 x 11,60012,74813.07. 15:26
rds5x86_​644 x 11,60012,74813.07. 15:27
rds6x86_​644 x 11,60012,74813.07. 15:27
rds7x86_​644 x 11,60012,74813.07. 15:28
rds8x86_​644 x 11,60012,74813.07. 15:28
res0x86_​644 x 23,40054,39213.07. 15:28
res1x86_​644 x 11,60014,40013.07. 15:29
res1sx86_​644 x 11,60014,40013.07. 15:30
res2x86_​644 x 11,60014,40013.07. 15:30
res3x86_​644 x 12,00015,97213.07. 15:31
res3saarch​640 x 1 x 11,0001,60013.07. 15:32
res4x86_​644 x 11,90015,05213.07. 03:35
res4sx86_​644 x 11,90015,05213.07. 15:32
res5x86_​642 x 22,20019,20013.07. 15:33
res5sx86_​642 x 22,20019,20013.07. 15:33
res6x86_​644 x 11,1008,75213.07. 15:34
res6saarch​644 x 101,60013.07. 15:35
res7arm​v7l0 x 1 x 11,0001213.07. 15:36
res7sarm​v7l0 x 1 x 11,0001213.07. 15:36
res8x86_​644 x 11,90015,05213.07. 15:37
res8sx86_​644 x 11,90015,05213.07. 15:37
rfs0x86_​6416 x 22,000128,00013.07. 15:38
rfs1aarch​644 x 11,50043213.07. 15:38
rfs1saarch​644 x 11,50043213.07. 15:39
rfs2x86_​644 x 13,00024,00013.07. 15:39
rfs2sx86_​642 x 13,00011,99813.07. 15:39
rfs3x86_​644 x 11,60012,74813.07. 15:40
rfs3sx86_​644 x 11,60012,74813.07. 15:40
rfs4aarch​641 x 11,4001,60013.07. 15:41
rfs4sarm​v7l1 x 180080013.07. 15:42
rfs5aarch​644 x 11,2006413.07. 15:43
rfs5saarch​644 x 11,2006413.07. 15:44
rfs6arm​v7l1 x 16671,33213.07. 15:44
rfs6sarm​v7l1 x 16671,33213.07. 15:45
rfs7x86_​644 x 22,60041,60013.07. 15:46
rfs7sx86_​644 x 17006,44813.07. 15:47
rfs8arm​v7l1 x 11,00012013.07. 15:47
 

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