You are here: Home / Projects / OSADL QA Farm Real-time / 
2023-02-01 - 16:16
OSADL Projects

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Number of cores/hyperthreads and bogoMIPS (x86 CPU strings, Intel names)

Box ↑ArchCoresMHzBogo​MIPSEffective
r0s0x86_​644 x 22,50040,00001.02. 13:10
r0s1x86_​644 x 22,30055,99201.02. 13:10
r0s1sx86_​644 x 23,30052,80001.02. 13:10
r0s2x86_​644 x 23,50055,86401.02. 13:11
r0s2sx86_​6410 x 13,70073,99001.02. 13:13
r0s3x86_​648 x 23,600115,20001.02. 13:13
r0s3sx86_​644 x 23,60067,20001.02. 13:15
r0s4x86_​648 x 23,600115,20001.02. 13:17
r0s4sx86_​648 x 23,600115,20001.02. 13:19
r0s5x86_​648 x 23,500115,20001.02. 13:20
r0s5sx86_​648 x 23,600115,20001.02. 13:22
r0s6x86_​648 x 23,600115,20001.02. 13:23
r0s6sx86_​6410 x 23,700147,98001.02. 13:25
r0s7x86_​648 x 23,600115,20001.02. 13:26
r0s7sx86_​642 x 23,70029,53201.02. 13:28
r0s8x86_​648 x 23,600115,20001.02. 13:30
r0s8sx86_​646 x 23,47083,38801.02. 13:32
r1s0x86_​644 x 13,10024,79601.02. 13:33
r1s1x86_​642 x 22,60021,69601.02. 13:33
r1s2x86_​644 x 12,30028,00001.02. 13:34
r1s2sx86_​644 x 12,30028,00001.02. 13:34
r1s3x86_​644 x 23,50056,00026.05. 01:16
r1s3sx86_​644 x 23,50056,00026.05. 01:16
r1s4arm​v7l2 x 11,2004801.02. 13:35
r1s4sarm​v7l2 x 14004801.02. 13:35
r1s5aarch​644 x 11,20079601.02. 13:36
r1s6x86_​642 x 22,13017,06401.02. 13:36
r1s6sx86_​642 x 21,66713,33201.02. 13:36
r1s7arm​v6l1 x 11,66753001.02. 13:37
r1s8i6861 x 21,6006,40001.02. 13:37
r1s8sx86_​644 x 11,90015,19601.02. 13:38
r2s0x86_​644 x 13,10024,80001.02. 13:39
r2s1arm​v5tejl1 x 120019928.06. 13:37
r2s2arm​v7l1 x 172049901.02. 13:39
r2s4mips​641 x 180053110.01. 01:23
r2s5ppc1 x 13966621.01. 13:37
r2s6i6861 x 11,5002,99901.02. 13:40
r2s6sx86_​644 x 11,99015,99209.02. 01:27
r2s7x86_​644 x 13,70029,60010.03. 13:24
r2s8ppc1 x 14006601.02. 13:41
r3s0i6864 x 23,50056,00001.02. 13:42
r3s1i6864 x 12,40019,12701.02. 13:42
r3s2riscv641 x 11,00028401.02. 13:42
r3s3x86_​646 x 23,33379,99201.02. 13:43
r3s4x86_​641 x 21,4005,60010.01. 01:28
r3s5i5861 x 113326501.02. 13:44
r3s5sppc2 x 11,20040001.02. 13:46
r3s6x86_​641 x 21,6606,66601.02. 13:47
r3s6sx86_​642 x 22,66721,33201.02. 14:04
r3s7i6861 x 15331,06601.02. 14:04
r3s8i6866 x 13,20038,52001.02. 14:06
r4s0x86_​642 x 22,30018,39601.02. 14:06
r4s1arm​v7l4 x 11,50079201.02. 14:07
r4s1sarm​v7l4 x 11,50079201.02. 14:07
r4s2arm​v7l1 x 180079601.02. 14:08
r4s2sarm​v7l1 x 180047701.02. 14:09
r4s3i5861 x 150099601.02. 14:12
r4s3si6861 x 11,4662,93201.02. 14:13
r4s4ppc4 x 11,20049801.02. 14:13
r4s5arm​v7l1 x 1500001.02. 14:16
r4s5saarch​644 x 11,60020001.02. 14:16
r4s6x86_​644 x 23,40054,25601.02. 14:17
r4s6sarm​v7l0 x 1 x 11,0006601.02. 14:17
r4s7i6864 x 11,83314,66401.02. 14:18
r4s7sx86_​642 x 11,8337,33201.02. 14:18
r4s8arm​v7l1 x 140039801.02. 14:18
r4s8sarm​v7l1 x 140039801.02. 14:19
r5s0x86_​642 x 22,20017,58201.02. 14:19
r5s1x86_​646 x 13,33340,09201.02. 14:19
r5s2x86_​644 x 12,70021,69901.02. 14:20
r5s2sx86_​644 x 24,00063,86312.04. 01:34
r5s3x86_​644 x 22,00031,87201.02. 14:20
r5s3sx86_​644 x 11,60012,74801.02. 14:21
r5s4x86_​642 x 22,53020,26401.02. 14:21
r5s4sx86_​642 x 22,53020,26401.02. 14:22
r5s5arm​v7l1 x 160059701.02. 14:23
r5s5sarm​v7l1 x 160060001.02. 02:25
r5s6ppc1 x 153313301.02. 14:24
r5s7arm​v7l1 x 15286401.02. 14:25
r5s7sarm​v7l1 x 15284801.02. 14:26
r6s0x86_​642 x 10 x 21,700136,14001.02. 14:28
r6s1x86_​642 x 12,0007,97801.02. 14:28
r6s2x86_​642 x 11,6679,57601.02. 14:28
r6s3x86_​644 x 22,20035,12001.02. 14:29
r6s4x86_​642 x 11,1004,37601.02. 14:29
r6s5i6861 x 11,5002,99201.02. 14:30
r6s6i6861 x 11,6003,19101.02. 14:31
r6s7i6862 x 12,3009,17601.02. 14:31
r6s8x86_​642 x 22,30018,35601.02. 14:31
r7s0x86_​642 x 22,30018,40001.02. 14:32
r7s1x86_​644 x 11,60012,84001.02. 14:32
r7s2sarm​v7l4 x 11,50072013.07. 02:16
r7s3arm​v6l1 x 1700501.02. 14:33
r7s3sarm​v7l4 x 11,40035601.02. 14:34
r7s4arm​v7l1 x 153634801.02. 14:35
r7s4sarm​v7l4 x 11,5001,00801.02. 14:36
r7s5i6861 x 11,3002,59301.02. 14:36
r7s6arm​v7l1 x 11,00039828.02. 14:10
r7s7x86_​644 x 11,60012,76701.02. 14:37
r7s7sx86_​642 x 22,30018,39601.02. 14:37
r7s8arm​v7l1 x 11,00099501.02. 14:38
r7s8sarm​v7l1 x 11,00079601.02. 14:38
r8s0x86_​642 x 22,30018,40001.02. 14:38
r8s1i5861 x 130060101.02. 14:39
r8s2x86_​642 x 22,10016,76001.02. 14:40
r8s2sx86_​642 x 22,10016,76001.02. 14:41
r8s3x86_​644 x 12,66721,27601.02. 14:41
r8s4x86_​644 x 21,60028,80001.02. 14:42
r8s4sx86_​644 x 21,60028,80001.02. 14:42
r8s5i6864 x 23,40054,40001.02. 14:43
r8s6arm​v7l1 x 150049801.02. 14:44
r8s7x86_​642 x 12,70010,77601.02. 14:44
r8s7sx86_​642 x 13,30013,24801.02. 14:44
r8s8x86_​642 x 11,3005,14401.02. 14:45
r9s0x86_​642 x 22,30018,40001.02. 14:45
r9s1x86_​642 x 12,0003,99201.02. 14:46
r9s1sarm​v7l1 x 101,25022.07. 09:38
r9s2x86_​644 x 11,60012,74801.02. 14:46
r9s2sx86_​644 x 11,60012,74830.08. 17:02
r9s3x86_​644 x 11,60012,74801.02. 14:47
r9s3sx86_​644 x 13,00024,00001.02. 14:47
r9s4i6861 x 21,0003,98801.02. 14:48
r9s4sx86_​642 x 11,3335,34701.02. 14:48
r9s5x86_​642 x 12,70010,77601.02. 14:49
r9s5sx86_​642 x 13,50013,99801.02. 14:49
r9s6x86_​642 x 23,00023,94401.02. 14:49
r9s7arm​v7l2 x 11,000001.02. 14:50
r9s8sarm​v7l1 x 180079606.01. 14:53
ras0x86_​642 x 22,30018,41801.02. 14:50
ras1i6861 x 11,4002,79901.02. 14:51
ras2x86_​642 x 11,0674,26601.02. 14:51
ras3sarm​v7l8 x 11,30084025.11. 02:17
ras4arm​v7l1 x 150039801.02. 14:52
ras4sarm​v7l1 x 160059707.02. 02:45
ras5arm​v7l2 x 11,0002401.02. 14:52
ras5sarm​v7l2 x 11,0002401.02. 14:52
ras6arm​v7l1 x 11,0001,98701.02. 14:53
ras6sarm​v7l1 x 11,0001,98701.02. 14:53
ras7ppc1 x 13966501.02. 14:53
ras8x86_​644 x 11,60014,40001.02. 14:54
ras8sx86_​644 x 11,60012,74801.02. 14:54
rbs0i6862 x 22,50017,60001.02. 14:55
rbs1x86_​644 x 13,10024,79601.02. 14:55
rbs2x86_​644 x 23,20051,20001.02. 14:56
rbs2sx86_​644 x 23,50055,86401.02. 14:56
rbs3arm​v7l4 x 19962401.02. 14:58
rbs3sarm​v7l4 x 11,40035601.02. 14:58
rbs4x86_​644 x 11,2009,60001.02. 14:59
rbs4sx86_​644 x 11,60012,74801.02. 14:59
rbs5i6864 x 2049,16901.02. 15:00
rbs5saarch​644 x 11,6006401.02. 15:00
rbs6x86_​644 x 11,91515,32401.02. 15:00
rbs6sx86_​642 x 11,3335,33201.02. 15:01
rbs7arm​v7l4 x 19961201.02. 15:02
rbs7sarm​v7l4 x 19962401.02. 15:02
rbs8arm​v7l2 x 16662,65001.02. 15:03
rbs8sx86_​644 x 22,40038,70401.02. 15:04
rcs0x86_​648 x 22,40077,36801.02. 15:06
rcs1x86_​646 x 23,46783,37601.02. 15:06
rcs2x86_​642 x 12,80011,23201.02. 15:07
rcs3i6862 x 11,4005,58601.02. 15:07
rcs3sx86_​644 x 23,30052,69601.02. 15:08
rcs4x86_​642 x 11,1004,37601.02. 15:08
rcs4sx86_​644 x 11,1008,75201.02. 15:09
rcs5x86_​642 x 12,80011,19801.02. 15:10
rcs5sx86_​642 x 12,80011,19801.02. 15:12
rcs6x86_​644 x 23,50063,99201.02. 15:14
rcs7x86_​642 x 21,80014,40001.02. 15:14
rcs7sx86_​644 x 11,50011,98001.02. 15:15
rcs8x86_​6416 x 23,700217,15201.02. 15:18
rcs8sx86_​644 x 23,30052,79201.02. 15:19
rds0x86_​644 x 21,80031,99201.02. 15:19
rds1x86_​644 x 11,91015,32401.02. 15:20
rds2x86_​644 x 11,91015,32401.02. 15:20
rds3x86_​644 x 11,91015,32401.02. 15:21
rds4x86_​644 x 11,91015,32401.02. 15:21
rds5x86_​644 x 11,60012,74801.02. 15:22
rds6x86_​644 x 11,60012,74801.02. 15:22
rds7x86_​644 x 11,60012,74801.02. 15:23
rds8x86_​644 x 11,60012,74801.02. 15:23
res0x86_​644 x 21,80031,99201.02. 15:23
res1x86_​644 x 11,60014,40001.02. 15:24
res1sx86_​644 x 11,60014,40001.02. 15:25
res2x86_​644 x 11,60014,40001.02. 15:26
res3x86_​644 x 12,00015,97201.02. 15:27
res4x86_​644 x 11,90015,05225.10. 03:17
res5x86_​642 x 22,20019,20001.02. 15:27
res5sx86_​642 x 22,20019,20001.02. 15:28
res6x86_​642 x 22,20019,20019.01. 14:55
res7x86_​644 x 11,90015,05201.02. 15:28
res8x86_​644 x 11,90015,05201.02. 15:29
 

Valid XHTML 1.0 Transitional