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2024-04-27 - 02:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Fri Apr 26, 2024 12:46:08)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1835499372360,12cyclictest21633-21kworker/2:111:45:012
1835499368365,2cyclictest20418-21gsd-color10:14:032
1835499350347,1cyclictest0-21swapper/207:29:022
1835499350347,1cyclictest0-21swapper/207:29:022
1835499346345,1cyclictest13623-21kworker/2:011:18:032
1835499344334,10cyclictest13623-21kworker/2:010:01:022
1835499342340,2cyclictest0-21swapper/211:59:022
1835499341340,0cyclictest0-21swapper/210:47:032
1835499341340,0cyclictest0-21swapper/210:47:032
1835499341339,0cyclictest0-21swapper/207:43:022
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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