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2023-03-27 - 12:48

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #5

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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x86 Intel Core i9-9900K @3600 MHz, Linux 5.10.162-rt78 (Profile)

Latency plot of shadow in rack #0, slot #5
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot5s.osadl.org (updated Tue Feb 21, 2023 00:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
24514599442441,1cyclictest309490-21kworker/u32:300:39:002
24514599441440,1cyclictest309490-21kworker/u32:300:29:002
24514599440439,1cyclictest305275-21kworker/u32:000:03:002
24514599440439,1cyclictest283005-21kworker/u32:222:32:592
24514599440439,1cyclictest253918-21kworker/u32:220:31:002
24514599440439,1cyclictest253918-21kworker/u32:220:31:002
245145994400,3cyclictest0-21swapper/1020:53:002
245139994260,0cyclictest0-21swapper/400:14:5710
245154994250,425cyclictest0-21swapper/1520:05:007
24514999425424,1cyclictest264421-21turbostat20:44:576
24514799425424,1cyclictest293238-21turbostat23:04:554
24514699424423,1cyclictest299475-21kworker/u32:123:31:003
245154994230,423cyclictest0-21swapper/1519:19:567
24513699423418,2cyclictest308719-21turbostat00:19:571
24513799422422,0cyclictest274716-21turbostat21:34:568
24514599421421,0cyclictest0-21swapper/1021:15:002
24514299420420,0cyclictest295311-21turbostat23:10:0113
24515499418416,2cyclictest0-21swapper/1521:00:027
24514599418418,0cyclictest306655-21turbostat00:09:572
24514499417417,0cyclictest0-21swapper/919:14:5615
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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