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2026-02-24 - 07:46
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #4, slot #1

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot1s.osadl.org (updated Tue Feb 24, 2026 00:44:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
326352900,3sleep032638-21unixbench_multi22:06:330
60662850,1sleep0201rcuc/023:51:220
46442820,3sleep20-21swapper/219:26:282
46442820,3sleep20-21swapper/219:26:282
30900996861,5cyclictest10878-21grep00:01:331
30900996861,5cyclictest10878-21grep00:01:331
240912660,2chrt24090-21sshd20:18:360
240912660,2chrt24090-21sshd20:18:360
290012640,3sleep30-21swapper/320:31:293
290012640,3sleep30-21swapper/320:31:293
139272620,3sleep20-21swapper/200:11:262
139272620,3sleep20-21swapper/200:11:262
30895995951,4cyclictest0-21swapper/000:01:180
30895995951,4cyclictest0-21swapper/000:01:180
30895995951,4cyclictest0-21swapper/000:01:180
226212560,2sleep30-21swapper/320:16:183
237852550,3sleep30-21swapper/320:16:343
237852550,3sleep30-21swapper/320:16:343
229972540,3sleep20-21swapper/220:16:252
229972540,3sleep20-21swapper/220:16:252
145172540,2sleep30-21swapper/319:51:333
145172540,2sleep30-21swapper/319:51:333
147002520,2chrt0-21swapper/022:46:290
147002520,2chrt0-21swapper/022:46:290
147002520,2chrt0-21swapper/022:46:290
245232500,3sleep30-21swapper/323:11:333
245232500,3sleep30-21swapper/323:11:333
262562490,3sleep20-21swapper/221:51:242
262562490,3sleep20-21swapper/221:51:242
4802450,3sleep30-21swapper/323:36:213
4802450,3sleep30-21swapper/323:36:213
4802450,3sleep30-21swapper/323:36:213
25112450,3chrt0-21swapper/223:41:232
104432450,3sleep20-21swapper/200:01:302
104432450,3sleep20-21swapper/200:01:302
152932420,2sleep015399-21df00:16:230
152932420,2sleep015399-21df00:16:230
152932420,2sleep015399-21df00:16:230
11232400,3sleep20-21swapper/220:44:102
3089599389,5cyclictest201rcuc/000:03:470
3089599389,5cyclictest201rcuc/000:03:470
30900993733,3cyclictest1881-21cat19:21:101
3089599379,5cyclictest171ktimers/000:29:140
3089599379,5cyclictest171ktimers/000:29:140
169402370,2sleep017021-21cat21:26:270
30895993630,4cyclictest2608-21idleruntime23:41:230
30895993626,3cyclictest181rcu_preempt19:37:100
30895993626,3cyclictest181rcu_preempt19:37:100
30895993621,9cyclictest90-1pr/ttyS022:03:180
30895993621,9cyclictest90-1pr/ttyS022:03:180
30895993614,4cyclictest201rcuc/023:08:010
30895993614,4cyclictest201rcuc/023:08:010
3090699351,23cyclictest9600-21chrt00:01:172
3090699351,23cyclictest9600-21chrt00:01:172
3090699351,23cyclictest9600-21chrt00:01:172
30895993528,5cyclictest12581-21latency_hist21:16:120
30895993528,5cyclictest12581-21latency_hist21:16:120
30895993514,5cyclictest201rcuc/021:56:360
30895993514,5cyclictest201rcuc/021:56:360
30895993514,5cyclictest201rcuc/021:56:360
30895993513,6cyclictest201rcuc/019:55:090
30895993513,6cyclictest201rcuc/019:55:090
289812350,2sleep029009-21cpu23:26:220
289812350,2sleep029009-21cpu23:26:220
30900993426,6cyclictest14376-21gltestperf22:46:251
30900993426,6cyclictest14376-21gltestperf22:46:251
30900993426,6cyclictest14376-21gltestperf22:46:251
3091399331,23cyclictest9615-21chrt00:01:183
3091399331,23cyclictest9615-21chrt00:01:183
3091399331,23cyclictest9615-21chrt00:01:183
30900993327,4cyclictest6070-21fschecks_time19:31:221
30900993327,4cyclictest6070-21fschecks_time19:31:221
30900993224,6cyclictest13599-21fschecks_count00:11:231
30900993224,6cyclictest13599-21fschecks_count00:11:231
3089599326,4cyclictest201rcuc/022:19:270
3089599326,4cyclictest201rcuc/022:19:270
30895993227,4cyclictest729-21dbus-daemon22:41:100
30895993227,4cyclictest729-21dbus-daemon22:41:100
211492320,4chrt0-21swapper/200:31:242
211492320,4chrt0-21swapper/200:31:242
30900993126,3cyclictest22746-21head23:06:331
30900993126,3cyclictest22746-21head23:06:331
30900993122,7cyclictest7057-21kernelversion22:26:251
30900993122,7cyclictest7057-21kernelversion22:26:251
30900993122,7cyclictest17857-21needreboot00:21:281
30900993122,7cyclictest17857-21needreboot00:21:281
30900993120,9cyclictest27894-21fschecks_time21:56:221
30900993120,9cyclictest27894-21fschecks_time21:56:221
30900993120,9cyclictest27894-21fschecks_time21:56:221
3089599319,4cyclictest171ktimers/020:06:240
3089599319,4cyclictest171ktimers/020:06:240
3089599316,8cyclictest16-21ksoftirqd/023:40:450
3089599316,8cyclictest16-21ksoftirqd/023:40:450
3089599316,8cyclictest16-21ksoftirqd/023:40:450
3089599314,6cyclictest171ktimers/023:19:450
3089599314,6cyclictest171ktimers/023:19:450
3089599314,6cyclictest171ktimers/023:19:450
30895993126,3cyclictest5733-21kernelversion20:56:240
30895993126,3cyclictest5733-21kernelversion20:56:240
30895993123,6cyclictest5072-21latency_hist20:56:130
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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