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2026-02-03 - 18:44
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #4, slot #1

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot1s.osadl.org (updated Tue Feb 03, 2026 12:44:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1976921270,3sleep20-21swapper/209:26:052
1976921270,3sleep20-21swapper/209:26:052
3169621210,3sleep20-21swapper/208:31:062
3169621210,3sleep20-21swapper/208:31:062
244342980,3sleep024436-21fschecks_count11:06:020
244342980,3sleep024436-21fschecks_count11:06:020
146892940,2sleep014688-21tail12:06:040
209732870,2chrt0-21swapper/108:00:581
209732870,2chrt0-21swapper/108:00:581
209732870,2chrt0-21swapper/108:00:581
85062790,3sleep10-21swapper/108:56:051
85062790,3sleep10-21swapper/108:56:051
23412750,2sleep00-21swapper/008:40:570
23412750,2sleep00-21swapper/008:40:570
240872730,2sleep024086-21if_err_eth012:31:040
240872730,2sleep024086-21if_err_eth012:31:040
6512660,2sleep00-21swapper/010:01:090
6512660,2sleep00-21swapper/010:01:090
258222640,3sleep00-21swapper/008:16:000
41442580,3sleep20-21swapper/208:45:532
133782560,3sleep00-21swapper/007:40:510
133782560,3sleep00-21swapper/007:40:510
36312530,4sleep20-21swapper/211:36:072
36312530,4sleep20-21swapper/211:36:072
36312530,4sleep20-21swapper/211:36:072
253882520,2chrt0-21swapper/312:35:543
253882520,2chrt0-21swapper/312:35:543
260872460,2chrt0-21swapper/008:16:040
260872460,2chrt0-21swapper/008:16:040
18622450,2sleep00-21swapper/010:06:050
16102450,3sleep20-21swapper/208:36:132
16102450,3sleep20-21swapper/208:36:132
165372440,3sleep20-21swapper/212:11:042
165372440,3sleep20-21swapper/212:11:042
259952420,2sleep20-21swapper/212:36:062
259952420,2sleep20-21swapper/212:36:062
295732400,2sleep129661-21irqstats08:26:031
295732400,2sleep129661-21irqstats08:26:031
289502400,2sleep128948-21gltestperf09:51:051
289502400,2sleep128948-21gltestperf09:51:051
289502400,2sleep128948-21gltestperf09:51:051
12732400,2sleep30-21swapper/308:36:113
12732400,2sleep30-21swapper/308:36:113
198652390,3sleep20-21swapper/212:20:572
198652390,3sleep20-21swapper/212:20:572
185702370,3sleep02484-21cyclictest12:16:050
185702370,3sleep02484-21cyclictest12:16:050
315662360,3sleep30-21swapper/311:25:503
315662360,3sleep30-21swapper/311:25:503
130342360,2sleep113141-21bingrep12:01:071
130342360,2sleep113141-21bingrep12:01:071
110632360,1sleep20-21swapper/209:01:132
110632360,1sleep20-21swapper/209:01:132
2500993429,3cyclictest11533-21cron09:05:500
2500993429,3cyclictest11533-21cron09:05:500
2500993427,5cyclictest1035-21latency_hist11:30:510
2500993427,5cyclictest1035-21latency_hist11:30:510
2500993423,7cyclictest4216-21latency_hist08:45:560
2507993325,6cyclictest29664-21sendmail11:20:511
2507993325,6cyclictest29664-21sendmail11:20:511
2500993325,3cyclictest181rcu_preempt10:38:150
2500993325,3cyclictest181rcu_preempt10:38:150
2500993324,7cyclictest26277-21fschecks_count11:11:030
2500993324,7cyclictest26277-21fschecks_count11:11:030
2500993323,7cyclictest17011-21cut10:46:030
80672320,2sleep20-21swapper/207:26:012
80672320,2sleep20-21swapper/207:26:012
80672320,2sleep20-21swapper/207:26:012
2500993225,5cyclictest21644-21timerwakeupswit10:56:150
2500993225,5cyclictest21644-21timerwakeupswit10:56:150
2500993225,5cyclictest21644-21timerwakeupswit10:56:150
2500993224,6cyclictest15419-21latency_hist07:45:590
2500993219,4cyclictest181rcu_preempt09:31:100
2500993219,4cyclictest181rcu_preempt09:31:100
2507993125,4cyclictest21227-21fschecks_count08:01:021
2507993125,4cyclictest21227-21fschecks_count08:01:021
2507993121,8cyclictest3611-21unixbench_multi08:41:131
2500993126,3cyclictest90-1pr/ttyS010:22:440
2500993126,3cyclictest90-1pr/ttyS010:22:440
2500993126,3cyclictest2484-21cyclictest12:21:140
2500993126,3cyclictest2484-21cyclictest12:21:140
2500993123,6cyclictest2484-21cyclictest10:14:170
2500993123,6cyclictest2484-21cyclictest10:14:170
2500993123,6cyclictest16408-21mailstats09:16:140
2500993123,6cyclictest16408-21mailstats09:16:140
2500993123,6cyclictest16408-21mailstats09:16:140
2500993121,8cyclictest4493-21fschecks_time08:46:030
2507993021,7cyclictest25941-21latency_hist11:10:511
2507993021,7cyclictest25941-21latency_hist11:10:511
2507993020,7cyclictest15200-21fschecks_time10:41:041
2507993020,7cyclictest15200-21fschecks_time10:41:041
2500993024,3cyclictest0-21swapper/008:25:510
2500993024,3cyclictest0-21swapper/008:25:510
2500993023,5cyclictest23398-21kernelversion08:06:040
2500993023,5cyclictest23398-21kernelversion08:06:040
2500993021,7cyclictest0-21swapper/011:05:510
2500993021,7cyclictest0-21swapper/011:05:510
2500993020,7cyclictest7357-21latency_hist10:20:560
2500993020,7cyclictest7357-21latency_hist10:20:560
2500993020,7cyclictest7357-21latency_hist10:20:560
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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