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2026-01-27 - 14:03
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #4, slot #1

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack4slot1s.osadl.org (updated Tue Jan 27, 2026 12:44:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2381521520,2sleep023817-21strings11:01:000
2476221330,2sleep30-21swapper/308:10:583
2476221330,2sleep30-21swapper/308:10:583
1243221040,3sleep30-21swapper/311:56:073
1243221040,3sleep30-21swapper/311:56:073
2348321000,2sleep123486-21gltestperf11:00:571
140002980,3sleep20-21swapper/210:35:582
140002980,3sleep20-21swapper/210:35:582
147532820,2sleep3431rcuc/310:36:073
147532820,2sleep3431rcuc/310:36:073
70442760,3sleep30-21swapper/308:50:553
70442760,3sleep30-21swapper/308:50:553
323872690,2chrt29-21ksoftirqd/111:25:501
323872690,2chrt29-21ksoftirqd/111:25:501
275952690,2sleep10-21swapper/109:45:571
275952690,2sleep10-21swapper/109:45:571
161692690,1chrt0-21swapper/110:40:591
161692690,1chrt0-21swapper/110:40:591
82432680,2sleep20-21swapper/208:52:062
82432680,2sleep20-21swapper/208:52:062
13852650,3sleep2351rcuc/210:01:002
13852650,3sleep2351rcuc/210:01:002
18962630,3sleep20-21swapper/208:36:022
18962630,3sleep20-21swapper/208:36:022
18962630,3sleep20-21swapper/208:36:022
306702620,4sleep10-21swapper/108:26:041
306702620,4sleep10-21swapper/108:26:041
28992530,4chrt0-21swapper/311:31:023
28992530,4chrt0-21swapper/311:31:023
69392510,1sleep10-21swapper/110:15:591
69392510,1sleep10-21swapper/110:15:591
305802510,3sleep30-21swapper/311:20:543
305802510,3sleep30-21swapper/311:20:543
100102500,3sleep3431rcuc/307:30:593
100102500,3sleep3431rcuc/307:30:593
193599470,8cyclictest7210-21seq11:43:330
193599470,8cyclictest7210-21seq11:43:330
145182470,4sleep30-21swapper/309:10:563
145182470,4sleep30-21swapper/309:10:563
5702460,1chrt0-21swapper/110:00:511
5702460,1chrt0-21swapper/110:00:511
274972420,3sleep30-21swapper/311:11:003
274972420,3sleep30-21swapper/311:11:003
1935994216,24cyclictest1929-21cyclictest09:01:040
1935994216,24cyclictest1929-21cyclictest09:01:040
260432410,3sleep20-21swapper/208:15:482
260432410,3sleep20-21swapper/208:15:482
208692410,3sleep30-21swapper/309:26:043
1937994133,6cyclictest12856-21latency_hist07:40:441
1937994133,6cyclictest12856-21latency_hist07:40:441
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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