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2026-02-21 - 22:20
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #4, slot #1

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack4slot1s.osadl.org (updated Sat Feb 21, 2026 12:44:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
334421070,2chrt0-21swapper/110:11:071
334421070,2chrt0-21swapper/110:11:071
334421070,2chrt0-21swapper/110:11:071
102822770,2chrt10285-21latency09:01:240
102822770,2chrt10285-21latency09:01:240
215842640,4sleep00-21swapper/009:31:230
215842640,4sleep00-21swapper/009:31:230
52452610,3sleep05247-21grep11:41:230
308452600,2sleep30-21swapper/309:56:223
308452600,2sleep30-21swapper/309:56:223
304262570,3chrt0-21swapper/311:21:253
304262570,3chrt0-21swapper/311:21:253
245832560,2chrt24580-21latency_hist09:41:110
245832560,2chrt24580-21latency_hist09:41:110
197372560,2sleep30-21swapper/312:21:143
197372560,2sleep30-21swapper/312:21:143
109952550,3sleep20-21swapper/207:36:232
109952550,3sleep20-21swapper/207:36:232
247872530,2sleep20-21swapper/212:31:302
247872530,2sleep20-21swapper/212:31:302
199732530,3sleep30-21swapper/308:01:213
199732530,3sleep30-21swapper/308:01:213
104792470,3sleep20-21swapper/210:26:562
104792470,3sleep20-21swapper/210:26:562
1226994517,26cyclictest15928-21latency_hist12:11:100
1226994515,3cyclictest0-21swapper/010:26:300
1226994515,3cyclictest0-21swapper/010:26:300
164282440,2sleep016432-21gltestperf12:11:220
164282440,2sleep016432-21gltestperf12:11:220
1226994218,3cyclictest0-21swapper/008:41:220
1226994218,3cyclictest0-21swapper/008:41:220
1226994218,2cyclictest0-21swapper/007:21:270
1226994032,6cyclictest26953-21latency_hist08:21:080
1226994032,6cyclictest26953-21latency_hist08:21:080
1226994032,6cyclictest26953-21latency_hist08:21:080
1226994014,4cyclictest31491-21latency_hist11:26:110
1226994014,4cyclictest31491-21latency_hist11:26:110
1227993932,5cyclictest9523-21latency_hist09:01:071
1227993932,5cyclictest9523-21latency_hist09:01:071
1227993932,5cyclictest9523-21latency_hist09:01:071
140782380,3sleep20-21swapper/207:46:162
317552360,2sleep031914-21/usr/sbin/munin11:26:210
317552360,2sleep031914-21/usr/sbin/munin11:26:210
284362360,2sleep028437-21/usr/sbin/munin08:21:320
1227993628,6cyclictest29525-21sh11:21:071
1227993628,6cyclictest29525-21sh11:21:071
1227993628,6cyclictest29525-21sh11:21:071
27832350,2sleep30-21swapper/311:36:083
27832350,2sleep30-21swapper/311:36:083
189382350,3chrt0-21swapper/307:56:303
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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