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2026-02-14 - 18:14
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #4, slot #1

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack4slot1s.osadl.org (updated Sat Feb 14, 2026 12:44:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3003721460,8sleep1281ktimers/107:26:131
1236821280,1chrt0-21swapper/108:06:051
1542721070,4sleep115428-21head11:06:151
1542721070,4sleep115428-21head11:06:151
1542721070,4sleep115428-21head11:06:151
35512670,3chrt24399-21cyclictest09:06:220
35512670,3chrt24399-21cyclictest09:06:220
297072620,2sleep129708-21cat08:51:161
297072620,2sleep129708-21cat08:51:161
154632560,3sleep115467-21cron09:41:001
154632560,3sleep115467-21cron09:41:001
154632560,3sleep115467-21cron09:41:001
126682520,3sleep30-21swapper/312:26:133
126682520,3sleep30-21swapper/312:26:133
291022460,3chrt0-21swapper/311:41:233
291022460,3chrt0-21swapper/311:41:233
282882430,3chrt0-21swapper/307:21:133
282882430,3chrt0-21swapper/307:21:133
228542420,3sleep30-21swapper/308:31:243
228542420,3sleep30-21swapper/308:31:243
167212420,3sleep30-21swapper/308:16:163
167212420,3sleep30-21swapper/308:16:163
204602410,2sleep20-21swapper/209:51:232
204602410,2sleep20-21swapper/209:51:232
152132410,3chrt0-21swapper/311:06:133
152132410,3chrt0-21swapper/311:06:133
152132410,3chrt0-21swapper/311:06:133
24403993933,4cyclictest18020-21latency_hist12:41:011
24403993933,4cyclictest18020-21latency_hist12:41:011
275082380,3sleep30-21swapper/308:46:113
219422380,3sleep2351rcuc/211:21:242
219422380,3sleep2351rcuc/211:21:242
24402993630,4cyclictest27279-21gltestperf10:11:150
24402993630,4cyclictest27279-21gltestperf10:11:150
55772350,3sleep30-21swapper/312:06:153
55772350,3sleep30-21swapper/312:06:153
73872340,3chrt0-21swapper/312:11:133
6542330,2sleep1281ktimers/107:32:041
6542330,2sleep1281ktimers/107:32:041
143462330,3sleep30-21swapper/309:36:163
143462330,3sleep30-21swapper/309:36:163
143462330,3sleep30-21swapper/309:36:163
24403993225,5cyclictest22130-21gltestperf08:31:151
24403993225,5cyclictest22130-21gltestperf08:31:151
123022320,2sleep20-21swapper/208:06:032
24403993126,3cyclictest12997-21cron11:01:011
24403993126,3cyclictest12997-21cron11:01:011
24403993124,5cyclictest385-21latency_hist09:01:011
24403993124,5cyclictest385-21latency_hist09:01:011
24403993124,5cyclictest385-21latency_hist09:01:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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