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2025-10-23 - 23:14

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #4, slot #1

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack4slot1s.osadl.org (updated Thu Oct 23, 2025 12:44:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
387821050,2chrt3877-21users07:33:321
387821050,2chrt3877-21users07:33:321
1008621020,2chrt0-21swapper/007:53:090
270692900,2sleep0201rcuc/011:28:240
270692900,2sleep0201rcuc/011:28:240
182552880,2sleep118256-21needreboot09:38:271
182552880,2sleep118256-21needreboot09:38:271
127232730,3sleep012726-21unixbench-2d10:48:360
127232730,3sleep012726-21unixbench-2d10:48:360
189562630,3chrt0-21swapper/012:33:160
189562630,3chrt0-21swapper/012:33:160
2737399554,9cyclictest181rcu_preempt12:23:231
2737399554,9cyclictest181rcu_preempt12:23:231
2737399520,8cyclictest181rcu_preempt09:48:201
2737399520,8cyclictest181rcu_preempt09:48:201
147802510,2sleep00-21swapper/009:28:330
147802510,2sleep00-21swapper/009:28:330
2737399504,13cyclictest181rcu_preempt09:33:191
2737399504,13cyclictest181rcu_preempt09:33:191
2737399501,5cyclictest181rcu_preempt11:43:201
2737399501,5cyclictest181rcu_preempt11:43:201
2737399493,6cyclictest181rcu_preempt08:38:201
2737399462,9cyclictest181rcu_preempt09:43:181
2737399462,9cyclictest181rcu_preempt09:43:181
2737399441,5cyclictest181rcu_preempt10:13:211
2737399441,5cyclictest181rcu_preempt10:13:211
31992430,3sleep30-21swapper/308:58:293
48082420,5chrt0-21swapper/011:53:320
48082420,5chrt0-21swapper/011:53:320
2737299423,35cyclictest18579-21kworker/0:3+events_power_efficient12:38:210
2737299423,35cyclictest18579-21kworker/0:3+events_power_efficient12:38:210
291432410,3sleep00-21swapper/008:43:180
2737399411,5cyclictest181rcu_preempt11:18:201
2737399411,5cyclictest181rcu_preempt11:18:201
27372994133,6cyclictest0-21swapper/010:18:220
27372994133,6cyclictest0-21swapper/010:18:220
27372994133,5cyclictest0-21swapper/011:13:240
27372994133,5cyclictest0-21swapper/011:13:240
27372994115,18cyclictest201rcuc/009:13:190
142472400,3sleep30-21swapper/308:03:253
142472400,3sleep30-21swapper/308:03:253
27372993914,4cyclictest201rcuc/011:52:470
27372993914,4cyclictest201rcuc/011:52:470
2737299387,27cyclictest55150irq/47-eth007:53:200
2737299387,27cyclictest55150irq/47-eth007:53:200
2737299384,29cyclictest4622-21sshd07:38:190
2737299382,4cyclictest201rcuc/007:58:200
2737299382,4cyclictest201rcuc/007:58:200
27373993732,3cyclictest6252-21latency_hist07:43:071
2737399371,6cyclictest181rcu_preempt10:38:191
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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