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2026-02-28 - 22:45
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #4, slot #1

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack4slot1s.osadl.org (updated Sat Feb 28, 2026 12:44:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139021370,3sleep20-21swapper/211:36:362
139021370,3sleep20-21swapper/211:36:362
1061221160,3chrt0-21swapper/207:41:392
1061221160,3chrt0-21swapper/207:41:392
464121140,2sleep04644-21grep11:46:310
464121140,2sleep04644-21grep11:46:310
1866721040,3sleep30-21swapper/312:26:143
1866721040,3sleep30-21swapper/312:26:143
309172880,3sleep30-21swapper/308:36:363
309172880,3sleep30-21swapper/308:36:363
253142700,3chrt0-21swapper/311:16:273
253142700,3chrt0-21swapper/311:16:273
44632650,3sleep10-21swapper/108:51:371
44632650,3sleep10-21swapper/108:51:371
175632650,3chrt0-21swapper/110:56:231
175632650,3chrt0-21swapper/110:56:231
326462640,3chrt0-21swapper/208:41:332
326462640,3chrt0-21swapper/208:41:332
89882590,3sleep20-21swapper/210:31:322
89882590,3sleep20-21swapper/210:31:322
82232590,3sleep130771-21cyclictest07:36:361
82232590,3sleep130771-21cyclictest07:36:361
39322590,3sleep10-21swapper/111:46:241
39322590,3sleep10-21swapper/111:46:241
11102590,2chrt1109-21wc08:46:141
11102590,2chrt1109-21wc08:46:141
222602550,3sleep30-21swapper/311:06:343
222602550,3sleep30-21swapper/311:06:343
197452550,3chrt0-21swapper/312:26:343
197452550,3chrt0-21swapper/312:26:343
283822510,4sleep20-21swapper/209:56:352
283822510,4sleep20-21swapper/209:56:352
283822510,4sleep20-21swapper/209:56:352
283822510,4sleep20-21swapper/209:56:352
48942460,2chrt0-21swapper/210:21:272
48942460,2chrt0-21swapper/210:21:272
30772994618,4cyclictest30771-21cyclictest11:31:300
30772994618,4cyclictest30771-21cyclictest11:31:300
18252450,4chrt0-21swapper/307:21:223
316752440,4sleep2351rcuc/208:41:172
316752440,4sleep2351rcuc/208:41:172
30772994219,21cyclictest0-21swapper/009:46:350
30772994219,21cyclictest0-21swapper/009:46:350
30772994218,5cyclictest30771-21cyclictest09:43:550
233722420,3sleep10-21swapper/108:16:361
233722420,3sleep10-21swapper/108:16:361
92952410,1sleep10-21swapper/109:06:291
92952410,1sleep10-21swapper/109:06:291
30772994114,4cyclictest0-21swapper/011:11:160
30772994114,4cyclictest0-21swapper/011:11:160
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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