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2026-03-04 - 00:06
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #4, slot #1

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack4slot1s.osadl.org (updated Tue Mar 03, 2026 12:44:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
211892970,3sleep20-21swapper/211:36:482
211892970,3sleep20-21swapper/211:36:482
228762950,2chrt22875-21sort08:51:230
30212930,3sleep20-21swapper/210:51:252
170382880,2chrt0-21swapper/211:26:392
170382880,2chrt0-21swapper/211:26:392
274502840,1sleep30-21swapper/307:36:293
274502840,1sleep30-21swapper/307:36:293
274502840,1sleep30-21swapper/307:36:293
325282700,3sleep30-21swapper/310:41:373
325282700,3sleep30-21swapper/310:41:373
135712670,3chrt0-21swapper/308:26:263
135712670,3chrt0-21swapper/308:26:263
12672660,3chrt0-21swapper/312:11:343
308922650,2sleep130891-21cron12:06:171
308922650,2sleep130891-21cron12:06:171
262092640,4sleep30-21swapper/310:26:303
262092640,4sleep30-21swapper/310:26:303
293072630,3chrt0-21swapper/212:01:282
293072630,3chrt0-21swapper/212:01:282
134792620,3sleep20-21swapper/211:16:382
134792620,3sleep20-21swapper/211:16:382
134792620,3sleep20-21swapper/211:16:382
5222610,4chrt0-21swapper/210:41:402
5222610,4chrt0-21swapper/210:41:402
166242600,3sleep30-21swapper/308:31:403
166242600,3sleep30-21swapper/308:31:403
317222550,2sleep20-21swapper/207:46:372
317222550,2sleep20-21swapper/207:46:372
316962550,3chrt0-21swapper/110:41:271
316962550,3chrt0-21swapper/110:41:271
38582530,3chrt0-21swapper/310:51:383
38582530,3chrt0-21swapper/310:51:383
229472530,3sleep30-21swapper/310:16:333
229472530,3sleep30-21swapper/310:16:333
229472530,3sleep30-21swapper/310:16:333
223002530,3sleep20-21swapper/207:21:332
223002530,3sleep20-21swapper/207:21:332
187472530,3sleep10-21swapper/110:06:301
187472530,3sleep10-21swapper/110:06:301
74262480,3sleep20-21swapper/212:26:402
74262480,3sleep20-21swapper/212:26:402
184262460,1sleep3431rcuc/308:36:393
184262460,1sleep3431rcuc/308:36:393
17993994418,2cyclictest0-21swapper/009:36:290
17993994418,2cyclictest0-21swapper/009:36:290
211272420,5sleep117991-21cyclictest10:11:321
211272420,5sleep117991-21cyclictest10:11:321
17993994217,3cyclictest18321-21gltestperf11:31:300
17993994217,3cyclictest18321-21gltestperf11:31:300
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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