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2022-12-05 - 01:37

ARM TI AM3354 @800 MHz, Linux 5.10.47-rt46 (Profile)

Latency plot of system in rack #4, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Command line: cyclictest -l50000000 -m -n -a0 -t1 -p99 -i400 -h400 -q
Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 376 highest latencies:
System rack4slot2.osadl.org (updated Sun Dec 04, 2022 12:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
74502740,0irq/46-4a10000025550-1kworker/u3:007:08:020
258559913040,0cyclictest0-21swapper09:01:220
258559912941,0cyclictest943-21runrttasks10:39:170
258559912940,0cyclictest0-21swapper10:25:540
258559912842,0cyclictest0-21swapper08:48:270
258559912839,0cyclictest20041-21aten_r4power_cu11:35:110
258559912836,0cyclictest0-21swapper11:16:190
258559912741,0cyclictest0-21swapper07:40:010
258559912648,0cyclictest0-21swapper11:26:130
258559912641,0cyclictest0-21swapper07:10:450
258559912639,0cyclictest0-21swapper08:42:580
258559912551,0cyclictest7350irq/45-4a10000008:55:260
258559912551,0cyclictest0-21swapper11:10:520
258559912541,0cyclictest0-21swapper08:54:450
258559912540,0cyclictest0-21swapper09:05:550
258559912540,0cyclictest0-21swapper07:31:020
258559912539,0cyclictest0-21swapper11:50:250
258559912537,0cyclictest0-21swapper12:26:260
258559912535,0cyclictest0-21swapper07:38:080
258559912441,0cyclictest0-21swapper09:45:180
258559912439,0cyclictest0-21swapper10:00:200
258559912436,0cyclictest0-21swapper07:47:190
258559912340,0cyclictest0-21swapper12:33:510
258559912339,0cyclictest0-21swapper10:50:190
258559912339,0cyclictest0-21swapper10:10:230
258559912337,0cyclictest0-21swapper10:55:380
258559912337,0cyclictest0-21swapper08:35:240
258559912334,0cyclictest0-21swapper12:18:430
258559912248,0cyclictest0-21swapper11:31:090
258559912241,0cyclictest22720-21runrttasks08:31:370
258559912240,0cyclictest0-21swapper10:45:480
258559912240,0cyclictest0-21swapper09:57:580
258559912239,0cyclictest0-21swapper10:40:530
258559912236,0cyclictest0-21swapper07:20:410
258559912148,0cyclictest0-21swapper07:25:140
258559912140,0cyclictest4748-21/usr/sbin/munin09:15:180
258559912139,0cyclictest10960-21runrttasks07:58:450
258559912138,0cyclictest0-21swapper12:35:590
258559912138,0cyclictest0-21swapper12:00:250
258559912138,0cyclictest0-21swapper09:25:580
258559912137,0cyclictest0-21swapper11:00:030
258559912137,0cyclictest0-21swapper09:50:240
258559912137,0cyclictest0-21swapper08:15:320
258559912135,0cyclictest0-21swapper08:10:120
258559912053,0cyclictest7350irq/45-4a10000011:56:480
258559912039,0cyclictest0-21swapper10:21:100
258559912039,0cyclictest0-21swapper07:50:110
258559912038,0cyclictest0-21swapper07:15:070
258559912036,0cyclictest0-21swapper09:10:440
258559912036,0cyclictest0-21swapper08:05:430
258559911941,0cyclictest0-21swapper10:06:150
258559911936,0cyclictest0-21swapper12:08:270
258559911936,0cyclictest0-21swapper09:23:120
258559911927,0cyclictest10886-21runrttasks09:32:020
258559911841,0cyclictest0-21swapper11:05:590
258559911838,0cyclictest0-21swapper08:21:020
258559911837,0cyclictest0-21swapper12:12:000
258559911834,0cyclictest0-21swapper08:26:050
258559911737,0cyclictest0-21swapper11:21:080
258559911545,0cyclictest7350irq/45-4a10000012:20:430
258559911536,0cyclictest0-21swapper11:45:170
258559911536,0cyclictest0-21swapper09:40:570
258559911534,0cyclictest0-21swapper10:32:460
258559911440,0cyclictest0-21swapper09:36:070
258559911334,0cyclictest0-21swapper10:19:360
258559910943,0cyclictest12181-21/usr/sbin/munin08:01:000
25855998666,0cyclictest0-21swapper11:41:080
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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