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2025-02-08 - 17:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack5slot1.osadl.org (updated Sat Feb 08, 2025 12:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
119003914790,0EcMasterDemoSyn0-21swapper/612:18:576
13999391710,3EcMasterDemoSyn986599cyclictest12:39:130
483639970,0EcMasterDemoSyn484729tAtEmLog_012:34:095
227739920,0EcMasterDemoSyn228729tAtEmLog_009:56:575
1256739890,0EcMasterDemoSyn1257729tAtEmLog_010:32:275
3241939880,0EcMasterDemoSyn3242929tAtEmLog_007:50:125
2493939880,0EcMasterDemoSyn2494929tAtEmLog_011:07:585
2030439880,0EcMasterDemoSyn2031429tAtEmLog_011:28:145
2281539860,0EcMasterDemoSyn2282629tAtEmLog_011:48:305
1399939860,0EcMasterDemoSyn1400929tAtEmLog_012:39:135
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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