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2025-11-17 - 19:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack5slot1.osadl.org (updated Mon Nov 17, 2025 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2198939850,0EcMasterDemoSyn2199929tAtEmLog_009:35:565
985539830,0EcMasterDemoSyn986529tAtEmLog_008:50:175
450239820,0EcMasterDemoSyn451429tAtEmLog_012:13:085
2705839820,0EcMasterDemoSyn2706829tAtEmLog_008:19:525
1996939820,0EcMasterDemoSyn1997929tAtEmLog_008:04:395
1758939820,0EcMasterDemoSyn1759929tAtEmLog_007:59:355
1287739820,0EcMasterDemoSyn1288729tAtEmLog_007:49:265
288739810,0EcMasterDemoSyn289729tAtEmLog_007:29:085
2246839810,0EcMasterDemoSyn2247829tAtEmLog_010:26:395
2233239810,0EcMasterDemoSyn2234229tAtEmLog_008:09:425
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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