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2024-04-26 - 22:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Fri Apr 26, 2024 13:01:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2091199216185,6cyclictest0-21swapper/311:08:3923
2091199216185,6cyclictest0-21swapper/311:08:3923
2091199216185,6cyclictest0-21swapper/311:08:3923
2091199205182,20cyclictest0-21swapper/310:37:4123
2091199205182,20cyclictest0-21swapper/310:37:4123
2091199205182,20cyclictest0-21swapper/310:37:4023
209399920488,107cyclictest0-21swapper/2709:00:0120
209399920488,107cyclictest0-21swapper/2709:00:0120
2093199202153,17cyclictest0-21swapper/2110:50:4814
2093199202153,17cyclictest0-21swapper/2110:50:4714
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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