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2023-03-24 - 04:57

x86 Intel Xeon E5-2650Lv2 @1700 MHz, Linux 4.18.7-rt5 (Profile)

Latency plot of system in rack #6, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Up99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Mon Mar 20, 2023 02:52:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
501999271267,2cyclictest0-21swapper/519:45:2635
501999271267,2cyclictest0-21swapper/519:45:2535
5050992080,67cyclictest0-21swapper/2923:10:2422
5050992080,67cyclictest0-21swapper/2923:10:2322
5050992031,118cyclictest0-21swapper/2923:05:2722
5050992031,118cyclictest0-21swapper/2923:05:2722
5050992000,1cyclictest0-21swapper/2922:02:2922
5050992000,1cyclictest0-21swapper/2922:02:2822
5050991930,2cyclictest0-21swapper/2921:25:3322
5050991930,2cyclictest0-21swapper/2921:25:3222
5050991930,2cyclictest0-21swapper/2921:25:3222
5055991921,71cyclictest0-21swapper/3322:15:1627
5055991921,71cyclictest0-21swapper/3322:15:1527
5055991921,71cyclictest0-21swapper/3322:15:1527
50559919143,50cyclictest0-21swapper/3321:39:4427
50559919143,50cyclictest0-21swapper/3321:39:4427
5061991900,2cyclictest0-21swapper/3600:20:0330
5061991900,2cyclictest0-21swapper/3600:20:0330
5050991901,172cyclictest0-21swapper/2900:16:5922
5050991901,172cyclictest0-21swapper/2900:16:5922
50559918942,108cyclictest12862-21qemu-system-x8622:47:0727
50559918942,108cyclictest12862-21qemu-system-x8622:47:0627
50559918845,133cyclictest0-21swapper/3323:45:2827
50559918845,133cyclictest0-21swapper/3323:45:2727
5050991861,182cyclictest0-21swapper/2923:45:0122
5050991861,182cyclictest0-21swapper/2923:45:0122
5050991850,102cyclictest0-21swapper/2922:50:2222
5050991850,102cyclictest0-21swapper/2922:50:2122
50559918447,85cyclictest0-21swapper/3323:50:4027
50559918447,85cyclictest0-21swapper/3323:50:3927
50559918440,55cyclictest0-21swapper/3322:30:3827
50559918440,55cyclictest0-21swapper/3322:30:3827
5050991840,121cyclictest0-21swapper/2922:14:5222
5050991840,121cyclictest0-21swapper/2922:14:5222
50559918353,53cyclictest0-21swapper/3300:26:0127
50559918353,53cyclictest0-21swapper/3300:26:0027
50559918347,76cyclictest0-21swapper/3322:06:4027
50559918347,76cyclictest0-21swapper/3322:06:4027
50509918383,62cyclictest12515-21run-parts23:55:2622
50509918383,62cyclictest12515-21run-parts23:55:2622
50389918335,143cyclictest0-21swapper/1922:15:1611
50389918335,143cyclictest0-21swapper/1922:15:1611
50389918335,143cyclictest0-21swapper/1922:15:1511
503499182176,3cyclictest37862-21qemu-system-x8619:30:148
503499182176,3cyclictest37862-21qemu-system-x8619:30:138
50359918139,136cyclictest25031-21CPU9
50359918139,136cyclictest25031-21CPU9
5061991800,4cyclictest10897-21CPU30
5061991800,4cyclictest10897-21CPU30
5050991801,98cyclictest0-21swapper/2922:16:5322
5050991801,98cyclictest0-21swapper/2922:16:5322
5050991801,98cyclictest0-21swapper/2922:16:5322
5019991801,6cyclictest0-21swapper/522:50:2735
5019991801,6cyclictest0-21swapper/522:50:2735
5062991791,7cyclictest0-21swapper/3700:15:3431
5062991791,7cyclictest0-21swapper/3700:15:3431
50559917945,90cyclictest0-21swapper/3321:58:4827
50559917945,90cyclictest0-21swapper/3321:58:4827
5050991791,138cyclictest0-21swapper/2922:36:2622
5050991791,138cyclictest0-21swapper/2922:36:2622
5050991791,138cyclictest0-21swapper/2922:36:2522
50559917848,91cyclictest0-21swapper/3321:48:5327
50559917848,91cyclictest0-21swapper/3321:48:5227
5061991770,174cyclictest909-21sshd21:14:2230
5061991770,174cyclictest909-21sshd21:14:2230
50559917743,77cyclictest0-21swapper/3323:02:0727
50559917743,77cyclictest0-21swapper/3323:02:0627
5046991771,172cyclictest30258-21sshd21:43:3618
5046991771,172cyclictest30258-21sshd21:43:3618
5046991771,172cyclictest30258-21sshd21:43:3618
50389917764,74cyclictest0-21swapper/1921:15:0511
50389917764,74cyclictest0-21swapper/1921:15:0511
50389917730,141cyclictest26093-21sshd22:25:2111
50389917730,141cyclictest26093-21sshd22:25:2111
442221770,7sleep23504299cyclictest00:28:2916
442221770,7sleep23504299cyclictest00:28:2816
63521760,7sleep1501399cyclictest22:35:271
63521760,7sleep1501399cyclictest22:35:261
63521760,7sleep1501399cyclictest22:35:261
5061991760,173cyclictest10645-21sshd00:28:5830
5061991760,173cyclictest10645-21sshd00:28:5730
50559917640,83cyclictest0-21swapper/3300:00:5427
50559917640,83cyclictest0-21swapper/3300:00:5427
50559917640,71cyclictest12939-21CPU27
50559917640,71cyclictest12939-21CPU27
5050991761,171cyclictest0-21swapper/2922:28:0922
5050991761,171cyclictest0-21swapper/2922:28:0822
50559917541,109cyclictest0-21swapper/3322:57:2427
50559917541,109cyclictest0-21swapper/3322:57:2327
50559917452,80cyclictest0-21swapper/3323:59:5527
50559917452,80cyclictest0-21swapper/3323:59:5427
50559917438,132cyclictest0-21swapper/3300:05:3127
50559917438,132cyclictest0-21swapper/3300:05:3027
50559917431,58cyclictest0-21swapper/3322:20:1927
50559917431,58cyclictest0-21swapper/3322:20:1827
50559917430,129cyclictest0-21swapper/3300:17:1527
50559917430,129cyclictest0-21swapper/3300:17:1427
50389917436,135cyclictest0-21swapper/1922:44:0111
50389917436,135cyclictest0-21swapper/1922:44:0111
5061991731,3cyclictest0-21swapper/3622:35:5030
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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