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2026-05-20 - 13:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Wed May 20, 2026 01:02:15)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
957899219216,2cyclictest0-21swapper/319:55:2223
957899219216,2cyclictest0-21swapper/319:55:2123
960499209193,8cyclictest0-21swapper/2420:40:0617
960499209193,8cyclictest0-21swapper/2420:40:0617
960499206198,4cyclictest37351-21CPU17
960499206198,4cyclictest37351-21CPU17
958599206181,6cyclictest0-21swapper/923:59:2239
958599206181,6cyclictest0-21swapper/923:59:2239
958599206181,6cyclictest0-21swapper/923:59:2139
960499204196,6cyclictest0-21swapper/2420:00:0117
960499204196,6cyclictest0-21swapper/2420:00:0117
961899203195,6cyclictest0-21swapper/3620:52:0230
961899203195,6cyclictest0-21swapper/3620:52:0130
960499203195,6cyclictest3535-21qemu-system-x8622:55:4417
960499203195,6cyclictest3535-21qemu-system-x8622:55:4417
961899201195,4cyclictest0-21swapper/3622:04:2230
961899201195,4cyclictest0-21swapper/3622:04:2230
961899200193,5cyclictest24952-21packagekitd23:18:3930
961899200193,5cyclictest24952-21packagekitd23:18:3830
961799199182,15cyclictest0-21swapper/3523:56:1429
961799199182,15cyclictest0-21swapper/3523:56:1429
961799199182,15cyclictest0-21swapper/3523:56:1429
959499199188,6cyclictest0-21swapper/1523:56:137
959499199188,6cyclictest0-21swapper/1523:56:137
959499199188,6cyclictest0-21swapper/1523:56:137
959299199191,4cyclictest3546-21CPU5
959299199191,4cyclictest3546-21CPU5
960499198190,6cyclictest0-21swapper/2420:25:2117
960499198190,6cyclictest0-21swapper/2420:25:2117
959399198149,46cyclictest0-21swapper/1422:36:566
959399198149,46cyclictest0-21swapper/1422:36:556
961899197190,5cyclictest0-21swapper/3623:29:1630
961899197190,5cyclictest0-21swapper/3623:29:1630
961899197190,5cyclictest0-21swapper/3623:29:1630
961899196190,3cyclictest2324-21systemd21:55:1930
961899196190,3cyclictest2324-21systemd21:55:1930
957799196188,5cyclictest0-21swapper/222:10:3012
957799196188,5cyclictest0-21swapper/222:10:3012
957699196187,5cyclictest2464-21CPU1
957699196187,5cyclictest2464-21CPU1
961899195190,4cyclictest0-21swapper/3621:05:4630
961899195190,4cyclictest0-21swapper/3621:05:4530
961899195189,4cyclictest0-21swapper/3620:30:0430
961899195189,4cyclictest0-21swapper/3620:30:0330
961699195186,4cyclictest0-21swapper/3420:05:0328
961699195186,4cyclictest0-21swapper/3420:05:0328
960499195184,9cyclictest0-21swapper/2422:54:0517
960499195184,9cyclictest0-21swapper/2422:54:0417
961899194188,4cyclictest0-21swapper/3622:45:4130
961899194188,4cyclictest0-21swapper/3622:45:4030
961899194188,4cyclictest0-21swapper/3622:45:4030
961899194188,4cyclictest0-21swapper/3621:10:3230
961899194188,4cyclictest0-21swapper/3621:10:3230
960499194182,11cyclictest0-21swapper/2420:24:5217
960499194182,11cyclictest0-21swapper/2420:24:5217
961899193187,5cyclictest0-21swapper/3622:40:2130
961899193187,5cyclictest0-21swapper/3622:40:2130
961899193187,4cyclictest0-21swapper/3620:15:1830
961899193187,4cyclictest0-21swapper/3620:15:1830
961899193185,5cyclictest2461-21CPU30
961899193185,5cyclictest2461-21CPU30
961899193185,4cyclictest2464-21CPU30
957699193189,2cyclictest0-21swapper/122:42:211
957699193189,2cyclictest0-21swapper/122:42:211
957699193181,6cyclictest37356-21CPU1
957699193181,6cyclictest37356-21CPU1
957699193181,6cyclictest37356-21CPU1
961899192185,4cyclictest1384-21rs:main30
961899192185,4cyclictest1384-21rs:main30
961899192182,7cyclictest0-21swapper/3623:30:1830
961899192182,7cyclictest0-21swapper/3623:30:1830
960899192181,9cyclictest0-21swapper/2823:33:5021
960899192181,9cyclictest0-21swapper/2823:33:5021
958699192176,14cyclictest0-21swapper/1023:30:212
958699192176,14cyclictest0-21swapper/1023:30:212
957699192185,5cyclictest1442-21gdbus21:43:031
957699192185,5cyclictest1442-21gdbus21:43:031
961899191185,4cyclictest0-21swapper/3621:01:3230
961899191185,4cyclictest0-21swapper/3621:01:3230
961899191183,5cyclictest2459-21CPU30
961899191180,7cyclictest37270-21CPU30
961899191180,7cyclictest37270-21CPU30
961899191180,7cyclictest37270-21CPU30
960499191186,3cyclictest0-21swapper/2420:01:2617
960499191186,3cyclictest0-21swapper/2420:01:2517
960499191178,7cyclictest171rcu_preempt00:04:1417
960499191178,7cyclictest171rcu_preempt00:04:1317
960499191178,7cyclictest171rcu_preempt00:04:1317
961899190185,4cyclictest0-21swapper/3621:44:4330
961899190185,4cyclictest0-21swapper/3621:44:4330
961899190172,15cyclictest0-21swapper/3621:45:2130
961899190172,15cyclictest0-21swapper/3621:45:2130
961199190182,4cyclictest3610-21CPU25
961199190182,4cyclictest3610-21CPU25
960499190186,3cyclictest0-21swapper/2420:37:5517
960499190186,3cyclictest0-21swapper/2420:37:5417
960499190110,65cyclictest3541-21CPU17
960499190110,65cyclictest3541-21CPU17
960499190110,65cyclictest3541-21CPU17
959299190183,5cyclictest0-21swapper/1322:34:395
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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