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2024-04-27 - 09:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Sat Apr 27, 2024 01:01:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2883399265261,2cyclictest0-21swapper/3222:39:3626
2883399265261,2cyclictest0-21swapper/3222:39:3526
2879599201191,9cyclictest0-21swapper/021:51:280
2879599201191,9cyclictest0-21swapper/021:51:280
2879599201191,9cyclictest0-21swapper/021:51:280
2883299190168,14cyclictest0-21swapper/3119:45:0325
2879599188173,12cyclictest0-21swapper/023:57:340
2879599188173,12cyclictest0-21swapper/023:57:330
2879599188173,12cyclictest0-21swapper/023:57:330
2883399180167,11cyclictest0-21swapper/3221:15:3126
2883399180167,11cyclictest0-21swapper/3221:15:3126
2883399180167,11cyclictest0-21swapper/3221:15:3126
2883399179172,5cyclictest0-21swapper/3221:10:1626
2883399179172,5cyclictest0-21swapper/3221:10:1626
287959917761,111cyclictest11900-21CPU0
287959917761,111cyclictest11900-21CPU0
2883399176159,13cyclictest1930-21gdbus00:37:3626
2883399176159,13cyclictest1930-21gdbus00:37:3626
2883399176159,13cyclictest1930-21gdbus00:37:3526
2882199175163,10cyclictest0-21swapper/2222:43:5515
2882199175163,10cyclictest0-21swapper/2222:43:5515
2882199175163,10cyclictest0-21swapper/2222:43:5515
2883399174140,30cyclictest0-21swapper/3200:10:2526
2883399174140,30cyclictest0-21swapper/3200:10:2526
2883399174140,30cyclictest0-21swapper/3200:10:2426
2882399174147,24cyclictest0-21swapper/2321:56:1916
2882399174147,24cyclictest0-21swapper/2321:56:1916
2882399174147,24cyclictest0-21swapper/2321:56:1916
28809991731,7cyclictest16517-21sshd22:34:294
28809991731,7cyclictest16517-21sshd22:34:284
28809991731,7cyclictest16517-21sshd22:34:284
2879699173127,30cyclictest0-21swapper/121:37:031
2879699173127,30cyclictest0-21swapper/121:37:031
2881899172127,34cyclictest11905-21CPU13
2881899172127,34cyclictest11905-21CPU13
2882199170154,8cyclictest0-21swapper/2221:29:4415
2882199170154,8cyclictest0-21swapper/2221:29:4415
2880999170128,34cyclictest0-21swapper/1221:51:534
2880999170128,34cyclictest0-21swapper/1221:51:534
2880999170128,34cyclictest0-21swapper/1221:51:534
2883299169159,2cyclictest0-21swapper/3122:34:1825
2883299169159,2cyclictest0-21swapper/3122:34:1825
2883299169159,2cyclictest0-21swapper/3122:34:1825
2882199169157,9cyclictest0-21swapper/2221:31:5415
2882199169157,9cyclictest0-21swapper/2221:31:5315
2883399168149,9cyclictest2781rcuc/3223:49:4726
2883399168149,9cyclictest2781rcuc/3223:49:4726
2883399168148,14cyclictest1526-21dbus-daemon22:46:1826
2883399168148,14cyclictest1526-21dbus-daemon22:46:1826
2883299168148,8cyclictest0-21swapper/3100:17:5125
2883299168148,8cyclictest0-21swapper/3100:17:5025
2881199168135,27cyclictest0-21swapper/1422:20:446
2881199168135,27cyclictest0-21swapper/1422:20:446
2880699168165,2cyclictest0-21swapper/923:25:2439
2880699168165,2cyclictest0-21swapper/923:25:2439
2883399167158,7cyclictest0-21swapper/3222:50:3026
2883399167158,7cyclictest0-21swapper/3222:50:3026
2883399167158,7cyclictest0-21swapper/3222:50:3026
2883399167157,8cyclictest0-21swapper/3200:16:3226
2883399167157,8cyclictest0-21swapper/3200:16:3226
2883399167154,8cyclictest0-21swapper/3221:55:5626
2883399167154,8cyclictest0-21swapper/3221:55:5626
2883399167154,8cyclictest0-21swapper/3221:55:5626
2882199167161,5cyclictest0-21swapper/2200:03:3415
2882199167161,5cyclictest0-21swapper/2200:03:3415
2882199167161,5cyclictest0-21swapper/2200:03:3415
2883399166159,3cyclictest0-21swapper/3222:24:3626
2883399166159,3cyclictest0-21swapper/3222:24:3626
2883399166148,10cyclictest0-21swapper/3223:00:2026
2883399166148,10cyclictest0-21swapper/3223:00:2026
2883399166148,10cyclictest0-21swapper/3223:00:2026
2883399166147,16cyclictest0-21swapper/3223:07:0326
2883399166147,16cyclictest0-21swapper/3223:07:0326
2883399166147,16cyclictest0-21swapper/3223:07:0326
2883399165144,11cyclictest0-21swapper/3221:36:1626
2883399165144,11cyclictest0-21swapper/3221:36:1626
2883299165105,20cyclictest0-21swapper/3100:26:0925
2883299165105,20cyclictest0-21swapper/3100:26:0925
2883299165105,20cyclictest0-21swapper/3100:26:0825
2879599165144,10cyclictest0-21swapper/022:26:070
2879599165144,10cyclictest0-21swapper/022:26:070
2879599165144,10cyclictest0-21swapper/022:26:070
2883399163151,10cyclictest0-21swapper/3222:04:4326
2883399163151,10cyclictest0-21swapper/3222:04:4326
2883399163151,10cyclictest0-21swapper/3222:04:4326
2883299163141,10cyclictest0-21swapper/3119:47:1325
2883299163141,10cyclictest0-21swapper/3119:47:1325
2882399163133,26cyclictest0-21swapper/2322:09:1816
2882399163133,26cyclictest0-21swapper/2322:09:1816
2882399163133,26cyclictest0-21swapper/2322:09:1816
2883399162144,10cyclictest0-21swapper/3221:24:2626
2883399162144,10cyclictest0-21swapper/3221:24:2626
2883399162144,10cyclictest0-21swapper/3221:24:2626
28809991623,78cyclictest4907-21CPU4
28809991623,78cyclictest4907-21CPU4
28809991623,78cyclictest4907-21CPU4
2879599162111,41cyclictest11901-21CPU0
2879599162111,41cyclictest11901-21CPU0
2879599162111,41cyclictest11901-21CPU0
2883399161153,6cyclictest0-21swapper/3222:14:5326
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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