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2022-01-19 - 09:46

Intel(R) Xeon(R) CPU E5-2650L v2 @ 1.70GHz, Linux 4.18.7-rt5 (Profile)

Latency plot of system in rack #6, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Up99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Thu Dec 30, 2021 14:49:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2769299220215,2cyclictest0-21swapper/3511:00:1629
2769299220215,2cyclictest0-21swapper/3511:00:1529
2769099211207,2cyclictest0-21swapper/3410:57:3028
2769099211207,2cyclictest0-21swapper/3410:57:2928
276809920930,172cyclictest0-21swapper/2911:22:2022
276809920930,172cyclictest0-21swapper/2911:22:2022
2765999207204,1cyclictest0-21swapper/1407:25:086
2764399202195,3cyclictest11006-21CPU12
2764399202195,3cyclictest11006-21CPU12
2764399199191,6cyclictest0-21swapper/211:33:4112
2764399199191,6cyclictest0-21swapper/211:33:4012
2764399198192,4cyclictest0-21swapper/211:25:3412
2764399198192,4cyclictest0-21swapper/211:25:3312
2765099197191,3cyclictest11007-21CPU38
2765099197191,3cyclictest11007-21CPU38
2764399197191,4cyclictest0-21swapper/210:57:3612
2764399197191,4cyclictest0-21swapper/210:57:3512
2764399196190,4cyclictest0-21swapper/210:15:2212
2764399196189,5cyclictest0-21swapper/211:49:0812
2764399196189,5cyclictest0-21swapper/211:49:0812
2764399196187,6cyclictest0-21swapper/212:36:5812
2764399196187,6cyclictest0-21swapper/212:36:5812
2764399195189,4cyclictest0-21swapper/212:16:2412
2764399195189,4cyclictest0-21swapper/212:16:2312
2764399195189,4cyclictest0-21swapper/210:51:2312
2764399195189,4cyclictest0-21swapper/209:10:5112
2764399195189,4cyclictest0-21swapper/209:10:5112
2764399195188,5cyclictest0-21swapper/209:52:2312
2764399195188,5cyclictest0-21swapper/209:52:2312
2764399195186,7cyclictest0-21swapper/210:02:3312
276739919437,67cyclictest0-21swapper/2411:25:1717
276739919437,67cyclictest0-21swapper/2411:25:1617
2764399194188,4cyclictest0-21swapper/212:02:3112
2764399194188,4cyclictest0-21swapper/212:02:3012
276659919337,151cyclictest0-21swapper/1910:02:3011
2764399193189,2cyclictest0-21swapper/209:25:1512
2764399193189,2cyclictest0-21swapper/209:25:1512
2764399193187,4cyclictest0-21swapper/211:05:3712
2764399193187,4cyclictest0-21swapper/211:05:3712
2764399193187,4cyclictest0-21swapper/210:47:4812
2764399193187,4cyclictest0-21swapper/210:47:4812
2764399192186,4cyclictest0-21swapper/210:13:0912
2764399192183,6cyclictest36181-21sh11:10:2812
2764399192183,6cyclictest36181-21sh11:10:2712
2764399191185,4cyclictest644-21sshd11:53:2612
2764399191185,4cyclictest644-21sshd11:53:2512
2764399191185,4cyclictest0-21swapper/211:00:1612
2764399191185,4cyclictest0-21swapper/211:00:1512
2764399191184,5cyclictest0-21swapper/209:58:5312
2764399191184,5cyclictest0-21swapper/209:58:5312
2764399191184,5cyclictest0-21swapper/209:58:5212
2764999190182,4cyclictest11010-21CPU37
2764999190182,4cyclictest11010-21CPU37
2764399189182,5cyclictest0-21swapper/212:22:2512
2764399189182,5cyclictest0-21swapper/212:22:2412
2764399189182,5cyclictest0-21swapper/209:35:0912
2764399189182,5cyclictest0-21swapper/209:35:0812
2764399189181,6cyclictest0-21swapper/210:27:0212
2764399189181,6cyclictest0-21swapper/210:27:0112
2764399189173,11cyclictest0-21swapper/210:43:4412
2764399189173,11cyclictest0-21swapper/210:43:4412
2764399188183,3cyclictest0-21swapper/209:46:2612
2764399188183,3cyclictest0-21swapper/209:46:2612
2764399188182,4cyclictest0-21swapper/211:42:0112
2764399188182,4cyclictest0-21swapper/211:42:0012
2764399188182,4cyclictest0-21swapper/207:29:0012
2764399187182,3cyclictest8389-21sshd10:38:1112
2764399187182,3cyclictest8389-21sshd10:38:1012
2764399187181,4cyclictest0-21swapper/211:17:1912
2764399187181,4cyclictest0-21swapper/211:17:1912
2764399187181,4cyclictest0-21swapper/209:32:4012
2764399187181,4cyclictest0-21swapper/209:32:4012
2764399187181,4cyclictest0-21swapper/208:05:0112
2764399187181,4cyclictest0-21swapper/208:05:0012
2764399187171,9cyclictest0-21swapper/212:29:3612
2764399187171,9cyclictest0-21swapper/212:29:3512
276399918725,126cyclictest0-21swapper/011:20:130
276399918725,126cyclictest0-21swapper/011:20:120
27696991862,4cyclictest5894-21CPU32
27696991862,4cyclictest5894-21CPU32
276889918612,61cyclictest0-21swapper/3209:57:0626
276889918612,61cyclictest0-21swapper/3209:57:0626
276889918612,61cyclictest0-21swapper/3209:57:0526
2764399186180,4cyclictest0-21swapper/211:56:0312
2764399186180,4cyclictest0-21swapper/211:56:0212
2764399186180,4cyclictest0-21swapper/211:36:3812
2764399186180,4cyclictest0-21swapper/210:05:2012
2764399186180,4cyclictest0-21swapper/210:05:2012
2764399186179,5cyclictest1246-21dbus-daemon10:21:4912
2764399186179,5cyclictest1246-21dbus-daemon10:21:4812
2764399186179,5cyclictest0-21swapper/210:31:2712
2764399186179,5cyclictest0-21swapper/210:31:2612
276739918546,132cyclictest0-21swapper/2411:18:0117
276739918546,132cyclictest0-21swapper/2411:18:0117
2764399185179,4cyclictest0-21swapper/208:25:1012
2764399185179,4cyclictest0-21swapper/208:25:1012
2764399185175,6cyclictest6055-21CPU12
2764399185175,6cyclictest6055-21CPU12
27696991843,4cyclictest5752-21CPU32
27696991843,4cyclictest5752-21CPU32
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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