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2022-05-26 - 20:14

x86 Intel Xeon E5-2650Lv2 @1700 MHz, Linux 4.18.7-rt5 (Profile)

Latency plot of system in rack #6, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Up99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Fri Apr 22, 2022 10:07:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
25945992362,217cyclictest0-21swapper/3008:50:2824
25945992362,217cyclictest0-21swapper/3008:50:2724
25945992182,208cyclictest19425-21CPU24
25945992182,208cyclictest19425-21CPU24
25945992131,209cyclictest0-21swapper/3007:58:1624
25945992131,209cyclictest0-21swapper/3007:58:1624
25945992081,117cyclictest0-21swapper/3008:45:1824
25945992081,117cyclictest0-21swapper/3008:45:1724
25945992050,183cyclictest0-21swapper/3009:08:4524
25945992050,183cyclictest0-21swapper/3009:08:4524
25945992000,1cyclictest0-21swapper/3007:45:2024
25945991960,1cyclictest0-21swapper/3007:37:0724
25945991950,192cyclictest0-21swapper/3007:17:3724
25945991950,192cyclictest0-21swapper/3007:17:3624
259579919443,147cyclictest0-21swapper/3808:45:1932
259579919443,147cyclictest0-21swapper/3808:45:1932
25945991941,161cyclictest0-21swapper/3009:15:1724
25945991941,161cyclictest0-21swapper/3009:15:1724
25945991920,1cyclictest0-21swapper/3007:25:5924
25945991920,1cyclictest0-21swapper/3007:25:5924
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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