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2023-12-06 - 06:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Wed Dec 06, 2023 01:00:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
107199207197,7cyclictest0-21swapper/2422:24:2617
107199207197,7cyclictest0-21swapper/2422:24:2617
105399200197,2cyclictest0-21swapper/823:50:2538
105399200197,2cyclictest0-21swapper/823:50:2538
105399200197,2cyclictest0-21swapper/823:50:2538
1045991971,186cyclictest10889-21cstates23:05:221
1045991971,186cyclictest10889-21cstates23:05:221
1045991971,186cyclictest10889-21cstates23:05:211
1045991961,190cyclictest15212-21sshd22:41:371
1045991961,190cyclictest15212-21sshd22:41:361
106099193171,20cyclictest0-21swapper/1523:35:437
106099193171,20cyclictest0-21swapper/1523:35:437
106099189167,19cyclictest3513-21lxd20:54:247
106099189167,19cyclictest3513-21lxd20:54:247
1045991892,182cyclictest18937-21CPU1
1045991892,182cyclictest18937-21CPU1
1045991892,182cyclictest18937-21CPU1
107599188184,2cyclictest0-21swapper/2721:35:4420
107599188184,2cyclictest0-21swapper/2721:35:4420
1073991880,113cyclictest0-21swapper/2521:40:2318
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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