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2024-04-21 - 04:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Sun Apr 21, 2024 01:01:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2833299273270,2cyclictest0-21swapper/2023:02:0913
2833299273270,2cyclictest0-21swapper/2023:02:0913
2833299273270,2cyclictest0-21swapper/2023:02:0913
2834099229226,2cyclictest0-21swapper/2722:45:0720
2834099229226,2cyclictest0-21swapper/2722:45:0720
2834099229226,2cyclictest0-21swapper/2722:45:0720
2832699210198,7cyclictest0-21swapper/1500:38:097
2832699210198,7cyclictest0-21swapper/1500:38:097
2832699210198,7cyclictest0-21swapper/1500:38:087
2831699200145,45cyclictest0-21swapper/622:07:4636
2831699200145,45cyclictest0-21swapper/622:07:4636
2831699200145,45cyclictest0-21swapper/622:07:4536
28316991943,186cyclictest4912-21CPU36
28316991943,186cyclictest4912-21CPU36
2831699193164,27cyclictest0-21swapper/621:35:3136
2831699193164,27cyclictest0-21swapper/621:35:3136
2831699193164,27cyclictest0-21swapper/621:35:3136
2832699192175,15cyclictest0-21swapper/1522:13:097
2832699192175,15cyclictest0-21swapper/1522:13:097
2832699192175,15cyclictest0-21swapper/1522:13:097
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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