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2024-04-27 - 11:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Sat Apr 27, 2024 01:01:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2883399265261,2cyclictest0-21swapper/3222:39:3626
2883399265261,2cyclictest0-21swapper/3222:39:3526
2879599201191,9cyclictest0-21swapper/021:51:280
2879599201191,9cyclictest0-21swapper/021:51:280
2879599201191,9cyclictest0-21swapper/021:51:280
2883299190168,14cyclictest0-21swapper/3119:45:0325
2879599188173,12cyclictest0-21swapper/023:57:340
2879599188173,12cyclictest0-21swapper/023:57:330
2879599188173,12cyclictest0-21swapper/023:57:330
2883399180167,11cyclictest0-21swapper/3221:15:3126
2883399180167,11cyclictest0-21swapper/3221:15:3126
2883399180167,11cyclictest0-21swapper/3221:15:3126
2883399179172,5cyclictest0-21swapper/3221:10:1626
2883399179172,5cyclictest0-21swapper/3221:10:1626
287959917761,111cyclictest11900-21CPU0
287959917761,111cyclictest11900-21CPU0
2883399176159,13cyclictest1930-21gdbus00:37:3626
2883399176159,13cyclictest1930-21gdbus00:37:3626
2883399176159,13cyclictest1930-21gdbus00:37:3526
2882199175163,10cyclictest0-21swapper/2222:43:5515
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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