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2019-07-16 - 02:53

Intel(R) Xeon(R) CPU E5-2650L v2 @ 1.70GHz, Linux 4.18.7-rt5 (Profile)

Latency plot of system in rack #6, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Up99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Mon Jul 15, 2019 02:48:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1541399260253,4cyclictest25658-21CPU19
1541399260253,4cyclictest25658-21CPU19
1307992380,3rtkit-daemon28229-21CPU24
1307992260,1rtkit-daemon0-21swapper/1021:58:2929
1307992260,1rtkit-daemon0-21swapper/1021:58:2829
1307992220,1rtkit-daemon0-21swapper/1623:05:5728
1307992220,1rtkit-daemon0-21swapper/1623:05:5728
15419992212,3cyclictest28231-21CPU25
15419992212,3cyclictest28231-21CPU25
1542399219213,3cyclictest0-21swapper/3420:00:0528
1542399219213,3cyclictest0-21swapper/3420:00:0428
15425992180,1cyclictest0-21swapper/3619:22:2630
1307992160,1rtkit-daemon0-21swapper/1021:25:022
1307992160,1rtkit-daemon0-21swapper/1021:25:022
1307992140,1rtkit-daemon0-21swapper/1019:48:573
1307992140,1rtkit-daemon0-21swapper/1019:48:573
1307992130,1rtkit-daemon0-21swapper/1321:43:473
1307992130,1rtkit-daemon0-21swapper/1321:43:473
15425992120,1cyclictest0-21swapper/3622:16:1430
15425992120,1cyclictest0-21swapper/3622:16:1330
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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