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2025-03-18 - 05:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Tue Mar 18, 2025 01:01:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3289299240214,3cyclictest15979-21CPU0
3289299240214,3cyclictest15979-21CPU0
3289299240214,3cyclictest15979-21CPU0
32937992251,3cyclictest0-21swapper/3822:30:1332
32937992251,3cyclictest0-21swapper/3822:30:1332
32893992201,4cyclictest3078-21CPU1
32893992201,4cyclictest3078-21CPU1
32893992201,4cyclictest3078-21CPU1
32937992161,2cyclictest0-21swapper/3822:40:2632
32937992161,2cyclictest0-21swapper/3822:40:2632
32896992152,209cyclictest27377-21NetworkChangeNo21:15:1923
32896992152,209cyclictest27377-21NetworkChangeNo21:15:1923
32896992152,209cyclictest27377-21NetworkChangeNo21:15:1923
32896992061,197cyclictest0-21swapper/323:20:1923
32896992061,197cyclictest0-21swapper/323:20:1823
32896992061,197cyclictest0-21swapper/323:20:1823
32937992051,3cyclictest0-21swapper/3822:35:4332
32937992051,3cyclictest0-21swapper/3822:35:4332
32937992040,2cyclictest0-21swapper/3819:27:3232
32937992040,2cyclictest0-21swapper/3819:27:3232
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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