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2021-06-20 - 03:33

Intel(R) Xeon(R) CPU E5-2650L v2 @ 1.70GHz, Linux 4.18.7-rt5 (Profile)

Latency plot of system in rack #6, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Up99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Thu May 27, 2021 02:54:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3424499301294,4cyclictest10476-21CPU3
3424499301294,4cyclictest10476-21CPU3
1697992850,6rtkit-daemon34897-21sshd00:07:3314
1697992850,6rtkit-daemon34897-21sshd00:07:3314
3427999278270,4cyclictest10465-21CPU31
3427999278270,4cyclictest10465-21CPU31
3424899268264,2cyclictest0-21swapper/1422:40:236
3424899268264,2cyclictest0-21swapper/1422:40:236
3426999253250,1cyclictest0-21swapper/3019:45:4324
3426999253250,1cyclictest0-21swapper/3019:45:4324
3428099252244,5cyclictest0-21swapper/3800:10:0032
3428099252244,5cyclictest0-21swapper/3800:10:0032
3427499252247,3cyclictest0-21swapper/3422:40:2728
3427499252247,3cyclictest0-21swapper/3422:40:2728
3428099248242,4cyclictest0-21swapper/3800:39:5532
3428099248242,4cyclictest0-21swapper/3800:39:5432
3427599248245,1cyclictest0-21swapper/3522:04:3929
3428099247241,4cyclictest0-21swapper/3821:14:0932
3428099247241,4cyclictest0-21swapper/3821:14:0932
3428099246240,4cyclictest0-21swapper/3822:50:0232
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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