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2026-01-20 - 07:34
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Tue Jan 20, 2026 01:00:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
928999249240,7cyclictest0-21swapper/800:00:1338
928999249240,7cyclictest0-21swapper/800:00:1338
928999249240,7cyclictest0-21swapper/800:00:1338
932299224214,5cyclictest2464-21CPU30
932299224214,5cyclictest2464-21CPU30
932299221215,4cyclictest0-21swapper/3621:35:2130
932299221215,4cyclictest0-21swapper/3621:35:2130
932299221215,4cyclictest0-21swapper/3621:35:2130
932299220213,5cyclictest0-21swapper/3623:49:2130
932299220213,5cyclictest0-21swapper/3623:49:2130
932299220211,6cyclictest0-21swapper/3622:48:1030
932299220211,6cyclictest0-21swapper/3622:48:1030
932299219211,6cyclictest0-21swapper/3621:28:5030
932299219211,6cyclictest0-21swapper/3621:28:5030
932299219210,4cyclictest2459-21CPU30
932299219210,4cyclictest2459-21CPU30
932299216210,4cyclictest0-21swapper/3600:35:4930
932299216210,4cyclictest0-21swapper/3600:35:4930
932299215207,6cyclictest0-21swapper/3623:40:1930
932299215207,6cyclictest0-21swapper/3623:40:1930
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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