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2025-02-18 - 23:40

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #9, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack9slot4s (updated Tue Feb 18, 2025 12:59:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
300449911221105,14cyclictest0-21swapper/107:25:121
300439911221091,18cyclictest0-21swapper/007:25:140
299442661614,32sleep10-21swapper/107:24:331
289742608558,36sleep00-21swapper/007:20:250
30043997758,3cyclictest0-21swapper/010:40:020
45692490,7sleep03004399cyclictest10:50:220
45692490,7sleep03004399cyclictest10:50:220
122322410,4sleep03004399cyclictest08:00:210
30043993923,6cyclictest3-21ksoftirqd/010:02:590
30043993822,6cyclictest3-21ksoftirqd/010:56:170
30043993822,6cyclictest3-21ksoftirqd/008:58:450
30043993822,5cyclictest3-21ksoftirqd/009:25:470
30043993722,5cyclictest3-21ksoftirqd/008:51:010
30043993721,5cyclictest3-21ksoftirqd/012:54:450
30043993720,6cyclictest3-21ksoftirqd/008:34:150
3004399364,16cyclictest11434-21hddtemp_smartct09:30:140
30043993621,5cyclictest3-21ksoftirqd/007:51:550
30043993620,6cyclictest3-21ksoftirqd/010:44:130
30043993620,6cyclictest3-21ksoftirqd/008:49:120
30043993620,6cyclictest3-21ksoftirqd/008:23:450
30043993619,6cyclictest3-21ksoftirqd/009:08:500
30043993520,5cyclictest3-21ksoftirqd/011:33:250
30043993519,6cyclictest3-21ksoftirqd/007:59:000
30043993511,12cyclictest30041-21cyclictest12:15:000
155132351,5sleep115554-21ntp_states09:40:311
3004499344,4cyclictest81rcu_preempt10:30:341
3004499341,5cyclictest81rcu_preempt07:40:291
30043993419,5cyclictest3-21ksoftirqd/009:00:530
30043993418,6cyclictest3-21ksoftirqd/012:05:340
30043993418,6cyclictest3-21ksoftirqd/011:43:590
30043993418,6cyclictest3-21ksoftirqd/007:48:210
30043993319,4cyclictest3-21ksoftirqd/008:26:430
30043993318,5cyclictest3-21ksoftirqd/010:26:070
30043993318,5cyclictest3-21ksoftirqd/010:23:350
30043993318,5cyclictest3-21ksoftirqd/010:08:400
30043993318,5cyclictest3-21ksoftirqd/007:33:130
30043993317,6cyclictest3-21ksoftirqd/012:30:320
30043993317,5cyclictest3-21ksoftirqd/012:49:470
30043993317,5cyclictest3-21ksoftirqd/007:43:210
254752331,28sleep125570-21hddtemp_smartct08:35:181
63142321,27sleep06204-21gdbus09:14:170
61302321,4sleep16180-21iostat10:55:211
3004499324,4cyclictest81rcu_preempt09:04:481
3004499321,9cyclictest17560-21/usr/sbin/munin08:15:301
30043993218,4cyclictest3-21ksoftirqd/009:57:470
30043993217,5cyclictest3-21ksoftirqd/011:55:520
30043993217,5cyclictest3-21ksoftirqd/011:02:260
30043993216,6cyclictest3-21ksoftirqd/011:18:570
30043993216,5cyclictest3-21ksoftirqd/011:25:470
3004399321,17cyclictest17394-21cron08:15:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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