You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-06-17 - 00:42

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Default latency plot of shadow in rack #a, slot #5

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
Special  All - All RT - Optimization - Ethernet - Thumbnails - Next
  TI
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackaslot5s.osadl.org (updated Tue Jun 16, 2026 12:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
811120,0rcu_preempt19-21ksoftirqd/111:56:101
811080,0rcu_preempt3-21ksoftirqd/012:02:120
811080,0rcu_preempt19-21ksoftirqd/111:47:501
811030,0rcu_preempt19-21ksoftirqd/109:25:321
811000,0rcu_preempt3-21ksoftirqd/010:00:160
811000,0rcu_preempt19-21ksoftirqd/109:54:321
81910,0rcu_preempt19-21ksoftirqd/111:25:081
81880,0rcu_preempt19-21ksoftirqd/110:03:371
81870,0rcu_preempt19-21ksoftirqd/111:42:581
81870,0rcu_preempt19-21ksoftirqd/110:07:451
81870,0rcu_preempt19-21ksoftirqd/110:07:451
81750,0rcu_preempt3-21ksoftirqd/009:20:320
81750,0rcu_preempt19-21ksoftirqd/109:12:451
9950740,0irq/345-484840041ktimersoftd/012:17:410
81740,0rcu_preempt3-21ksoftirqd/012:11:580
81740,0rcu_preempt3-21ksoftirqd/009:55:030
81740,0rcu_preempt3-21ksoftirqd/009:30:090
81730,0rcu_preempt3-21ksoftirqd/010:41:560
81730,0rcu_preempt3-21ksoftirqd/010:04:460
10050730,0irq/346-4848400111rcuc/009:51:470
81720,0rcu_preempt3-21ksoftirqd/011:28:350
9950710,0irq/345-48484000-21swapper/011:56:300
9950700,0irq/345-484840041ktimersoftd/011:36:460
81700,0rcu_preempt19-21ksoftirqd/112:22:461
81690,0rcu_preempt19-21ksoftirqd/112:06:381
435399692,0cyclictest0-21swapper/010:25:360
81680,0rcu_preempt26813-21if_eth109:22:490
81680,0rcu_preempt19-21ksoftirqd/112:12:021
9950670,0irq/345-484840041ktimersoftd/011:44:160
9950670,0irq/345-4848400111rcuc/012:36:590
9950670,0irq/345-4848400111rcuc/012:36:590
81670,0rcu_preempt3-21ksoftirqd/012:32:130
81670,0rcu_preempt19-21ksoftirqd/109:27:591
10050670,0irq/346-4848400111rcuc/010:32:270
81660,0rcu_preempt19-21ksoftirqd/110:30:071
81660,0rcu_preempt10335-21kworker/0:209:42:560
81640,0rcu_preempt851-21rngd10:48:320
81640,0rcu_preempt851-21rngd10:48:320
9950630,0irq/345-48484007787-1kworker/0:1H10:46:420
9950620,0irq/345-484840012714-1kworker/0:0H10:58:000
9950610,0irq/345-484840041ktimersoftd/011:08:520
9950610,0irq/345-48484000-21swapper/010:35:510
81610,0rcu_preempt19-21ksoftirqd/108:18:001
9950600,0irq/345-484840041ktimersoftd/007:29:060
81600,0rcu_preempt19-21ksoftirqd/109:51:491
156962600,0chrt10050irq/346-484840007:40:520
9950590,0irq/345-48484000-21swapper/011:23:510
9950590,0irq/345-48484000-21swapper/009:37:310
81580,0rcu_preempt3-21ksoftirqd/011:40:450
81580,0rcu_preempt3-21ksoftirqd/011:40:450
81580,0rcu_preempt19-21ksoftirqd/108:08:021
10050580,0irq/346-484840054-21kswapd009:32:460
81570,0rcu_preempt3-21ksoftirqd/008:37:590
141622570,0chrt10050irq/346-484840007:37:140
4350560,0irq/32-433000003-21ksoftirqd/008:02:470
81550,0rcu_preempt19-21ksoftirqd/109:58:111
10050550,0irq/346-48484009424-1kworker/0:0H08:59:200
10050550,0irq/346-484840054-21kswapd012:25:020
81540,0rcu_preempt3-21ksoftirqd/007:57:560
81540,0rcu_preempt3-21ksoftirqd/007:47:480
81540,0rcu_preempt3-21ksoftirqd/007:47:480
81540,0rcu_preempt3-21ksoftirqd/007:07:470
81540,0rcu_preempt20552-21ping08:22:400
10050540,0irq/346-484840054-21kswapd009:12:360
81530,0rcu_preempt3-21ksoftirqd/012:13:000
81530,0rcu_preempt3-21ksoftirqd/008:07:440
9950520,0irq/345-4848400171rcuc/111:30:401
81520,0rcu_preempt3-21ksoftirqd/011:22:300
81520,0rcu_preempt3-21ksoftirqd/010:54:550
81520,0rcu_preempt3-21ksoftirqd/009:07:300
10050520,0irq/346-484840054-21kswapd010:17:460
81510,0rcu_preempt7866-21ssh11:47:500
81510,0rcu_preempt3-21ksoftirqd/010:07:480
81510,0rcu_preempt3-21ksoftirqd/010:07:480
81500,0rcu_preempt3-21ksoftirqd/011:16:130
81500,0rcu_preempt3-21ksoftirqd/010:13:180
81500,0rcu_preempt3-21ksoftirqd/009:07:560
81500,0rcu_preempt3-21ksoftirqd/008:17:460
81500,0rcu_preempt19-21ksoftirqd/110:45:191
81500,0rcu_preempt19-21ksoftirqd/109:32:551
81490,0rcu_preempt3-21ksoftirqd/012:04:590
81490,0rcu_preempt3-21ksoftirqd/008:27:500
81480,0rcu_preempt19-21ksoftirqd/110:22:301
81470,0rcu_preempt31521-21ssh11:06:200
81470,0rcu_preempt19-21ksoftirqd/110:37:491
81470,0rcu_preempt19-21ksoftirqd/108:25:471
81470,0rcu_preempt19-21ksoftirqd/107:26:251
81460,0rcu_preempt7636-21ping07:22:420
81460,0rcu_preempt6134-21apt-get07:12:390
81460,0rcu_preempt3-21ksoftirqd/008:47:440
81460,0rcu_preempt3-21ksoftirqd/007:56:480
81460,0rcu_preempt3-21ksoftirqd/007:56:480
81460,0rcu_preempt3-21ksoftirqd/007:02:510
81460,0rcu_preempt19-21ksoftirqd/111:59:331
81460,0rcu_preempt19-21ksoftirqd/109:42:501
81460,0rcu_preempt19-21ksoftirqd/109:37:421
81460,0rcu_preempt19-21ksoftirqd/108:39:301
81460,0rcu_preempt19-21ksoftirqd/107:58:051
81450,0rcu_preempt3-21ksoftirqd/008:42:430
81450,0rcu_preempt3-21ksoftirqd/008:14:350
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional