You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-11-18 - 06:56

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Default latency plot of shadow in rack #a, slot #5

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
Special  All - All RT - Optimization - Ethernet - Thumbnails - Next
  TI
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackaslot5s.osadl.org (updated Tue Nov 18, 2025 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
81920,0rcu_preempt3-21ksoftirqd/023:54:150
81840,0rcu_preempt0-21swapper/122:57:321
81830,0rcu_preempt0-21swapper/122:15:311
81810,0rcu_preempt19-21ksoftirqd/122:30:031
81810,0rcu_preempt19-21ksoftirqd/122:30:031
10050810,0irq/346-4848400111rcuc/021:55:050
10050800,0irq/346-4848400111rcuc/021:22:280
18572770,0sleep010050irq/346-484840020:05:320
81760,0rcu_preempt19-21ksoftirqd/123:59:581
81760,0rcu_preempt19-21ksoftirqd/119:29:591
10050760,0irq/346-4848400111rcuc/022:53:350
35322750,0sleep010050irq/346-484840020:10:580
35322750,0sleep010050irq/346-484840020:10:580
81730,0rcu_preempt3-21ksoftirqd/000:04:500
81710,0rcu_preempt19-21ksoftirqd/123:40:071
81710,0rcu_preempt19-21ksoftirqd/121:42:371
81710,0rcu_preempt19-21ksoftirqd/119:24:391
81710,0rcu_preempt19-21ksoftirqd/100:39:141
81700,0rcu_preempt19-21ksoftirqd/123:20:351
81690,0rcu_preempt554-21kworker/1:021:32:251
81690,0rcu_preempt54-21kswapd022:26:171
81680,0rcu_preempt3-21ksoftirqd/022:45:210
81670,0rcu_preempt13025-21kworker/1:123:16:231
81670,0rcu_preempt0-21swapper/123:39:061
1501899671,0cyclictest13209-1kworker/0:4H23:36:330
81660,0rcu_preempt19-21ksoftirqd/123:29:181
81660,0rcu_preempt19-21ksoftirqd/122:41:261
81660,0rcu_preempt19-21ksoftirqd/122:41:261
81660,0rcu_preempt19-21ksoftirqd/122:06:561
1501899661,0cyclictest0-21swapper/022:57:080
81650,0rcu_preempt19-21ksoftirqd/123:51:251
1501899657,0cyclictest21199-1kworker/0:0H22:29:590
1501899657,0cyclictest21199-1kworker/0:0H22:29:590
1501899652,0cyclictest18373-21ssh21:44:490
81640,0rcu_preempt3-21ksoftirqd/022:23:270
81640,0rcu_preempt19-21ksoftirqd/123:30:461
81640,0rcu_preempt19-21ksoftirqd/123:30:461
81640,0rcu_preempt19-21ksoftirqd/123:12:551
81640,0rcu_preempt19-21ksoftirqd/123:12:551
81640,0rcu_preempt19-21ksoftirqd/121:35:421
81640,0rcu_preempt0-21swapper/100:27:381
1501899642,0cyclictest0-21swapper/021:41:300
15018996417,0cyclictest0-21swapper/023:45:070
1501899641,0cyclictest27955-1kworker/0:2H21:19:220
81630,0rcu_preempt3-21ksoftirqd/000:29:580
81630,0rcu_preempt19-21ksoftirqd/122:54:001
81630,0rcu_preempt19-21ksoftirqd/119:49:511
81630,0rcu_preempt19-21ksoftirqd/119:19:401
81630,0rcu_preempt15238-1kworker/1:3H00:23:461
81620,0rcu_preempt3-21ksoftirqd/022:36:480
81620,0rcu_preempt3-21ksoftirqd/022:36:480
206972620,0chrt9950irq/345-484840023:05:180
81610,0rcu_preempt19-21ksoftirqd/121:44:561
81610,0rcu_preempt0-21swapper/100:04:521
1501899614,0cyclictest2846-21sort22:04:590
81600,0rcu_preempt19-21ksoftirqd/123:47:051
81600,0rcu_preempt19-21ksoftirqd/122:09:571
81600,0rcu_preempt19-21ksoftirqd/122:02:501
81600,0rcu_preempt19-21ksoftirqd/121:24:541
81600,0rcu_preempt19-21ksoftirqd/120:31:301
81600,0rcu_preempt19-21ksoftirqd/100:33:461
1501899609,0cyclictest18294-21ping19:19:400
81590,0rcu_preempt19-21ksoftirqd/122:59:431
81590,0rcu_preempt19-21ksoftirqd/122:59:431
81590,0rcu_preempt19-21ksoftirqd/121:23:421
81590,0rcu_preempt19-21ksoftirqd/121:19:161
81590,0rcu_preempt19-21ksoftirqd/120:14:261
81590,0rcu_preempt19-21ksoftirqd/120:14:261
81590,0rcu_preempt19-21ksoftirqd/100:16:001
81590,0rcu_preempt0-21swapper/023:14:590
1501899598,0cyclictest26327-1kworker/0:3H23:55:080
15018995912,0cyclictest0-21swapper/019:25:090
81580,0rcu_preempt3-21ksoftirqd/000:34:530
1501899583,0cyclictest0-21swapper/000:20:170
1501899582,0cyclictest9950irq/345-484840023:39:390
1501899582,0cyclictest18294-21ping19:34:520
81570,0rcu_preempt19-21ksoftirqd/122:49:301
81570,0rcu_preempt19-21ksoftirqd/122:23:201
1501899571,0cyclictest31166-21ping20:15:120
10050570,0irq/346-4848400751-21rngd00:00:080
81560,0rcu_preempt3-21ksoftirqd/023:19:510
1501899569,0cyclictest0-21swapper/019:45:090
1501899562,0cyclictest0-21swapper/022:10:020
1501899561,0cyclictest18294-21ping19:19:380
81550,0rcu_preempt3-21ksoftirqd/000:25:010
81550,0rcu_preempt19-21ksoftirqd/119:59:381
81550,0rcu_preempt19-21ksoftirqd/119:45:011
81550,0rcu_preempt10050irq/346-484840019:40:050
1501899551,0cyclictest0-21swapper/021:37:220
1501899551,0cyclictest0-21swapper/021:14:030
10050550,0irq/346-4848400751-21rngd22:59:470
10050550,0irq/346-4848400751-21rngd22:59:470
10050550,0irq/346-48484000-21swapper/021:28:140
81540,0rcu_preempt3-21ksoftirqd/023:09:560
81540,0rcu_preempt3-21ksoftirqd/023:09:560
81540,0rcu_preempt3-21ksoftirqd/021:54:300
81540,0rcu_preempt3-21ksoftirqd/020:35:010
81540,0rcu_preempt19-21ksoftirqd/123:54:491
68732540,0sleep010050irq/346-484840020:21:300
10050540,0irq/346-4848400751-21rngd00:12:530
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional