You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-11-07 - 20:07

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Default latency plot of shadow in rack #a, slot #5

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
Special  All - All RT - Optimization - Ethernet - Thumbnails - Next
  TI
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackaslot5s.osadl.org (updated Fri Nov 07, 2025 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2846021310,0sleep010050irq/346-484840008:17:350
811080,0rcu_preempt19-21ksoftirqd/107:30:241
2697721040,0sleep010050irq/346-484840008:14:150
2697721040,0sleep010050irq/346-484840008:14:150
81930,0rcu_preempt19-21ksoftirqd/107:39:501
81930,0rcu_preempt19-21ksoftirqd/107:39:501
252142900,0sleep010050irq/346-484840008:07:490
285652790,0chrt9950irq/345-484840009:33:200
81770,0rcu_preempt19-21ksoftirqd/107:19:471
317042710,0sleep010050irq/346-484840008:27:100
222872680,0sleep010050irq/346-484840007:59:530
288402670,0sleep010050irq/346-484840008:19:570
81650,0rcu_preempt19-21ksoftirqd/109:50:201
56592640,0sleep19950irq/345-484840012:05:021
81620,0rcu_preempt3-21ksoftirqd/010:10:460
81610,0rcu_preempt3-21ksoftirqd/009:12:060
81600,0rcu_preempt19-21ksoftirqd/111:12:571
81590,0rcu_preempt19-21ksoftirqd/111:27:511
81580,0rcu_preempt19-21ksoftirqd/111:06:051
10050580,0irq/346-48484003-21ksoftirqd/011:01:290
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional