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2025-10-13 - 17:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackbslot1.osadl.org (updated Mon Oct 13, 2025 12:44:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
39319312212182,19sleep30-21swapper/307:09:463
39318872211169,32sleep10-21swapper/107:09:111
39317232203156,13sleep20-21swapper/207:07:082
39316762197173,14sleep00-21swapper/007:06:290
41038242690,1chrt4103804-21/usr/share/muni09:55:012
39542592600,1chrt3954223-21snmp_areswitch.07:30:042
3932112995651,4cyclictest3959250-21/usr/share/muni07:35:131
3932113995334,18cyclictest4093435-21CompositorTileW09:45:002
3932112995350,2cyclictest4072373-21kworker/u8:1+events_unbound09:35:011
3932111995346,5cyclictest4115371-21ntpq10:05:150
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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