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2025-08-21 - 21:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackbslot1.osadl.org (updated Thu Aug 21, 2025 12:44:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7715302212171,31sleep20-21swapper/207:09:062
7715092212161,41sleep10-21swapper/107:08:491
7714332208179,19sleep00-21swapper/007:07:510
7713892204176,18sleep30-21swapper/307:07:193
77181999870,55cyclictest994762-21/usr/share/muni10:45:020
77181999870,53cyclictest40658-21ThreadPoolForeg07:45:020
771832998379,2cyclictest871229-21apache_processe08:45:023
10644202650,1sleep20-21swapper/211:50:172
10116652540,1sleep30-21swapper/311:00:103
771828995135,11cyclictest906900-21latency_hist09:20:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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