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2025-11-28 - 07:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackbslot1.osadl.org (updated Thu Nov 27, 2025 12:45:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
38238152212183,19sleep30-21swapper/307:08:033
38238042209185,14sleep20-21swapper/207:07:542
38238832205181,14sleep00-21swapper/007:08:560
38238382202172,20sleep10-21swapper/107:08:211
38241339910245,55cyclictest3861557-21chrome07:45:023
41473142980,3sleep2361ktimers/212:20:102
3824130999590,3cyclictest3986424-21snmp_wlanswitch09:45:022
3824127999489,3cyclictest3125721-21chrome09:45:020
382412999714,66cyclictest4110046-21chrome11:45:021
3824129996456,6cyclictest3125725-21ThreadPoolForeg10:20:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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