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2025-06-29 - 01:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackbslot1.osadl.org (updated Sat Jun 28, 2025 12:44:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31456042216188,18sleep20-21swapper/207:07:112
31457712209186,14sleep00-21swapper/007:09:170
31455682204155,35sleep30-21swapper/307:06:433
31455282197173,14sleep10-21swapper/107:06:141
33593102750,2sleep01515609-21ThreadPoolForeg10:35:280
33759812720,0chrt3375976-21/usr/sbin/munin10:55:000
3146039997168,2cyclictest3193052-21kworker/u8:1+flush-179:007:55:193
3146039997166,3cyclictest3365469-21latency_hist10:45:013
3146031996354,5cyclictest3365773-21chrome10:45:011
3146034996259,2cyclictest3395874-21kworker/u8:0+flush-179:011:30:202
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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