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2025-11-29 - 04:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackbslot1.osadl.org (updated Fri Nov 28, 2025 12:44:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11194692213189,14sleep30-21swapper/307:08:093
11194512207183,14sleep00-21swapper/007:07:530
11195752196172,14sleep10-21swapper/107:09:301
11194272190166,14sleep20-21swapper/207:07:362
121361821360,2sleep31213614-21snmp_wlanpowerc08:40:003
1119798996460,3cyclictest1296084-21kworker/u8:0+events_unbound10:20:312
1119798996360,2cyclictest1156405-21kworker/u8:2+events_unbound08:00:102
1119798996359,3cyclictest1383514-21kworker/u8:0+events_unbound11:50:102
1119795996257,3cyclictest1281145-21snmp_wlanpowerc09:45:021
1119798996156,3cyclictest1275628-21kworker/u8:2+events_unbound10:19:062
1119798996057,2cyclictest1265410-21kworker/u8:0+events_unbound09:45:402
1119798996034,22cyclictest1404340-21kworker/u8:1+flush-179:012:25:052
1119798995956,2cyclictest1450416-21kworker/u8:2+events_unbound12:30:312
1119798995956,2cyclictest1341787-21kworker/u8:0+events_unbound11:05:342
1119794995849,7cyclictest247560-21ThreadPoolForeg10:20:080
111979499581,55cyclictest247557-21chrome10:05:010
1119798995742,13cyclictest1275628-21kworker/u8:2+flush-179:010:09:092
1119798995652,3cyclictest1238178-21kworker/u8:1+flush-179:009:10:072
1119798995651,4cyclictest1416580-21kworker/u8:3+flush-179:011:55:232
1119798995552,2cyclictest1341787-21kworker/u8:0+events_unbound10:48:232
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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