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2026-01-23 - 15:19
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #c, slot #7

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackcslot7s.osadl.org (updated Fri Jan 23, 2026 12:45:18)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
308176399510503,4cyclictest3187135-21turbostat12:25:013
308176399481456,22cyclictest3188901-21turbostat12:30:013
308176399474445,6cyclictest3176683-21turbostat11:55:003
308176099462453,6cyclictest3187135-21turbostat12:29:562
308176399459450,6cyclictest3116951-21turbostat08:55:193
308176399457449,4cyclictest3191268-21turbostat12:40:013
308176399457448,6cyclictest3129668-21turbostat09:25:253
308176399451429,19cyclictest3153849-21turbostat10:45:193
308176399450442,5cyclictest3169466-21turbostat11:35:003
308176399449423,23cyclictest3176683-21turbostat11:59:563
308176399448441,4cyclictest3153849-21turbostat10:40:253
308176399445437,5cyclictest3185379-21turbostat12:20:013
308176399444437,4cyclictest3125914-21turbostat09:20:193
308176399443436,4cyclictest3164215-21turbostat11:24:563
308176399443435,5cyclictest3149115-21turbostat10:25:203
308176099438431,4cyclictest3158620-21turbostat11:05:202
308176399437430,4cyclictest3164215-21turbostat11:20:013
308175599435428,4cyclictest3150843-21turbostat10:30:201
308175599435428,4cyclictest3150843-21turbostat10:30:191
308176399432425,4cyclictest3171191-21turbostat11:44:563
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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