You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-03-10 - 00:07

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Default latency plot of shadow in rack #c, slot #7

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
Special  All - All RT - Optimization - Ethernet - Thumbnails - Next
  
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackcslot7s.osadl.org (updated Mon Mar 09, 2026 12:44:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
356192699465438,24cyclictest3665990-21turbostat12:00:003
356192699463439,8cyclictest3576554-21turbostat07:54:553
356192699462455,4cyclictest3669504-21turbostat12:14:563
356192699462455,4cyclictest3620795-21turbostat09:59:563
356192699462440,19cyclictest3667768-21turbostat12:04:593
356192699459452,4cyclictest3574832-21turbostat07:49:563
356192499456448,5cyclictest3624559-21turbostat10:09:542
356192699454447,4cyclictest3646896-21turbostat11:05:003
356192699453445,5cyclictest3619067-21turbostat09:50:003
356192499453435,15cyclictest3672964-21turbostat12:24:562
356192699452445,4cyclictest3606649-21turbostat09:15:003
356192699452442,7cyclictest3628329-21turbostat10:19:553
356192699451443,5cyclictest3653874-21turbostat11:25:003
356192699450442,5cyclictest3674696-21turbostat12:25:003
356192699449442,4cyclictest3565820-21turbostat07:20:013
356192699446438,5cyclictest3672964-21turbostat12:20:013
356192699444437,4cyclictest3596254-21turbostat08:49:553
356192699443436,4cyclictest3567538-21turbostat07:29:543
356192699443435,5cyclictest3631788-21turbostat10:29:563
356192699440432,5cyclictest3644853-21turbostat11:00:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional