You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-03-16 - 00:40

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Default latency plot of shadow in rack #c, slot #7

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
Special  All - All RT - Optimization - Ethernet - Thumbnails - Next
  
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackcslot7s.osadl.org (updated Sun Mar 15, 2026 12:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
280365399525498,24cyclictest2854931-21turbostat09:39:551
280364999470448,19cyclictest2812732-21turbostat07:39:550
280365999469448,18cyclictest2845977-21turbostat09:14:553
280365999463455,5cyclictest2919998-21turbostat12:40:003
280365999463454,6cyclictest2914495-21turbostat12:25:003
280365999463440,20cyclictest2856953-21turbostat09:40:003
280365399460453,4cyclictest2851467-21turbostat09:29:551
280365999459435,21cyclictest2823170-21turbostat08:05:003
280365999458448,7cyclictest2883230-21turbostat10:55:003
280364999458450,5cyclictest2842515-21turbostat09:04:550
280365999457450,4cyclictest2907571-21turbostat12:05:003
280365599457448,6cyclictest2816255-21turbostat07:49:552
280365999455448,4cyclictest2853200-21turbostat09:30:003
280365999455447,5cyclictest2828366-21turbostat08:20:003
280365999453446,4cyclictest2863888-21turbostat10:00:003
280365999450443,4cyclictest2837320-21turbostat08:45:003
280365999450443,4cyclictest2824901-21turbostat08:10:003
280365999449441,5cyclictest2891876-21turbostat11:24:543
280365999448441,4cyclictest2886693-21turbostat11:05:003
280365999446439,4cyclictest2883230-21turbostat10:59:553
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional