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2026-02-22 - 15:59
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #c, slot #7

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackcslot7s.osadl.org (updated Sun Feb 22, 2026 12:44:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
341710599480457,20cyclictest3505338-21turbostat11:20:003
341710599462453,6cyclictest3477323-21turbostat10:04:563
341710599462442,17cyclictest3433140-21turbostat07:55:003
341710599460437,20cyclictest3445871-21turbostat08:29:593
341710599458450,5cyclictest3498097-21turbostat11:04:543
341710599457434,20cyclictest3513988-21turbostat11:45:003
341710599456449,4cyclictest3465212-21turbostat09:29:543
341709999456449,4cyclictest3479056-21turbostat10:09:541
341710599455432,20cyclictest3420963-21turbostat07:24:553
341710599454447,4cyclictest3436614-21turbostat08:09:553
341710599454445,6cyclictest3451058-21turbostat08:45:013
341710599452445,4cyclictest3420963-21turbostat07:20:003
341710599452445,4cyclictest3420963-21turbostat07:20:003
341710599451444,4cyclictest3496376-21turbostat10:59:553
341709599451427,21cyclictest3519174-21turbostat12:04:550
341710599450443,4cyclictest3431417-21turbostat07:50:003
341710599450442,5cyclictest3501571-21turbostat11:10:003
341710599450429,18cyclictest3451058-21turbostat08:49:563
341710599448441,4cyclictest3463476-21turbostat09:24:543
341710599444437,4cyclictest3422704-21turbostat07:29:553
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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