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2026-03-01 - 10:15
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #c, slot #7

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot7s.osadl.org (updated Sun Mar 01, 2026 00:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
292865599522500,19cyclictest2934737-21turbostat19:39:550
292866699507500,4cyclictest2932071-21turbostat19:29:563
292866699506497,6cyclictest2950698-21turbostat20:55:003
292866699491449,19cyclictest2953359-21turbostat21:05:003
292866699491449,19cyclictest2953359-21turbostat21:05:003
292866699482453,25cyclictest3025194-21turbostat00:34:563
292866699472429,23cyclictest2953994-21turbostat21:14:553
292866699466439,23cyclictest3025194-21turbostat00:30:013
292866699464457,4cyclictest2977402-21turbostat22:15:003
292866699464457,4cyclictest2959491-21turbostat21:29:553
292866699464457,4cyclictest2937734-21turbostat19:54:563
292866699464456,5cyclictest2980865-21turbostat22:29:553
292866699463456,4cyclictest2986059-21turbostat22:39:593
292866699463456,4cyclictest2986059-21turbostat22:39:593
292866199463455,5cyclictest2971905-21turbostat22:04:552
292866699462455,4cyclictest2973953-21turbostat22:05:013
292865599461438,20cyclictest3017967-21turbostat00:14:560
292865599461438,20cyclictest3017967-21turbostat00:14:550
292866699459451,5cyclictest3007561-21turbostat23:40:003
292865799459450,6cyclictest2935377-21turbostat19:44:551
292866699457450,4cyclictest2962957-21turbostat21:35:003
292865799454447,4cyclictest2929221-21turbostat19:19:551
292866699452443,6cyclictest2991337-21turbostat22:55:013
292866199452443,6cyclictest3011025-21turbostat23:54:562
292866699449441,5cyclictest3026927-21turbostat00:39:563
292866699445438,4cyclictest2931441-21turbostat19:20:003
292866699445437,5cyclictest2950067-21turbostat20:50:003
292866699444436,5cyclictest2936003-21turbostat19:49:553
292866199444436,5cyclictest2940727-21turbostat20:09:552
292866699442435,4cyclictest3009288-21turbostat23:49:563
292866699442435,4cyclictest2979132-21turbostat22:19:593
292866699442434,5cyclictest2938360-21turbostat19:59:553
292866699441434,4cyclictest2944029-21turbostat20:24:553
292866699437430,4cyclictest2953359-21turbostat21:09:553
292866699437407,26cyclictest3014488-21turbostat23:59:593
292866699437407,26cyclictest3014488-21turbostat23:59:593
292866699436429,4cyclictest3016239-21turbostat00:09:563
292866699436408,25cyclictest2970176-21turbostat21:54:593
292866699433426,4cyclictest3000635-21turbostat23:24:563
292866199433425,5cyclictest3012744-21turbostat23:59:552
292866199433425,5cyclictest3012744-21turbostat23:59:552
292866199432423,6cyclictest2928528-21turbostat19:14:552
292866699430405,22cyclictest2993368-21turbostat23:00:013
292866699425418,4cyclictest2987835-21turbostat22:44:593
292866699422414,5cyclictest2979132-21turbostat22:24:553
292865799422415,4cyclictest2950067-21turbostat20:54:551
292866699418411,4cyclictest2950698-21turbostat20:59:553
292866699415408,4cyclictest2947028-21turbostat20:39:563
292866699415408,4cyclictest2947028-21turbostat20:39:553
292866699414386,25cyclictest2929221-21turbostat19:15:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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