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2026-02-08 - 09:13
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #c, slot #7

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot7s.osadl.org (updated Sun Feb 08, 2026 00:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
351939499507498,6cyclictest3620674-21turbostat23:55:013
351939499494447,31cyclictest3555645-21turbostat20:50:003
351939499467444,20cyclictest3602705-21turbostat23:09:553
351939499464457,4cyclictest3569492-21turbostat21:30:003
351939499462455,4cyclictest3627620-21turbostat00:19:553
351939499458451,4cyclictest3567757-21turbostat21:25:003
351939499457434,20cyclictest3541440-21turbostat20:09:593
351937399456433,20cyclictest3564294-21turbostat21:19:560
351937399456433,20cyclictest3564294-21turbostat21:19:560
351938199454446,5cyclictest3587139-21turbostat22:24:552
351937399454430,20cyclictest3622411-21turbostat00:04:550
351937399454430,20cyclictest3622411-21turbostat00:04:550
351939499453430,20cyclictest3534529-21turbostat19:54:553
351938199451442,6cyclictest3525572-21turbostat19:29:552
351939499450443,4cyclictest3631082-21turbostat00:25:003
351939499450442,5cyclictest3620674-21turbostat23:59:553
351939499450434,13cyclictest3527307-21turbostat19:30:003
351939499449426,19cyclictest3592329-21turbostat22:39:553
351939499447439,5cyclictest3592329-21turbostat22:35:003
351939499446433,10cyclictest3574720-21turbostat21:45:003
351939499443434,6cyclictest3599252-21turbostat22:59:563
351937899442433,6cyclictest3537992-21turbostat20:04:551
351937899442433,6cyclictest3537992-21turbostat20:04:551
351937899442420,19cyclictest3551883-21turbostat20:44:561
351939499441434,4cyclictest3559107-21turbostat21:00:013
351939499441430,8cyclictest3530754-21turbostat19:44:553
351939499440432,5cyclictest3625892-21turbostat00:14:563
351939499439432,4cyclictest3585413-21turbostat22:19:553
351938199438429,6cyclictest3541440-21turbostat20:14:542
351939499437430,4cyclictest3581953-21turbostat22:05:003
351939499437417,17cyclictest3551883-21turbostat20:40:003
351939499436428,5cyclictest3631082-21turbostat00:29:553
351939499436428,5cyclictest3631082-21turbostat00:29:553
351939499431424,4cyclictest3611980-21turbostat23:34:553
351939499431424,4cyclictest3559107-21turbostat21:04:553
351939499431422,6cyclictest3624163-21turbostat00:09:553
351939499431410,18cyclictest3523790-21turbostat19:24:543
351939499430423,4cyclictest3588877-21turbostat22:29:563
351938199429422,4cyclictest3539712-21turbostat20:09:552
351939499428420,5cyclictest3617218-21turbostat23:49:553
351939499427418,6cyclictest3576755-21turbostat21:54:553
351939499423416,4cyclictest3583672-21turbostat22:14:543
351939499422413,6cyclictest3606480-21turbostat23:19:553
351939499422413,6cyclictest3594062-21turbostat22:44:553
351939499421412,6cyclictest3543182-21turbostat20:15:003
351939499420412,5cyclictest3544909-21turbostat20:20:003
351939499417410,4cyclictest3537992-21turbostat20:00:003
351939499416394,19cyclictest3521256-21turbostat19:19:553
351937399416409,4cyclictest3608207-21turbostat23:24:560
351939499414407,4cyclictest3571228-21turbostat21:35:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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