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2026-02-15 - 09:36
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #c, slot #7

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot7s.osadl.org (updated Sun Feb 15, 2026 00:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
332042199507500,4cyclictest3417468-21turbostat23:45:013
332042199479456,20cyclictest3354249-21turbostat20:49:543
332042199470446,8cyclictest3373598-21turbostat21:40:003
332042199469427,29cyclictest3350792-21turbostat20:39:553
332042199465454,8cyclictest3412269-21turbostat23:34:553
332042199464457,4cyclictest3417468-21turbostat23:49:553
332042199463456,4cyclictest3405346-21turbostat23:14:553
332042199462455,4cyclictest3430527-21turbostat00:24:543
332042199461453,5cyclictest3421226-21turbostat23:54:593
332042199461453,5cyclictest3368408-21turbostat21:29:563
332042199461453,5cyclictest3368408-21turbostat21:29:563
332041499461454,4cyclictest3415739-21turbostat23:44:552
332042199460453,4cyclictest3347321-21turbostat20:29:543
332042199459450,6cyclictest3335215-21turbostat19:54:563
332042199459450,6cyclictest3335215-21turbostat19:54:563
332042199458450,5cyclictest3391498-21turbostat22:30:013
332041499457448,6cyclictest3338675-21turbostat20:04:552
332042199455448,4cyclictest3378784-21turbostat21:55:003
332042199455448,4cyclictest3373598-21turbostat21:44:543
332042199455448,4cyclictest3363200-21turbostat21:14:553
332042199454436,15cyclictest3403612-21turbostat23:09:553
332042199452445,4cyclictest3401892-21turbostat23:00:003
332042199451444,4cyclictest3361468-21turbostat21:05:013
332041499450442,5cyclictest3426748-21turbostat00:14:562
332042199449442,4cyclictest3408807-21turbostat23:24:553
332041499449442,4cyclictest3329720-21turbostat19:39:552
332041499448441,4cyclictest3366672-21turbostat21:24:552
332042199446435,8cyclictest3434076-21turbostat00:30:013
332042199445438,4cyclictest3422968-21turbostat23:59:593
332042199444436,5cyclictest3387733-21turbostat22:20:003
332042199441434,4cyclictest3398425-21turbostat22:50:003
332041499439432,4cyclictest3324528-21turbostat19:24:552
332042199438430,5cyclictest3350792-21turbostat20:35:003
332041499438431,4cyclictest3377043-21turbostat21:54:552
332041499438431,4cyclictest3370130-21turbostat21:34:552
332042199437429,5cyclictest3398425-21turbostat22:54:553
332041499437429,5cyclictest3327991-21turbostat19:34:552
332042199436427,6cyclictest3338675-21turbostat20:00:003
332042199435428,4cyclictest3383978-21turbostat22:10:003
332042199435428,4cyclictest3380516-21turbostat22:00:003
332042199433424,6cyclictest3340402-21turbostat20:09:543
332042199431423,5cyclictest3422968-21turbostat00:04:553
332042199431423,5cyclictest3422968-21turbostat00:04:553
332041499431424,4cyclictest3333482-21turbostat19:49:552
332042199430422,5cyclictest3389778-21turbostat22:25:003
332041499423415,5cyclictest3371864-21turbostat21:39:552
332042199422406,13cyclictest3415739-21turbostat23:40:003
332042199420412,5cyclictest3345597-21turbostat20:20:003
332042199420412,5cyclictest3345597-21turbostat20:20:003
332042199420411,6cyclictest3335215-21turbostat19:50:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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