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2026-01-25 - 05:38
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #c, slot #7

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot7s.osadl.org (updated Sun Jan 25, 2026 00:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
392021999507500,4cyclictest3962518-21turbostat21:14:541
392022799505495,6cyclictest4035928-21turbostat00:40:013
392021599485445,33cyclictest3986751-21turbostat22:24:560
392021999475441,20cyclictest3955299-21turbostat20:54:541
392022799472453,16cyclictest3925841-21turbostat19:25:003
392021999467430,23cyclictest3950104-21turbostat20:39:551
392021599466422,25cyclictest3965993-21turbostat21:24:550
392022399464457,4cyclictest3997186-21turbostat22:54:542
392022799462453,6cyclictest3932770-21turbostat19:44:593
392022799460452,5cyclictest4018563-21turbostat23:50:003
392022799460452,5cyclictest4011635-21turbostat23:34:553
392021999460451,6cyclictest3924113-21turbostat19:24:541
392022799459452,4cyclictest3957037-21turbostat20:55:013
392022399459450,6cyclictest3920110-21turbostat19:14:552
392022399459450,6cyclictest3920110-21turbostat19:14:552
392022799458451,4cyclictest4006143-21turbostat23:14:593
392021599458450,5cyclictest3964254-21turbostat21:19:560
392022799457450,4cyclictest4009607-21turbostat23:29:563
392022799455448,4cyclictest4032472-21turbostat00:30:003
392022799455446,6cyclictest3931037-21turbostat19:40:013
392022799455446,6cyclictest3931037-21turbostat19:40:003
392022799454446,5cyclictest3995461-21turbostat22:45:003
392021999454447,4cyclictest4004417-21turbostat23:14:561
392022399453446,4cyclictest4007872-21turbostat23:24:552
392021999452445,4cyclictest3941455-21turbostat20:14:551
392022799449442,4cyclictest3976367-21turbostat21:50:003
392021599449442,4cyclictest3974642-21turbostat21:49:550
392022799448429,16cyclictest3969437-21turbostat21:30:003
392021599444434,7cyclictest3931037-21turbostat19:44:550
392022799442433,6cyclictest3934538-21turbostat19:50:003
392022799440433,4cyclictest4007872-21turbostat23:20:003
392022799440433,4cyclictest3960796-21turbostat21:05:003
392022799435426,6cyclictest3983289-21turbostat22:10:003
392021999435428,4cyclictest4022024-21turbostat00:04:541
392021599435428,4cyclictest3993724-21turbostat22:44:550
392021599435428,4cyclictest3983289-21turbostat22:14:550
392022799434426,5cyclictest3998915-21turbostat22:55:013
392021599433426,4cyclictest3934538-21turbostat19:54:550
392022799430421,5cyclictest4028964-21turbostat00:24:543
392022399430421,6cyclictest4016826-21turbostat23:49:552
392022399427417,7cyclictest4027229-21turbostat00:19:552
392022399427417,7cyclictest4027229-21turbostat00:19:552
392022799426417,6cyclictest4023777-21turbostat00:05:003
392021999424417,4cyclictest3967715-21turbostat21:29:551
392021999424417,4cyclictest3946652-21turbostat20:29:541
392021599423415,5cyclictest4032472-21turbostat00:34:550
392022399422415,4cyclictest3991998-21turbostat22:39:562
392022799420413,4cyclictest3993724-21turbostat22:40:003
392022799419412,4cyclictest3946652-21turbostat20:25:003
392022799419412,4cyclictest3946652-21turbostat20:24:593
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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