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2026-02-01 - 06:31
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #c, slot #7

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot7s.osadl.org (updated Sun Feb 01, 2026 00:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
372404799522502,16cyclictest3834148-21turbostat00:29:563
372404799509502,4cyclictest3826578-21turbostat00:04:563
372404799464457,4cyclictest3828960-21turbostat00:10:003
372404799464457,4cyclictest3780888-21turbostat21:54:553
372404199464456,5cyclictest3740431-21turbostat19:59:551
372404799463456,4cyclictest3784352-21turbostat22:04:563
372404799463456,4cyclictest3784352-21turbostat22:04:563
372404799463456,4cyclictest3733202-21turbostat19:39:563
372404799460453,4cyclictest3789539-21turbostat22:19:553
372404799460453,4cyclictest3784352-21turbostat22:00:003
372404799459451,5cyclictest3760082-21turbostat20:54:563
372404799458450,4cyclictest3800231-21turbostat22:44:593
372404799458449,6cyclictest3808918-21turbostat23:09:593
372404799458437,18cyclictest3742142-21turbostat20:04:563
372404199458449,6cyclictest3828960-21turbostat00:14:551
372404799453446,4cyclictest3747656-21turbostat20:14:593
372404799451444,4cyclictest3787809-21turbostat22:10:003
372404799451443,5cyclictest3775659-21turbostat21:35:003
372404799451440,7cyclictest3742142-21turbostat20:00:013
372404799447440,4cyclictest3798503-21turbostat22:39:593
372404799446439,4cyclictest3793308-21turbostat22:25:003
372403799446439,4cyclictest3837617-21turbostat00:39:540
372404499445436,6cyclictest3747656-21turbostat20:19:542
372404499441434,4cyclictest3807192-21turbostat23:09:552
372404499440432,4cyclictest3779105-21turbostat21:49:552
372404799439418,18cyclictest3777386-21turbostat21:40:013
372404799434427,4cyclictest3793308-21turbostat22:29:563
372404799434427,4cyclictest3793308-21turbostat22:29:563
372404499434427,4cyclictest3796774-21turbostat22:39:552
372404799431423,5cyclictest3743882-21turbostat20:09:553
372404799429407,19cyclictest3814156-21turbostat23:29:543
372404799428421,4cyclictest3830694-21turbostat00:19:553
372404799427420,4cyclictest3729686-21turbostat19:29:553
372404799426419,4cyclictest3734936-21turbostat19:44:553
372404499426417,5cyclictest3808918-21turbostat23:14:542
372404799425418,4cyclictest3821083-21turbostat23:49:543
372404799424417,4cyclictest3815891-21turbostat23:34:553
372404799424417,4cyclictest3768728-21turbostat21:19:563
372404799424417,4cyclictest3768728-21turbostat21:15:013
372404799423414,6cyclictest3725727-21turbostat19:15:013
372404499423416,4cyclictest3745914-21turbostat20:14:552
372404499422413,6cyclictest3777386-21turbostat21:44:552
372404799421414,4cyclictest3835887-21turbostat00:34:563
372404799421410,7cyclictest3824843-21turbostat23:55:003
372404499420412,5cyclictest3723899-21turbostat19:14:552
372404799417410,4cyclictest3751414-21turbostat20:25:013
372404799413405,5cyclictest3772194-21turbostat21:25:003
372404199413406,4cyclictest3770460-21turbostat21:24:541
372404799412404,5cyclictest3839345-21turbostat00:39:593
372404499408401,4cyclictest3828324-21turbostat00:09:562
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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