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2026-02-04 - 08:20
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #c, slot #7

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot7s.osadl.org (updated Wed Feb 04, 2026 00:44:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
123641699502495,4cyclictest1287396-21turbostat21:39:550
123641699502495,4cyclictest1287396-21turbostat21:39:550
123643199482456,23cyclictest1291156-21turbostat21:45:003
123643199482456,23cyclictest1291156-21turbostat21:45:003
123643199464457,4cyclictest1308768-21turbostat22:35:003
123643199464434,27cyclictest1342027-21turbostat00:10:003
123642999464457,4cyclictest1326115-21turbostat23:29:552
123643199463451,9cyclictest1270036-21turbostat20:49:553
123643199462453,6cyclictest1317420-21turbostat23:00:003
123643199462428,21cyclictest1285662-21turbostat21:34:553
123643199461453,5cyclictest1289129-21turbostat21:40:003
123643199461453,5cyclictest1289129-21turbostat21:40:003
123642999461454,4cyclictest1342027-21turbostat00:14:552
123642499459440,16cyclictest1345488-21turbostat00:24:551
123643199458451,4cyclictest1338551-21turbostat00:00:003
123643199458451,4cyclictest1324392-21turbostat23:24:553
123642999458451,4cyclictest1312225-21turbostat22:49:542
123642499458451,4cyclictest1317420-21turbostat23:04:551
123642999457450,4cyclictest1315683-21turbostat22:59:552
123643199455448,4cyclictest1250984-21turbostat19:54:543
123643199455447,5cyclictest1264839-21turbostat20:30:003
123643199454445,6cyclictest1312225-21turbostat22:45:003
123643199453446,4cyclictest1301849-21turbostat22:15:003
123642999451442,6cyclictest1266577-21turbostat20:39:552
123643199449442,4cyclictest1320876-21turbostat23:10:003
123641699449442,4cyclictest1283933-21turbostat21:29:550
123643199448441,4cyclictest1327863-21turbostat23:30:003
123643199448441,4cyclictest1242034-21turbostat19:29:553
123643199443436,4cyclictest1268303-21turbostat20:40:003
123643199443435,5cyclictest1240305-21turbostat19:20:003
123642999443420,20cyclictest1236294-21turbostat19:14:552
123643199441433,5cyclictest1296651-21turbostat22:00:003
123641699441434,4cyclictest1347218-21turbostat00:29:560
123643199439432,4cyclictest1266577-21turbostat20:35:003
123643199439432,4cyclictest1266577-21turbostat20:35:003
123643199439411,25cyclictest1277010-21turbostat21:05:003
123642999439432,4cyclictest1303578-21turbostat22:24:552
123482324390,6sleep342-21ksoftirqd/319:05:103
123643199437430,4cyclictest1249255-21turbostat19:45:003
123642999434426,5cyclictest1240305-21turbostat19:24:552
123642999434426,5cyclictest1240305-21turbostat19:24:552
123642499434427,4cyclictest1334783-21turbostat23:54:551
123642999431423,5cyclictest1271767-21turbostat20:54:552
123642999431423,5cyclictest1271767-21turbostat20:54:552
123643199429421,4cyclictest1292889-21turbostat21:50:003
123643199427420,4cyclictest1270036-21turbostat20:45:003
123643199425418,4cyclictest1313956-21turbostat22:50:003
123643199425417,5cyclictest1347218-21turbostat00:25:003
123643199423416,4cyclictest1261382-21turbostat20:20:003
123642999423416,4cyclictest1247227-21turbostat19:44:552
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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