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2024-05-25 - 16:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot6.osadl.org (updated Sat May 25, 2024 00:46:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
90339923750,3sleep30-21swapper/319:09:233
8994862135117,3sleep60-21swapper/619:06:146
9018792126107,17sleep10-21swapper/119:08:181
101426221020,0sleep20-21swapper/221:40:292
90193029185,4sleep20-21swapper/219:08:192
904408998815,39cyclictest0-21swapper/000:38:560
89857828866,19sleep50-21swapper/519:05:325
904408998715,39cyclictest0-21swapper/021:43:570
904467998617,37cyclictest0-21swapper/722:53:577
904408998616,37cyclictest0-21swapper/020:18:570
904467998415,38cyclictest0-21swapper/720:53:577
904415998416,36cyclictest0-21swapper/122:38:571
904415998315,35cyclictest0-21swapper/100:03:571
11261562820,0sleep70-21swapper/723:15:187
11100662820,1sleep549-21ksoftirqd/523:01:135
90349928161,18sleep70-21swapper/719:09:287
904467998014,36cyclictest0-21swapper/719:18:577
11937252760,0sleep30-21swapper/300:12:013
90082327543,19sleep40-21swapper/419:07:404
10224562750,1sleep11022454-21sh21:48:211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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