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2024-07-27 - 07:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot6.osadl.org (updated Sat Jul 27, 2024 00:46:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
367356329257,12sleep70-21swapper/719:07:057
367356329257,12sleep70-21swapper/719:07:047
367349328956,11sleep30-21swapper/319:06:043
367349328956,11sleep30-21swapper/319:06:043
37719702850,0sleep20-21swapper/221:32:462
3673991998417,37cyclictest0-21swapper/422:15:134
38316952830,0sleep20-21swapper/222:21:392
367236728354,23sleep40-21swapper/419:05:174
367236728354,23sleep40-21swapper/419:05:164
3674008998216,36cyclictest0-21swapper/600:00:146
367348128259,11sleep00-21swapper/019:05:530
367348128259,11sleep00-21swapper/019:05:530
3673991998115,36cyclictest0-21swapper/420:10:144
3673991998115,35cyclictest0-21swapper/419:45:144
37825502780,0sleep00-21swapper/021:40:370
367360827861,12sleep50-21swapper/519:07:435
367360827861,12sleep50-21swapper/519:07:425
367345427861,11sleep20-21swapper/219:05:312
367345427861,11sleep20-21swapper/219:05:302
38554422770,0sleep30-21swapper/322:41:023
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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