You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2024-07-27 - 03:15
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackcslot8.osadl.org (updated Fri Jul 26, 2024 12:48:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2279912560,243ptp4l0-21swapper/107:10:011
286849917331,99cyclictest0-21swapper/411:10:1626
287269917031,117cyclictest0-21swapper/1309:55:485
287269917031,117cyclictest0-21swapper/1309:55:485
287269916932,83cyclictest0-21swapper/1310:15:345
287269916932,83cyclictest0-21swapper/1310:15:345
287269916633,75cyclictest0-21swapper/1311:30:235
287839916519,82cyclictest151rcu_preempt11:37:1917
287269916230,71cyclictest0-21swapper/1311:46:255
286849915931,76cyclictest0-21swapper/410:29:3626
286849915694,61cyclictest40-21ksoftirqd/410:17:2126
286849915694,61cyclictest40-21ksoftirqd/410:17:2126
286849915340,73cyclictest0-21swapper/412:29:2226
288129914838,68cyclictest0-21swapper/2807:35:1921
287839914856,47cyclictest0-21swapper/2412:22:4517
288129914729,89cyclictest0-21swapper/2811:35:0921
288129914628,87cyclictest0-21swapper/2810:35:2621
288129914557,87cyclictest151rcu_preempt12:10:0021
286849914420,91cyclictest0-21swapper/411:23:3826
28835991430,86cyclictest0-21swapper/3111:00:1425
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional