You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-07-07 - 01:50
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackcslot8.osadl.org (updated Sun Jul 06, 2025 12:49:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
329891279270,7phc2sys0-21swapper/207:08:5512
2482911900,182ptp4l0-21swapper/107:06:271
116329917479,27cyclictest137-21ksoftirqd/2009:45:1713
116229916428,82cyclictest0-21swapper/1811:13:2310
116229916428,82cyclictest0-21swapper/1811:13:2310
116499916349,74cyclictest0-21swapper/2207:25:1615
116499916132,76cyclictest0-21swapper/2211:22:0115
116499916132,76cyclictest0-21swapper/2211:22:0115
116229916132,81cyclictest0-21swapper/1810:02:0310
115749916197,56cyclictest0-21swapper/911:58:0831
116499916032,72cyclictest0-21swapper/2210:45:0815
116499916031,128cyclictest0-21swapper/2209:44:1315
116499915930,84cyclictest0-21swapper/2209:21:1515
116499915830,78cyclictest0-21swapper/2212:29:5315
116229915820,105cyclictest0-21swapper/1810:45:3610
116499915426,110cyclictest0-21swapper/2211:35:2215
116499915425,108cyclictest0-21swapper/2208:35:1715
115909915262,46cyclictest151rcu_preempt12:25:285
116499915130,67cyclictest0-21swapper/2210:31:1515
116499915130,67cyclictest0-21swapper/2210:31:1415
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional