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2025-07-12 - 12:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackcslot8.osadl.org (updated Sat Jul 12, 2025 00:49:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2482913210,312ptp4l0-21swapper/119:09:421
129582208200,6sleep110-21swapper/1119:05:203
143042194187,6sleep20-21swapper/219:07:5212
157899916257,104cyclictest0-21swapper/2421:30:2417
157069916228,89cyclictest0-21swapper/420:30:1826
157069915710,91cyclictest151rcu_preempt22:38:0426
157309915354,95cyclictest0-21swapper/923:29:0031
1570099153152,1cyclictest151rcu_preempt22:21:3312
157899915052,51cyclictest0-21swapper/2423:35:2817
1573099143142,0cyclictest70-21ksoftirqd/921:31:5731
157429914154,61cyclictest0-21swapper/1223:37:404
15742991410,84cyclictest0-21swapper/1221:13:064
157489914012,69cyclictest151rcu_preempt22:49:556
157489914012,69cyclictest151rcu_preempt22:49:546
157429914050,58cyclictest0-21swapper/1222:34:524
15760991390,83cyclictest0-21swapper/1720:56:509
157429913955,59cyclictest0-21swapper/1223:57:254
157429913931,68cyclictest0-21swapper/1220:05:194
157429913929,67cyclictest0-21swapper/1222:50:254
157429913923,72cyclictest0-21swapper/1221:16:484
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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