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2025-06-12 - 23:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Thu Jun 12, 2025 12:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
534299241,20cyclictest0-21swapper/108:45:171
5343992314,0cyclictest0-21swapper/212:25:122
534199230,5cyclictest0-21swapper/009:10:020
5343992213,0cyclictest0-21swapper/211:05:042
534199220,21cyclictest0-21swapper/011:53:320
534199220,18cyclictest0-21swapper/008:08:110
534199220,18cyclictest0-21swapper/008:08:100
534199210,16cyclictest0-21swapper/011:21:450
534299200,3cyclictest0-21swapper/110:14:441
5341992010,5cyclictest0-21swapper/009:25:200
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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