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2025-07-01 - 03:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Mon Jun 30, 2025 12:46:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1257799230,22cyclictest0-21swapper/010:45:150
1258299220,5cyclictest0-21swapper/107:20:011
1258699210,17cyclictest0-21swapper/208:54:472
12582992117,3cyclictest2079-21systemd-udevd11:57:071
12582992117,3cyclictest2079-21systemd-udevd11:57:061
12577992121,0cyclictest0-21swapper/011:15:140
1258699200,17cyclictest0-21swapper/210:15:192
1258299201,18cyclictest0-21swapper/110:15:231
1257799200,19cyclictest0-21swapper/011:20:210
1258699193,1cyclictest0-21swapper/212:07:262
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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