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2024-06-24 - 11:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Mon Jun 24, 2024 00:45:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2915199365364,1cyclictest0-21swapper/219:13:022
2915199363359,2cyclictest0-21swapper/200:33:022
2915199363358,4cyclictest0-21swapper/219:50:022
2914199362353,0cyclictest0-21swapper/023:29:020
2915199361358,3cyclictest0-21swapper/223:29:022
2914199361351,1cyclictest0-21swapper/000:06:020
2915199358356,2cyclictest0-21swapper/200:06:022
2915199358356,0cyclictest0-21swapper/220:54:022
2915199355353,2cyclictest0-21swapper/220:17:022
2915199354353,0cyclictest0-21swapper/221:58:022
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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