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2025-07-05 - 18:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sat Jul 05, 2025 12:45:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2847191770,15ptp4l0-21swapper/312:35:283
2847191770,15ptp4l0-21swapper/312:35:283
2847191710,3ptp4l0-21swapper/209:05:332
2847191680,5ptp4l0-21swapper/309:50:113
138432670,4sleep00-21swapper/008:45:190
1017996230,4cyclictest25-21ksoftirqd/108:20:001
2847191610,17ptp4l25-21ksoftirqd/108:20:231
2847191600,15ptp4l0-21swapper/211:40:302
2847191590,4ptp4l0-21swapper/011:05:270
1017995923,9cyclictest25-21ksoftirqd/112:10:251
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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