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2023-12-11 - 01:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Sun Dec 10, 2023 12:46:08)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1176911660,63ptp4l216-21systemd-journal07:06:380
1176911440,15ptp4l0-21swapper/207:08:282
1176911330,41ptp4l4815-21rs:main1
1176911070,7ptp4l0-21swapper/307:06:153
216152780,5sleep14813-21in:imuxsock11:35:401
117691750,2ptp4l0-21swapper/211:51:302
117691740,2ptp4l0-21swapper/310:54:583
117691730,35ptp4l9-21ksoftirqd/011:35:200
117691730,2ptp4l0-21swapper/307:49:573
117691730,2ptp4l0-21swapper/210:42:342
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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