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2024-04-26 - 08:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot4.osadl.org (updated Fri Apr 26, 2024 00:46:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1299911890,109ptp4l401ktimersoftd/319:08:223
603121780,9sleep3970799cyclictest23:35:143
603121780,9sleep3970799cyclictest23:35:143
649921250,8sleep2970699cyclictest20:10:122
255922940,8sleep0970499cyclictest00:15:220
90712803,64sleep20-21swapper/219:05:352
93322782,19sleep00-21swapper/019:08:520
9704997735,7cyclictest9-21ksoftirqd/023:50:210
9704997633,8cyclictest9-21ksoftirqd/023:15:160
9704997533,7cyclictest9-21ksoftirqd/023:35:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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